--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_ll_fmc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 24-March-2015\r
+ * @brief FMC Low Layer HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Flexible Memory Controller (FMC) peripheral memories:\r
+ * + Initialization/de-initialization functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### FMC peripheral features #####\r
+ ==============================================================================\r
+ [..] The Flexible memory controller (FMC) includes three memory controllers:\r
+ (+) The NOR/PSRAM memory controller\r
+ (+) The NAND memory controller\r
+ (+) The Synchronous DRAM (SDRAM) controller \r
+ \r
+ [..] The FMC functional block makes the interface with synchronous and asynchronous static\r
+ memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:\r
+ (+) to translate AHB transactions into the appropriate external device protocol\r
+ (+) to meet the access time requirements of the external memory devices\r
+ \r
+ [..] All external memories share the addresses, data and control signals with the controller.\r
+ Each external device is accessed by means of a unique Chip Select. The FMC performs\r
+ only one access at a time to an external device.\r
+ The main features of the FMC controller are the following:\r
+ (+) Interface with static-memory mapped devices including:\r
+ (++) Static random access memory (SRAM)\r
+ (++) Read-only memory (ROM)\r
+ (++) NOR Flash memory/OneNAND Flash memory\r
+ (++) PSRAM (4 memory banks)\r
+ (++) 16-bit PC Card compatible devices\r
+ (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of\r
+ data\r
+ (+) Interface with synchronous DRAM (SDRAM) memories\r
+ (+) Independent Chip Select control for each memory bank\r
+ (+) Independent configuration for each memory bank\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FMC_LL FMC Low Layer\r
+ * @brief FMC driver modules\r
+ * @{\r
+ */\r
+\r
+#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions\r
+ * @brief NORSRAM Controller functions \r
+ *\r
+ @verbatim \r
+ ============================================================================== \r
+ ##### How to use NORSRAM device driver #####\r
+ ==============================================================================\r
+ \r
+ [..] \r
+ This driver contains a set of APIs to interface with the FMC NORSRAM banks in order\r
+ to run the NORSRAM external devices.\r
+ \r
+ (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() \r
+ (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()\r
+ (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()\r
+ (+) FMC NORSRAM bank extended timing configuration using the function \r
+ FMC_NORSRAM_Extended_Timing_Init()\r
+ (+) FMC NORSRAM bank enable/disable write operation using the functions\r
+ FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()\r
+ \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de_initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the FMC NORSRAM interface\r
+ (+) De-initialize the FMC NORSRAM interface \r
+ (+) Configure the FMC clock and associated GPIOs \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initialize the FMC_NORSRAM device according to the specified\r
+ * control parameters in the FMC_NORSRAM_InitTypeDef\r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param Init: Pointer to NORSRAM Initialization structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)\r
+{ \r
+ uint32_t tmpr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));\r
+ assert_param(IS_FMC_MUX(Init->DataAddressMux));\r
+ assert_param(IS_FMC_MEMORY(Init->MemoryType));\r
+ assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));\r
+ assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));\r
+ assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));\r
+ assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));\r
+ assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));\r
+ assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));\r
+ assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));\r
+ assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));\r
+ assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));\r
+ assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); \r
+ assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));\r
+ assert_param(IS_FMC_PAGESIZE(Init->PageSize));\r
+\r
+ /* Get the BTCR register value */\r
+ tmpr = Device->BTCR[Init->NSBank];\r
+ \r
+ /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,\r
+ WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */\r
+ tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \\r
+ FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \\r
+ FMC_BCR1_WAITPOL | FMC_BCR1_CPSIZE | FMC_BCR1_WAITCFG | \\r
+ FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \\r
+ FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS));\r
+ \r
+ /* Set NORSRAM device control parameters */\r
+ tmpr |= (uint32_t)(Init->DataAddressMux |\\r
+ Init->MemoryType |\\r
+ Init->MemoryDataWidth |\\r
+ Init->BurstAccessMode |\\r
+ Init->WaitSignalPolarity |\\r
+ Init->WaitSignalActive |\\r
+ Init->WriteOperation |\\r
+ Init->WaitSignal |\\r
+ Init->ExtendedMode |\\r
+ Init->AsynchronousWait |\\r
+ Init->WriteBurst |\\r
+ Init->ContinuousClock |\\r
+ Init->PageSize |\\r
+ Init->WriteFifo);\r
+ \r
+ if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)\r
+ {\r
+ tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;\r
+ }\r
+ \r
+ Device->BTCR[Init->NSBank] = tmpr;\r
+\r
+ /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */\r
+ if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))\r
+ { \r
+ Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE; \r
+ Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\\r
+ Init->ContinuousClock);\r
+ }\r
+ if(Init->NSBank != FMC_NORSRAM_BANK1)\r
+ {\r
+ Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); \r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief DeInitialize the FMC_NORSRAM peripheral \r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param ExDevice: Pointer to NORSRAM extended mode device instance \r
+ * @param Bank: NORSRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));\r
+ \r
+ /* Disable the FMC_NORSRAM device */\r
+ __FMC_NORSRAM_DISABLE(Device, Bank);\r
+ \r
+ /* De-initialize the FMC_NORSRAM device */\r
+ /* FMC_NORSRAM_BANK1 */\r
+ if(Bank == FMC_NORSRAM_BANK1)\r
+ {\r
+ Device->BTCR[Bank] = 0x000030DB; \r
+ }\r
+ /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */\r
+ else\r
+ { \r
+ Device->BTCR[Bank] = 0x000030D2; \r
+ }\r
+ \r
+ Device->BTCR[Bank + 1] = 0x0FFFFFFF;\r
+ ExDevice->BWTR[Bank] = 0x0FFFFFFF;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initialize the FMC_NORSRAM Timing according to the specified\r
+ * parameters in the FMC_NORSRAM_TimingTypeDef\r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param Timing: Pointer to NORSRAM Timing structure\r
+ * @param Bank: NORSRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)\r
+{\r
+ uint32_t tmpr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));\r
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));\r
+ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));\r
+ assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));\r
+ assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));\r
+ assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));\r
+ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));\r
+ \r
+ /* Get the BTCR register value */\r
+ tmpr = Device->BTCR[Bank + 1];\r
+\r
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */\r
+ tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \\r
+ FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \\r
+ FMC_BTR1_ACCMOD));\r
+ \r
+ /* Set FMC_NORSRAM device timing parameters */ \r
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\\r
+ ((Timing->AddressHoldTime) << 4) |\\r
+ ((Timing->DataSetupTime) << 8) |\\r
+ ((Timing->BusTurnAroundDuration) << 16) |\\r
+ (((Timing->CLKDivision)-1) << 20) |\\r
+ (((Timing->DataLatency)-2) << 24) |\\r
+ (Timing->AccessMode)\r
+ );\r
+ \r
+ Device->BTCR[Bank + 1] = tmpr;\r
+ \r
+ /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */\r
+ if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))\r
+ {\r
+ tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20)); \r
+ tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);\r
+ Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;\r
+ } \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified\r
+ * parameters in the FMC_NORSRAM_TimingTypeDef\r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param Timing: Pointer to NORSRAM Timing structure\r
+ * @param Bank: NORSRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)\r
+{ \r
+ uint32_t tmpr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));\r
+ \r
+ /* Set NORSRAM device timing register for write configuration, if extended mode is used */\r
+ if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); \r
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));\r
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));\r
+ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));\r
+ assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));\r
+ assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));\r
+ assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));\r
+ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Bank)); \r
+ \r
+ /* Get the BWTR register value */\r
+ tmpr = Device->BWTR[Bank];\r
+\r
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */\r
+ tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \\r
+ FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));\r
+ \r
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\\r
+ ((Timing->AddressHoldTime) << 4) |\\r
+ ((Timing->DataSetupTime) << 8) |\\r
+ ((Timing->BusTurnAroundDuration) << 16) |\\r
+ (Timing->AccessMode));\r
+\r
+ Device->BWTR[Bank] = tmpr;\r
+ }\r
+ else\r
+ {\r
+ Device->BWTR[Bank] = 0x0FFFFFFF;\r
+ } \r
+ \r
+ return HAL_OK; \r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2\r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### FMC_NORSRAM Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the FMC NORSRAM interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables dynamically FMC_NORSRAM write operation.\r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param Bank: NORSRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));\r
+ \r
+ /* Enable write operation */\r
+ Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; \r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically FMC_NORSRAM write operation.\r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param Bank: NORSRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));\r
+ \r
+ /* Disable write operation */\r
+ Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; \r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions\r
+ * @brief NAND Controller functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use NAND device driver #####\r
+ ==============================================================================\r
+ [..]\r
+ This driver contains a set of APIs to interface with the FMC NAND banks in order\r
+ to run the NAND external devices.\r
+ \r
+ (+) FMC NAND bank reset using the function FMC_NAND_DeInit() \r
+ (+) FMC NAND bank control configuration using the function FMC_NAND_Init()\r
+ (+) FMC NAND bank common space timing configuration using the function \r
+ FMC_NAND_CommonSpace_Timing_Init()\r
+ (+) FMC NAND bank attribute space timing configuration using the function \r
+ FMC_NAND_AttributeSpace_Timing_Init()\r
+ (+) FMC NAND bank enable/disable ECC correction feature using the functions\r
+ FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()\r
+ (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de_initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the FMC NAND interface\r
+ (+) De-initialize the FMC NAND interface \r
+ (+) Configure the FMC clock and associated GPIOs\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the FMC_NAND device according to the specified\r
+ * control parameters in the FMC_NAND_HandleTypeDef\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Init: Pointer to NAND Initialization structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)\r
+{\r
+ uint32_t tmpr = 0; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NAND_DEVICE(Device));\r
+ assert_param(IS_FMC_NAND_BANK(Init->NandBank));\r
+ assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));\r
+ assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));\r
+ assert_param(IS_FMC_ECC_STATE(Init->EccComputation));\r
+ assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));\r
+ assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));\r
+ assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); \r
+\r
+ /* Get the NAND bank 3 register value */\r
+ tmpr = Device->PCR;\r
+\r
+ /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */\r
+ tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \\r
+ FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \\r
+ FMC_PCR_TAR | FMC_PCR_ECCPS)); \r
+ /* Set NAND device control parameters */\r
+ tmpr |= (uint32_t)(Init->Waitfeature |\\r
+ FMC_PCR_MEMORY_TYPE_NAND |\\r
+ Init->MemoryDataWidth |\\r
+ Init->EccComputation |\\r
+ Init->ECCPageSize |\\r
+ ((Init->TCLRSetupTime) << 9) |\\r
+ ((Init->TARSetupTime) << 13)); \r
+ \r
+ /* NAND bank 3 registers configuration */\r
+ Device->PCR = tmpr;\r
+ \r
+ return HAL_OK;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Initializes the FMC_NAND Common space Timing according to the specified\r
+ * parameters in the FMC_NAND_PCC_TimingTypeDef\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Timing: Pointer to NAND timing structure\r
+ * @param Bank: NAND bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)\r
+{\r
+ uint32_t tmpr = 0; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NAND_DEVICE(Device));\r
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));\r
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));\r
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));\r
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));\r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+ \r
+ /* Get the NAND bank 3 register value */\r
+ tmpr = Device->PMEM;\r
+\r
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */\r
+ tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3 | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \\r
+ FMC_PMEM_MEMHIZ3)); \r
+ /* Set FMC_NAND device timing parameters */\r
+ tmpr |= (uint32_t)(Timing->SetupTime |\\r
+ ((Timing->WaitSetupTime) << 8) |\\r
+ ((Timing->HoldSetupTime) << 16) |\\r
+ ((Timing->HiZSetupTime) << 24)\r
+ );\r
+ \r
+ /* NAND bank 3 registers configuration */\r
+ Device->PMEM = tmpr;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Initializes the FMC_NAND Attribute space Timing according to the specified\r
+ * parameters in the FMC_NAND_PCC_TimingTypeDef\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Timing: Pointer to NAND timing structure\r
+ * @param Bank: NAND bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)\r
+{\r
+ uint32_t tmpr = 0; \r
+ \r
+ /* Check the parameters */ \r
+ assert_param(IS_FMC_NAND_DEVICE(Device)); \r
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));\r
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));\r
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));\r
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));\r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+ \r
+ /* Get the NAND bank 3 register value */\r
+ tmpr = Device->PATT;\r
+\r
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */\r
+ tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3 | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \\r
+ FMC_PATT_ATTHIZ3));\r
+ /* Set FMC_NAND device timing parameters */\r
+ tmpr |= (uint32_t)(Timing->SetupTime |\\r
+ ((Timing->WaitSetupTime) << 8) |\\r
+ ((Timing->HoldSetupTime) << 16) |\\r
+ ((Timing->HiZSetupTime) << 24));\r
+ \r
+ /* NAND bank 3 registers configuration */\r
+ Device->PATT = tmpr;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the FMC_NAND device \r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Bank: NAND bank number\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)\r
+{\r
+ /* Check the parameters */ \r
+ assert_param(IS_FMC_NAND_DEVICE(Device)); \r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+ \r
+ /* Disable the NAND Bank */\r
+ __FMC_NAND_DISABLE(Device);\r
+ \r
+ /* Set the FMC_NAND_BANK3 registers to their reset values */\r
+ Device->PCR = 0x00000018;\r
+ Device->SR = 0x00000040;\r
+ Device->PMEM = 0xFCFCFCFC;\r
+ Device->PATT = 0xFCFCFCFC; \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_FMC_NAND_Group3 Control functions \r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### FMC_NAND Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the FMC NAND interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+ \r
+/**\r
+ * @brief Enables dynamically FMC_NAND ECC feature.\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Bank: NAND bank number\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)\r
+{\r
+ /* Check the parameters */ \r
+ assert_param(IS_FMC_NAND_DEVICE(Device)); \r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+ \r
+ /* Enable ECC feature */\r
+ Device->PCR |= FMC_PCR_ECCEN;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+\r
+/**\r
+ * @brief Disables dynamically FMC_NAND ECC feature.\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Bank: NAND bank number\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) \r
+{ \r
+ /* Check the parameters */ \r
+ assert_param(IS_FMC_NAND_DEVICE(Device)); \r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+ \r
+ /* Disable ECC feature */\r
+ Device->PCR &= ~FMC_PCR_ECCEN;\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically FMC_NAND ECC feature.\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param ECCval: Pointer to ECC value\r
+ * @param Bank: NAND bank number\r
+ * @param Timeout: Timeout wait value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Check the parameters */ \r
+ assert_param(IS_FMC_NAND_DEVICE(Device)); \r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+\r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait until FIFO is empty */\r
+ while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ }\r
+ \r
+ /* Get the ECCR register value */\r
+ *ECCval = (uint32_t)Device->ECCR;\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_LL_SDRAM\r
+ * @brief SDRAM Controller functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use SDRAM device driver #####\r
+ ==============================================================================\r
+ [..] \r
+ This driver contains a set of APIs to interface with the FMC SDRAM banks in order\r
+ to run the SDRAM external devices.\r
+ \r
+ (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() \r
+ (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()\r
+ (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()\r
+ (+) FMC SDRAM bank enable/disable write operation using the functions\r
+ FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() \r
+ (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de_initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the FMC SDRAM interface\r
+ (+) De-initialize the FMC SDRAM interface \r
+ (+) Configure the FMC clock and associated GPIOs\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the FMC_SDRAM device according to the specified\r
+ * control parameters in the FMC_SDRAM_InitTypeDef\r
+ * @param Device: Pointer to SDRAM device instance\r
+ * @param Init: Pointer to SDRAM Initialization structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)\r
+{\r
+ uint32_t tmpr1 = 0;\r
+ uint32_t tmpr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));\r
+ assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));\r
+ assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));\r
+ assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));\r
+ assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));\r
+ assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));\r
+ assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));\r
+ assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));\r
+ assert_param(IS_FMC_READ_BURST(Init->ReadBurst));\r
+ assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); \r
+\r
+ /* Set SDRAM bank configuration parameters */\r
+ if (Init->SDBank != FMC_SDRAM_BANK2) \r
+ { \r
+ tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];\r
+ \r
+ /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */\r
+ tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \\r
+ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \\r
+ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));\r
+\r
+ tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\\r
+ Init->RowBitsNumber |\\r
+ Init->MemoryDataWidth |\\r
+ Init->InternalBankNumber |\\r
+ Init->CASLatency |\\r
+ Init->WriteProtection |\\r
+ Init->SDClockPeriod |\\r
+ Init->ReadBurst |\\r
+ Init->ReadPipeDelay\r
+ ); \r
+ Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;\r
+ }\r
+ else /* FMC_Bank2_SDRAM */ \r
+ {\r
+ tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];\r
+ \r
+ /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */\r
+ tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \\r
+ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \\r
+ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));\r
+ \r
+ tmpr1 |= (uint32_t)(Init->SDClockPeriod |\\r
+ Init->ReadBurst |\\r
+ Init->ReadPipeDelay); \r
+ \r
+ tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];\r
+ \r
+ /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */\r
+ tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \\r
+ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \\r
+ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));\r
+\r
+ tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\\r
+ Init->RowBitsNumber |\\r
+ Init->MemoryDataWidth |\\r
+ Init->InternalBankNumber |\\r
+ Init->CASLatency |\\r
+ Init->WriteProtection);\r
+\r
+ Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;\r
+ Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;\r
+ } \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the FMC_SDRAM device timing according to the specified\r
+ * parameters in the FMC_SDRAM_TimingTypeDef\r
+ * @param Device: Pointer to SDRAM device instance\r
+ * @param Timing: Pointer to SDRAM Timing structure\r
+ * @param Bank: SDRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)\r
+{\r
+ uint32_t tmpr1 = 0;\r
+ uint32_t tmpr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));\r
+ assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));\r
+ assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));\r
+ assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));\r
+ assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));\r
+ assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));\r
+ assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));\r
+ assert_param(IS_FMC_SDRAM_BANK(Bank));\r
+ \r
+ /* Set SDRAM device timing parameters */ \r
+ if (Bank != FMC_SDRAM_BANK2) \r
+ { \r
+ tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];\r
+ \r
+ /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */\r
+ tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \\r
+ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \\r
+ FMC_SDTR1_TRCD));\r
+ \r
+ tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\\r
+ (((Timing->ExitSelfRefreshDelay)-1) << 4) |\\r
+ (((Timing->SelfRefreshTime)-1) << 8) |\\r
+ (((Timing->RowCycleDelay)-1) << 12) |\\r
+ (((Timing->WriteRecoveryTime)-1) <<16) |\\r
+ (((Timing->RPDelay)-1) << 20) |\\r
+ (((Timing->RCDDelay)-1) << 24));\r
+ Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;\r
+ }\r
+ else /* FMC_Bank2_SDRAM */\r
+ { \r
+ tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];\r
+ \r
+ /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */\r
+ tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \\r
+ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \\r
+ FMC_SDTR1_TRCD));\r
+ \r
+ tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\\r
+ (((Timing->ExitSelfRefreshDelay)-1) << 4) |\\r
+ (((Timing->SelfRefreshTime)-1) << 8) |\\r
+ (((Timing->WriteRecoveryTime)-1) <<16) |\\r
+ (((Timing->RCDDelay)-1) << 24)); \r
+ \r
+ tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];\r
+ \r
+ /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */\r
+ tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \\r
+ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \\r
+ FMC_SDTR1_TRCD));\r
+ tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\\r
+ (((Timing->RPDelay)-1) << 20)); \r
+\r
+ Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;\r
+ Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;\r
+ } \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the FMC_SDRAM peripheral \r
+ * @param Device: Pointer to SDRAM device instance\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_SDRAM_BANK(Bank));\r
+ \r
+ /* De-initialize the SDRAM device */\r
+ Device->SDCR[Bank] = 0x000002D0;\r
+ Device->SDTR[Bank] = 0x0FFFFFFF; \r
+ Device->SDCMR = 0x00000000;\r
+ Device->SDRTR = 0x00000000;\r
+ Device->SDSR = 0x00000000;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2\r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### FMC_SDRAM Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the FMC SDRAM interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables dynamically FMC_SDRAM write protection.\r
+ * @param Device: Pointer to SDRAM device instance\r
+ * @param Bank: SDRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_SDRAM_BANK(Bank));\r
+ \r
+ /* Enable write protection */\r
+ Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically FMC_SDRAM write protection.\r
+ * @param hsdram: FMC_SDRAM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_SDRAM_BANK(Bank));\r
+ \r
+ /* Disable write protection */\r
+ Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;\r
+ \r
+ return HAL_OK;\r
+}\r
+ \r
+/**\r
+ * @brief Send Command to the FMC SDRAM bank\r
+ * @param Device: Pointer to SDRAM device instance\r
+ * @param Command: Pointer to SDRAM command structure \r
+ * @param Timing: Pointer to SDRAM Timing structure\r
+ * @param Timeout: Timeout wait value\r
+ * @retval HAL state\r
+ */ \r
+HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)\r
+{\r
+ __IO uint32_t tmpr = 0;\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));\r
+ assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));\r
+ assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));\r
+ assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); \r
+\r
+ /* Set command register */\r
+ tmpr = (uint32_t)((Command->CommandMode) |\\r
+ (Command->CommandTarget) |\\r
+ (((Command->AutoRefreshNumber)-1) << 5) |\\r
+ ((Command->ModeRegisterDefinition) << 9)\r
+ );\r
+ \r
+ Device->SDCMR = tmpr;\r
+\r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ /* wait until command is send */\r
+ while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Program the SDRAM Memory Refresh rate.\r
+ * @param Device: Pointer to SDRAM device instance \r
+ * @param RefreshRate: The SDRAM refresh rate value. \r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_REFRESH_RATE(RefreshRate));\r
+ \r
+ /* Set the refresh rate in command register */\r
+ Device->SDRTR |= (RefreshRate<<1);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.\r
+ * @param Device: Pointer to SDRAM device instance \r
+ * @param AutoRefreshNumber: Specifies the auto Refresh number. \r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));\r
+ \r
+ /* Set the Auto-refresh number in command register */\r
+ Device->SDCMR |= (AutoRefreshNumber << 5); \r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Returns the indicated FMC SDRAM bank mode status.\r
+ * @param Device: Pointer to SDRAM device instance \r
+ * @param Bank: Defines the FMC SDRAM bank. This parameter can be \r
+ * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. \r
+ * @retval The FMC SDRAM bank mode status, could be on of the following values:\r
+ * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or \r
+ * FMC_SDRAM_POWER_DOWN_MODE. \r
+ */\r
+uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_SDRAM_BANK(Bank));\r
+\r
+ /* Get the corresponding bank mode */\r
+ if(Bank == FMC_SDRAM_BANK1)\r
+ {\r
+ tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); \r
+ }\r
+ else\r
+ {\r
+ tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);\r
+ }\r
+ \r
+ /* Return the mode status */\r
+ return tmpreg;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / blobdiff