--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_ll_usb.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 24-March-2015\r
+ * @brief USB Low Layer HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the USB Peripheral Controller:\r
+ * + Initialization/de-initialization functions\r
+ * + I/O operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.\r
+ \r
+ (#) Call USB_CoreInit() API to initialize the USB Core peripheral.\r
+\r
+ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_LL_USB_DRIVER\r
+ * @{\r
+ */\r
+\r
+#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);\r
+\r
+/** @defgroup PCD_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LL_USB_Group1 Initialization/de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization/de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the USB Core\r
+ * @param USBx: USB Instance\r
+ * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains\r
+ * the configuration information for the specified USBx peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
+{\r
+ if (cfg.phy_itface == USB_OTG_ULPI_PHY)\r
+ {\r
+ \r
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\r
+\r
+ /* Init The ULPI Interface */\r
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);\r
+ \r
+ /* Select vbus source */\r
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);\r
+ if(cfg.use_external_vbus == 1)\r
+ {\r
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;\r
+ }\r
+ /* Reset after a PHY select */\r
+ USB_CoreReset(USBx); \r
+ }\r
+ else /* FS interface (embedded Phy) */\r
+ {\r
+ \r
+ /* Select FS Embedded PHY */\r
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;\r
+ \r
+ /* Reset after a PHY select and set Host mode */\r
+ USB_CoreReset(USBx);\r
+ \r
+ /* Deactivate the power down*/\r
+ USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;\r
+ }\r
+ \r
+ if(cfg.dma_enable == ENABLE)\r
+ {\r
+ USBx->GAHBCFG |= (USB_OTG_GAHBCFG_HBSTLEN_1 | USB_OTG_GAHBCFG_HBSTLEN_2);\r
+ USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;\r
+ } \r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_EnableGlobalInt\r
+ * Enables the controller's Global Int in the AHB Config reg\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief USB_DisableGlobalInt\r
+ * Disable the controller's Global Int in the AHB Config reg\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;\r
+ return HAL_OK;\r
+}\r
+ \r
+/**\r
+ * @brief USB_SetCurrentMode : Set functional mode\r
+ * @param USBx : Selected device\r
+ * @param mode : current core mode\r
+ * This parameter can be one of the these values:\r
+ * @arg USB_OTG_DEVICE_MODE: Peripheral mode\r
+ * @arg USB_OTG_HOST_MODE: Host mode\r
+ * @arg USB_OTG_DRD_MODE: Dual Role Device mode \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)\r
+{\r
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); \r
+ \r
+ if ( mode == USB_OTG_HOST_MODE)\r
+ {\r
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; \r
+ }\r
+ else if ( mode == USB_OTG_DEVICE_MODE)\r
+ {\r
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; \r
+ }\r
+ HAL_Delay(50);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DevInit : Initializes the USB_OTG controller registers \r
+ * for device mode\r
+ * @param USBx : Selected device\r
+ * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains\r
+ * the configuration information for the specified USBx peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
+{\r
+ uint32_t i = 0;\r
+\r
+ /*Activate VBUS Sensing B */\r
+ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;\r
+ \r
+ if (cfg.vbus_sensing_enable == 0)\r
+ {\r
+ /*Desactivate VBUS Sensing B */\r
+ USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN;\r
+ \r
+ /* B-peripheral session valid override enable*/ \r
+ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;\r
+ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;\r
+ }\r
+ \r
+ /* Restart the Phy Clock */\r
+ USBx_PCGCCTL = 0;\r
+\r
+ /* Device mode configuration */\r
+ USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;\r
+ \r
+ if(cfg.phy_itface == USB_OTG_ULPI_PHY)\r
+ {\r
+ if(cfg.speed == USB_OTG_SPEED_HIGH)\r
+ { \r
+ /* Set High speed phy */\r
+ USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);\r
+ }\r
+ else \r
+ {\r
+ /* set High speed phy in Full speed mode */\r
+ USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set Full speed phy */\r
+ USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);\r
+ }\r
+\r
+ /* Flush the FIFOs */\r
+ USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */\r
+ USB_FlushRxFifo(USBx);\r
+\r
+ \r
+ /* Clear all pending Device Interrupts */\r
+ USBx_DEVICE->DIEPMSK = 0;\r
+ USBx_DEVICE->DOEPMSK = 0;\r
+ USBx_DEVICE->DAINT = 0xFFFFFFFF;\r
+ USBx_DEVICE->DAINTMSK = 0;\r
+ \r
+ for (i = 0; i < cfg.dev_endpoints; i++)\r
+ {\r
+ if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)\r
+ {\r
+ USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);\r
+ }\r
+ else\r
+ {\r
+ USBx_INEP(i)->DIEPCTL = 0;\r
+ }\r
+ \r
+ USBx_INEP(i)->DIEPTSIZ = 0;\r
+ USBx_INEP(i)->DIEPINT = 0xFF;\r
+ }\r
+ \r
+ for (i = 0; i < cfg.dev_endpoints; i++)\r
+ {\r
+ if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)\r
+ {\r
+ USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);\r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(i)->DOEPCTL = 0;\r
+ }\r
+ \r
+ USBx_OUTEP(i)->DOEPTSIZ = 0;\r
+ USBx_OUTEP(i)->DOEPINT = 0xFF;\r
+ }\r
+ \r
+ USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);\r
+ \r
+ if (cfg.dma_enable == 1)\r
+ {\r
+ /*Set threshold parameters */\r
+ USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);\r
+ USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);\r
+ \r
+ i= USBx_DEVICE->DTHRCTL;\r
+ }\r
+ \r
+ /* Disable all interrupts. */\r
+ USBx->GINTMSK = 0;\r
+ \r
+ /* Clear any pending interrupts */\r
+ USBx->GINTSTS = 0xBFFFFFFF;\r
+\r
+ /* Enable the common interrupts */\r
+ if (cfg.dma_enable == DISABLE)\r
+ {\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; \r
+ }\r
+ \r
+ /* Enable interrupts matching to the Device mode ONLY */\r
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\\r
+ USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\\r
+ USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\\r
+ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);\r
+ \r
+ if(cfg.Sof_enable)\r
+ {\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;\r
+ }\r
+\r
+ if (cfg.vbus_sensing_enable == ENABLE)\r
+ {\r
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); \r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO\r
+ * @param USBx : Selected device\r
+ * @param num : FIFO number\r
+ * This parameter can be a value from 1 to 15\r
+ 15 means Flush all Tx FIFOs\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )\r
+{\r
+ uint32_t count = 0;\r
+ \r
+ USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 5 )); \r
+ \r
+ do\r
+ {\r
+ if (++count > 200000)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief USB_FlushRxFifo : Flush Rx FIFO\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t count = 0;\r
+ \r
+ USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;\r
+ \r
+ do\r
+ {\r
+ if (++count > 200000)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register \r
+ * depending the PHY type and the enumeration speed of the device.\r
+ * @param USBx : Selected device\r
+ * @param speed : device speed\r
+ * This parameter can be one of the these values:\r
+ * @arg USB_OTG_SPEED_HIGH: High speed mode\r
+ * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode\r
+ * @arg USB_OTG_SPEED_FULL: Full speed mode\r
+ * @arg USB_OTG_SPEED_LOW: Low speed mode\r
+ * @retval Hal status\r
+ */\r
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)\r
+{\r
+ USBx_DEVICE->DCFG |= speed;\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_GetDevSpeed :Return the Dev Speed \r
+ * @param USBx : Selected device\r
+ * @retval speed : device speed\r
+ * This parameter can be one of the these values:\r
+ * @arg USB_OTG_SPEED_HIGH: High speed mode\r
+ * @arg USB_OTG_SPEED_FULL: Full speed mode\r
+ * @arg USB_OTG_SPEED_LOW: Low speed mode\r
+ */\r
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint8_t speed = 0;\r
+ \r
+ if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)\r
+ {\r
+ speed = USB_OTG_SPEED_HIGH;\r
+ }\r
+ else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||\r
+ ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))\r
+ {\r
+ speed = USB_OTG_SPEED_FULL;\r
+ }\r
+ else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)\r
+ {\r
+ speed = USB_OTG_SPEED_LOW;\r
+ }\r
+ \r
+ return speed;\r
+}\r
+\r
+/**\r
+ * @brief Activate and configure an endpoint\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ if (ep->is_in == 1)\r
+ {\r
+ USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));\r
+ \r
+ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); \r
+ } \r
+\r
+ }\r
+ else\r
+ {\r
+ USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);\r
+ \r
+ if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));\r
+ } \r
+ }\r
+ return HAL_OK;\r
+}\r
+/**\r
+ * @brief Activate and configure a dedicated endpoint\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ static __IO uint32_t debug = 0;\r
+ \r
+ /* Read DEPCTLn register */\r
+ if (ep->is_in == 1)\r
+ {\r
+ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); \r
+ } \r
+ \r
+ \r
+ debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); \r
+ \r
+ USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));\r
+ }\r
+ else\r
+ {\r
+ if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));\r
+ \r
+ debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE);\r
+ debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;\r
+ debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); \r
+ } \r
+ \r
+ USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+/**\r
+ * @brief De-activate and de-initialize an endpoint\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ /* Read DEPCTLn register */\r
+ if (ep->is_in == 1)\r
+ {\r
+ USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));\r
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); \r
+ USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; \r
+ }\r
+ else\r
+ {\r
+\r
+ USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));\r
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); \r
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief De-activate and de-initialize a dedicated endpoint\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ /* Read DEPCTLn register */\r
+ if (ep->is_in == 1)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;\r
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));\r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; \r
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_EPStartXfer : setup and starts a transfer over an EP\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of the these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)\r
+{\r
+ uint16_t pktcnt = 0;\r
+ \r
+ /* IN endpoint */\r
+ if (ep->is_in == 1)\r
+ {\r
+ /* Zero Length Packet? */\r
+ if (ep->xfer_len == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); \r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); \r
+ }\r
+ else\r
+ {\r
+ /* Program the transfer size and packet count\r
+ * as follows: xfersize = N * maxpacket +\r
+ * short_packet pktcnt = N + (short_packet\r
+ * exist ? 1 : 0)\r
+ */\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); \r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;\r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); \r
+ \r
+ if (ep->type == EP_TYPE_ISOC)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); \r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); \r
+ } \r
+ }\r
+\r
+ if (dma == 1)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);\r
+ }\r
+ else\r
+ {\r
+ if (ep->type != EP_TYPE_ISOC)\r
+ {\r
+ /* Enable the Tx FIFO Empty Interrupt for this EP */\r
+ if (ep->xfer_len > 0)\r
+ {\r
+ USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num;\r
+ }\r
+ }\r
+ }\r
+\r
+ if (ep->type == EP_TYPE_ISOC)\r
+ {\r
+ if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;\r
+ }\r
+ else\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;\r
+ }\r
+ } \r
+ \r
+ /* EP enable, IN data in FIFO */\r
+ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\r
+ \r
+ if (ep->type == EP_TYPE_ISOC)\r
+ {\r
+ USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma); \r
+ } \r
+ }\r
+ else /* OUT endpoint */\r
+ {\r
+ /* Program the transfer size and packet count as follows:\r
+ * pktcnt = N\r
+ * xfersize = N * maxpacket\r
+ */ \r
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); \r
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); \r
+ \r
+ if (ep->xfer_len == 0)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);\r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; \r
+ }\r
+ else\r
+ {\r
+ pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket; \r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19));\r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); \r
+ }\r
+\r
+ if (dma == 1)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;\r
+ }\r
+ \r
+ if (ep->type == EP_TYPE_ISOC)\r
+ {\r
+ if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;\r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;\r
+ }\r
+ }\r
+ /* EP enable */\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of the these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)\r
+{\r
+ /* IN endpoint */\r
+ if (ep->is_in == 1)\r
+ {\r
+ /* Zero Length Packet? */\r
+ if (ep->xfer_len == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); \r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); \r
+ }\r
+ else\r
+ {\r
+ /* Program the transfer size and packet count\r
+ * as follows: xfersize = N * maxpacket +\r
+ * short_packet pktcnt = N + (short_packet\r
+ * exist ? 1 : 0)\r
+ */\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); \r
+ \r
+ if(ep->xfer_len > ep->maxpacket)\r
+ {\r
+ ep->xfer_len = ep->maxpacket;\r
+ }\r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;\r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); \r
+ \r
+ }\r
+ \r
+ if (dma == 1)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);\r
+ }\r
+ else\r
+ {\r
+ /* Enable the Tx FIFO Empty Interrupt for this EP */\r
+ if (ep->xfer_len > 0)\r
+ {\r
+ USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num);\r
+ }\r
+ }\r
+ \r
+ /* EP enable, IN data in FIFO */\r
+ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); \r
+ }\r
+ else /* OUT endpoint */\r
+ {\r
+ /* Program the transfer size and packet count as follows:\r
+ * pktcnt = N\r
+ * xfersize = N * maxpacket\r
+ */\r
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); \r
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); \r
+ \r
+ if (ep->xfer_len > 0)\r
+ {\r
+ ep->xfer_len = ep->maxpacket;\r
+ }\r
+ \r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));\r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); \r
+ \r
+\r
+ if (dma == 1)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);\r
+ }\r
+ \r
+ /* EP enable */\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated \r
+ * with the EP/channel\r
+ * @param USBx : Selected device \r
+ * @param src : pointer to source buffer\r
+ * @param ch_ep_num : endpoint or host channel number\r
+ * @param len : Number of bytes to write\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of the these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)\r
+{\r
+ uint32_t count32b= 0 , i= 0;\r
+ \r
+ if (dma == 0)\r
+ {\r
+ count32b = (len + 3) / 4;\r
+ for (i = 0; i < count32b; i++, src += 4)\r
+ {\r
+ USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src);\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_ReadPacket : read a packet from the Tx FIFO associated \r
+ * with the EP/channel\r
+ * @param USBx : Selected device \r
+ * @param src : source pointer\r
+ * @param ch_ep_num : endpoint or host channel number\r
+ * @param len : Number of bytes to read\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of the these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @retval pointer to destination buffer\r
+ */\r
+void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)\r
+{\r
+ uint32_t i=0;\r
+ uint32_t count32b = (len + 3) / 4;\r
+ \r
+ for ( i = 0; i < count32b; i++, dest += 4 )\r
+ {\r
+ *(__packed uint32_t *)dest = USBx_DFIFO(0);\r
+ \r
+ }\r
+ return ((void *)dest);\r
+}\r
+\r
+/**\r
+ * @brief USB_EPSetStall : set a stall condition over an EP\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)\r
+{\r
+ if (ep->is_in == 1)\r
+ {\r
+ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); \r
+ } \r
+ USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;\r
+ }\r
+ else\r
+ {\r
+ if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); \r
+ } \r
+ USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief USB_EPClearStall : Clear a stall condition over an EP\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ if (ep->is_in == 1)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;\r
+ if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */\r
+ } \r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;\r
+ if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */\r
+ } \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_StopDevice : Stop the usb device mode\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t i;\r
+ \r
+ /* Clear Pending interrupt */\r
+ for (i = 0; i < 15 ; i++)\r
+ {\r
+ USBx_INEP(i)->DIEPINT = 0xFF;\r
+ USBx_OUTEP(i)->DOEPINT = 0xFF;\r
+ }\r
+ USBx_DEVICE->DAINT = 0xFFFFFFFF;\r
+ \r
+ /* Clear interrupt masks */\r
+ USBx_DEVICE->DIEPMSK = 0;\r
+ USBx_DEVICE->DOEPMSK = 0;\r
+ USBx_DEVICE->DAINTMSK = 0;\r
+ \r
+ /* Flush the FIFO */\r
+ USB_FlushRxFifo(USBx);\r
+ USB_FlushTxFifo(USBx , 0x10 ); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_SetDevAddress : Stop the usb device mode\r
+ * @param USBx : Selected device\r
+ * @param address : new device address to be assigned\r
+ * This parameter can be a value from 0 to 255\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)\r
+{\r
+ USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);\r
+ USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;\r
+ HAL_Delay(3);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ;\r
+ HAL_Delay(3);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief USB_ReadInterrupts: return the global USB interrupt status\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t v = 0;\r
+ \r
+ v = USBx->GINTSTS;\r
+ v &= USBx->GINTMSK;\r
+ return v; \r
+}\r
+\r
+/**\r
+ * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t v;\r
+ v = USBx_DEVICE->DAINT;\r
+ v &= USBx_DEVICE->DAINTMSK;\r
+ return ((v & 0xffff0000) >> 16);\r
+}\r
+\r
+/**\r
+ * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t v;\r
+ v = USBx_DEVICE->DAINT;\r
+ v &= USBx_DEVICE->DAINTMSK;\r
+ return ((v & 0xFFFF));\r
+}\r
+\r
+/**\r
+ * @brief Returns Device OUT EP Interrupt register\r
+ * @param USBx : Selected device\r
+ * @param epnum : endpoint number\r
+ * This parameter can be a value from 0 to 15\r
+ * @retval Device OUT EP Interrupt register\r
+ */\r
+uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)\r
+{\r
+ uint32_t v;\r
+ v = USBx_OUTEP(epnum)->DOEPINT;\r
+ v &= USBx_DEVICE->DOEPMSK;\r
+ return v;\r
+}\r
+\r
+/**\r
+ * @brief Returns Device IN EP Interrupt register\r
+ * @param USBx : Selected device\r
+ * @param epnum : endpoint number\r
+ * This parameter can be a value from 0 to 15\r
+ * @retval Device IN EP Interrupt register\r
+ */\r
+uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)\r
+{\r
+ uint32_t v, msk, emp;\r
+ \r
+ msk = USBx_DEVICE->DIEPMSK;\r
+ emp = USBx_DEVICE->DIEPEMPMSK;\r
+ msk |= ((emp >> epnum) & 0x1) << 7;\r
+ v = USBx_INEP(epnum)->DIEPINT & msk;\r
+ return v;\r
+}\r
+\r
+/**\r
+ * @brief USB_ClearInterrupts: clear a USB interrupt\r
+ * @param USBx : Selected device\r
+ * @param interrupt : interrupt flag\r
+ * @retval None\r
+ */\r
+void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)\r
+{\r
+ USBx->GINTSTS |= interrupt; \r
+}\r
+\r
+/**\r
+ * @brief Returns USB core mode\r
+ * @param USBx : Selected device\r
+ * @retval return core mode : Host or Device\r
+ * This parameter can be one of the these values:\r
+ * 0 : Host \r
+ * 1 : Device\r
+ */\r
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ return ((USBx->GINTSTS ) & 0x1);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Activate EP0 for Setup transactions\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ /* Set the MPS of the IN EP based on the enumeration speed */\r
+ USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;\r
+ \r
+ if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)\r
+ {\r
+ USBx_INEP(0)->DIEPCTL |= 3;\r
+ }\r
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Prepare the EP0 to start the first control setup\r
+ * @param USBx : Selected device\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of the these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @param psetup : pointer to setup packet\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)\r
+{\r
+ USBx_OUTEP(0)->DOEPTSIZ = 0;\r
+ USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;\r
+ USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8);\r
+ USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; \r
+ \r
+ if (dma == 1)\r
+ {\r
+ USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup;\r
+ /* EP enable */\r
+ USBx_OUTEP(0)->DOEPCTL = 0x80008000;\r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+\r
+/**\r
+ * @brief Reset the USB Core (needed after USB clock settings change)\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t count = 0;\r
+\r
+ /* Wait for AHB master IDLE state. */\r
+ do\r
+ {\r
+ if (++count > 200000)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);\r
+ \r
+ /* Core Soft Reset */\r
+ count = 0;\r
+ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;\r
+\r
+ do\r
+ {\r
+ if (++count > 200000)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief USB_HostInit : Initializes the USB OTG controller registers \r
+ * for Host mode \r
+ * @param USBx : Selected device\r
+ * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains\r
+ * the configuration information for the specified USBx peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
+{\r
+ uint32_t i;\r
+ \r
+ /* Restart the Phy Clock */\r
+ USBx_PCGCCTL = 0;\r
+ \r
+ /*Activate VBUS Sensing B */\r
+ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;\r
+ \r
+ /* Disable the FS/LS support mode only */\r
+ if((cfg.speed == USB_OTG_SPEED_FULL)&&\r
+ (USBx != USB_OTG_FS))\r
+ {\r
+ USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; \r
+ }\r
+ else\r
+ {\r
+ USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); \r
+ }\r
+\r
+ /* Make sure the FIFOs are flushed. */\r
+ USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */\r
+ USB_FlushRxFifo(USBx);\r
+\r
+ /* Clear all pending HC Interrupts */\r
+ for (i = 0; i < cfg.Host_channels; i++)\r
+ {\r
+ USBx_HC(i)->HCINT = 0xFFFFFFFF;\r
+ USBx_HC(i)->HCINTMSK = 0;\r
+ }\r
+ \r
+ /* Enable VBUS driving */\r
+ USB_DriveVbus(USBx, 1);\r
+ \r
+ HAL_Delay(200);\r
+ \r
+ /* Disable all interrupts. */\r
+ USBx->GINTMSK = 0;\r
+ \r
+ /* Clear any pending interrupts */\r
+ USBx->GINTSTS = 0xFFFFFFFF;\r
+\r
+ \r
+ if(USBx == USB_OTG_FS)\r
+ {\r
+ /* set Rx FIFO size */\r
+ USBx->GRXFSIZ = (uint32_t )0x80; \r
+ USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);\r
+ USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);\r
+\r
+ }\r
+\r
+ else\r
+ {\r
+ /* set Rx FIFO size */\r
+ USBx->GRXFSIZ = (uint32_t )0x200; \r
+ USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100 << 16)& USB_OTG_NPTXFD) | 0x200);\r
+ USBx->HPTXFSIZ = (uint32_t )(((0xE0 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300);\r
+ }\r
+ \r
+ /* Enable the common interrupts */\r
+ if (cfg.dma_enable == DISABLE)\r
+ {\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; \r
+ }\r
+ \r
+ /* Enable interrupts matching to the Host mode ONLY */\r
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\\r
+ USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\\r
+ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the \r
+ * HCFG register on the PHY type and set the right frame interval\r
+ * @param USBx : Selected device\r
+ * @param freq : clock frequency\r
+ * This parameter can be one of the these values:\r
+ * HCFG_48_MHZ : Full Speed 48 MHz Clock \r
+ * HCFG_6_MHZ : Low Speed 6 MHz Clock \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)\r
+{\r
+ USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);\r
+ USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);\r
+ \r
+ if (freq == HCFG_48_MHZ)\r
+ {\r
+ USBx_HOST->HFIR = (uint32_t)48000;\r
+ }\r
+ else if (freq == HCFG_6_MHZ)\r
+ {\r
+ USBx_HOST->HFIR = (uint32_t)6000;\r
+ } \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+* @brief USB_OTG_ResetPort : Reset Host Port\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ * @note : (1)The application must wait at least 10 ms\r
+ * before clearing the reset bit.\r
+ */\r
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ __IO uint32_t hprt0;\r
+ \r
+ hprt0 = USBx_HPRT0;\r
+ \r
+ hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\r
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r
+ \r
+ USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); \r
+ HAL_Delay (10); /* See Note #1 */\r
+ USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DriveVbus : activate or de-activate vbus\r
+ * @param state : VBUS state\r
+ * This parameter can be one of the these values:\r
+ * 0 : VBUS Active \r
+ * 1 : VBUS Inactive\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)\r
+{\r
+ __IO uint32_t hprt0;\r
+\r
+ hprt0 = USBx_HPRT0;\r
+ hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\r
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r
+ \r
+ if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))\r
+ {\r
+ USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); \r
+ }\r
+ if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))\r
+ {\r
+ USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); \r
+ }\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Return Host Core speed\r
+ * @param USBx : Selected device\r
+ * @retval speed : Host speed\r
+ * This parameter can be one of the these values:\r
+ * @arg USB_OTG_SPEED_HIGH: High speed mode\r
+ * @arg USB_OTG_SPEED_FULL: Full speed mode\r
+ * @arg USB_OTG_SPEED_LOW: Low speed mode\r
+ */\r
+uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ __IO uint32_t hprt0;\r
+ \r
+ hprt0 = USBx_HPRT0;\r
+ return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);\r
+}\r
+\r
+/**\r
+ * @brief Return Host Current Frame number\r
+ * @param USBx : Selected device\r
+ * @retval current frame number\r
+*/\r
+uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);\r
+}\r
+\r
+/**\r
+ * @brief Initialize a host channel\r
+ * @param USBx : Selected device\r
+ * @param ch_num : Channel number\r
+ * This parameter can be a value from 1 to 15\r
+ * @param epnum : Endpoint number\r
+ * This parameter can be a value from 1 to 15\r
+ * @param dev_address : Current device address\r
+ * This parameter can be a value from 0 to 255\r
+ * @param speed : Current device speed\r
+ * This parameter can be one of the these values:\r
+ * @arg USB_OTG_SPEED_HIGH: High speed mode\r
+ * @arg USB_OTG_SPEED_FULL: Full speed mode\r
+ * @arg USB_OTG_SPEED_LOW: Low speed mode\r
+ * @param ep_type : Endpoint Type\r
+ * This parameter can be one of the these values:\r
+ * @arg EP_TYPE_CTRL: Control type\r
+ * @arg EP_TYPE_ISOC: Isochronous type\r
+ * @arg EP_TYPE_BULK: Bulk type\r
+ * @arg EP_TYPE_INTR: Interrupt type\r
+ * @param mps : Max Packet Size\r
+ * This parameter can be a value from 0 to32K\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, \r
+ uint8_t ch_num,\r
+ uint8_t epnum,\r
+ uint8_t dev_address,\r
+ uint8_t speed,\r
+ uint8_t ep_type,\r
+ uint16_t mps)\r
+{\r
+ \r
+ /* Clear old interrupt conditions for this host channel. */\r
+ USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;\r
+ \r
+ /* Enable channel interrupts required for this transfer. */\r
+ switch (ep_type) \r
+ {\r
+ case EP_TYPE_CTRL:\r
+ case EP_TYPE_BULK:\r
+ \r
+ USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\\r
+ USB_OTG_HCINTMSK_STALLM |\\r
+ USB_OTG_HCINTMSK_TXERRM |\\r
+ USB_OTG_HCINTMSK_DTERRM |\\r
+ USB_OTG_HCINTMSK_AHBERR |\\r
+ USB_OTG_HCINTMSK_NAKM ;\r
+ \r
+ if (epnum & 0x80) \r
+ {\r
+ USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\r
+ } \r
+ else \r
+ {\r
+ if(USBx != USB_OTG_FS)\r
+ {\r
+ USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);\r
+ }\r
+ }\r
+ break;\r
+ case EP_TYPE_INTR:\r
+ \r
+ USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\\r
+ USB_OTG_HCINTMSK_STALLM |\\r
+ USB_OTG_HCINTMSK_TXERRM |\\r
+ USB_OTG_HCINTMSK_DTERRM |\\r
+ USB_OTG_HCINTMSK_NAKM |\\r
+ USB_OTG_HCINTMSK_AHBERR |\\r
+ USB_OTG_HCINTMSK_FRMORM ; \r
+ \r
+ if (epnum & 0x80) \r
+ {\r
+ USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\r
+ }\r
+ \r
+ break;\r
+ case EP_TYPE_ISOC:\r
+ \r
+ USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\\r
+ USB_OTG_HCINTMSK_ACKM |\\r
+ USB_OTG_HCINTMSK_AHBERR |\\r
+ USB_OTG_HCINTMSK_FRMORM ; \r
+ \r
+ if (epnum & 0x80) \r
+ {\r
+ USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); \r
+ }\r
+ break;\r
+ }\r
+ \r
+ /* Enable the top level host channel interrupt. */\r
+ USBx_HOST->HAINTMSK |= (1 << ch_num);\r
+ \r
+ /* Make sure host channel interrupts are enabled. */\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;\r
+ \r
+ /* Program the HCCHAR register */\r
+ USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\\r
+ (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\\r
+ ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\\r
+ (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\\r
+ ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\\r
+ (mps & USB_OTG_HCCHAR_MPSIZ));\r
+ \r
+ if (ep_type == EP_TYPE_INTR)\r
+ {\r
+ USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;\r
+ }\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Start a transfer over a host channel\r
+ * @param USBx : Selected device\r
+ * @param hc : pointer to host channel structure\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of the these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @retval HAL state\r
+ */\r
+#if defined (__CC_ARM) /*!< ARM Compiler */\r
+#pragma O0\r
+#elif defined (__GNUC__) /*!< GNU Compiler */\r
+#pragma GCC optimize ("O0")\r
+#endif /* __CC_ARM */\r
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)\r
+{\r
+ uint8_t is_oddframe = 0; \r
+ uint16_t len_words = 0; \r
+ uint16_t num_packets = 0;\r
+ uint16_t max_hc_pkt_count = 256;\r
+ \r
+ if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))\r
+ {\r
+ if((dma == 0) && (hc->do_ping == 1))\r
+ {\r
+ USB_DoPing(USBx, hc->ch_num);\r
+ return HAL_OK;\r
+ }\r
+ else if(dma == 1)\r
+ {\r
+ USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);\r
+ hc->do_ping = 0;\r
+ }\r
+ }\r
+ \r
+ /* Compute the expected number of packets associated to the transfer */\r
+ if (hc->xfer_len > 0)\r
+ {\r
+ num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;\r
+ \r
+ if (num_packets > max_hc_pkt_count)\r
+ {\r
+ num_packets = max_hc_pkt_count;\r
+ hc->xfer_len = num_packets * hc->max_packet;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ num_packets = 1;\r
+ }\r
+ if (hc->ep_is_in)\r
+ {\r
+ hc->xfer_len = num_packets * hc->max_packet;\r
+ }\r
+ \r
+ \r
+ \r
+ /* Initialize the HCTSIZn register */\r
+ USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\\r
+ ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\\r
+ (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);\r
+ \r
+ if (dma)\r
+ {\r
+ /* xfer_buff MUST be 32-bits aligned */\r
+ USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;\r
+ }\r
+ \r
+ is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;\r
+ USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;\r
+ USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);\r
+ \r
+ /* Set host channel enable */\r
+ USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;\r
+ USBx_HC(hc->ch_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
+ \r
+ if (dma == 0) /* Slave mode */\r
+ { \r
+ if((hc->ep_is_in == 0) && (hc->xfer_len > 0))\r
+ {\r
+ switch(hc->ep_type) \r
+ {\r
+ /* Non periodic transfer */\r
+ case EP_TYPE_CTRL:\r
+ case EP_TYPE_BULK:\r
+ \r
+ len_words = (hc->xfer_len + 3) / 4;\r
+ \r
+ /* check if there is enough space in FIFO space */\r
+ if(len_words > (USBx->HNPTXSTS & 0xFFFF))\r
+ {\r
+ /* need to process data in nptxfempty interrupt */\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;\r
+ }\r
+ break;\r
+ /* Periodic transfer */\r
+ case EP_TYPE_INTR:\r
+ case EP_TYPE_ISOC:\r
+ len_words = (hc->xfer_len + 3) / 4;\r
+ /* check if there is enough space in FIFO space */\r
+ if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */\r
+ {\r
+ /* need to process data in ptxfempty interrupt */\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; \r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+ \r
+ /* Write packet into the Tx FIFO. */\r
+ USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);\r
+ }\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Read all host channel interrupts status\r
+ * @param USBx : Selected device\r
+ * @retval HAL state\r
+ */\r
+uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ return ((USBx_HOST->HAINT) & 0xFFFF);\r
+}\r
+\r
+/**\r
+ * @brief Halt a host channel\r
+ * @param USBx : Selected device\r
+ * @param hc_num : Host Channel number\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)\r
+{\r
+ uint32_t count = 0;\r
+ \r
+ /* Check for space in the request queue to issue the halt. */\r
+ if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18)))\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\r
+ \r
+ if ((USBx->HNPTXSTS & 0xFFFF) == 0)\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; \r
+ USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\r
+ do \r
+ {\r
+ if (++count > 1000) \r
+ {\r
+ break;\r
+ }\r
+ } \r
+ while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); \r
+ }\r
+ else\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; \r
+ }\r
+ }\r
+ else\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\r
+ \r
+ if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; \r
+ USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\r
+ do \r
+ {\r
+ if (++count > 1000) \r
+ {\r
+ break;\r
+ }\r
+ } \r
+ while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); \r
+ }\r
+ else\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; \r
+ }\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initiate Do Ping protocol\r
+ * @param USBx : Selected device\r
+ * @param hc_num : Host Channel number\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)\r
+{\r
+ uint8_t num_packets = 1;\r
+\r
+ USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\\r
+ USB_OTG_HCTSIZ_DOPING;\r
+ \r
+ /* Set host channel enable */\r
+ USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;\r
+ USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Stop Host Core\r
+ * @param USBx : Selected device\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint8_t i;\r
+ uint32_t count = 0;\r
+ uint32_t value;\r
+ \r
+ USB_DisableGlobalInt(USBx);\r
+ \r
+ /* Flush FIFO */\r
+ USB_FlushTxFifo(USBx, 0x10);\r
+ USB_FlushRxFifo(USBx);\r
+ \r
+ /* Flush out any leftover queued requests. */\r
+ for (i = 0; i <= 15; i++)\r
+ { \r
+\r
+ value = USBx_HC(i)->HCCHAR ;\r
+ value |= USB_OTG_HCCHAR_CHDIS;\r
+ value &= ~USB_OTG_HCCHAR_CHENA; \r
+ value &= ~USB_OTG_HCCHAR_EPDIR;\r
+ USBx_HC(i)->HCCHAR = value;\r
+ }\r
+ \r
+ /* Halt all channels to put them into a known state. */ \r
+ for (i = 0; i <= 15; i++)\r
+ { \r
+\r
+ value = USBx_HC(i)->HCCHAR ;\r
+ \r
+ value |= USB_OTG_HCCHAR_CHDIS;\r
+ value |= USB_OTG_HCCHAR_CHENA; \r
+ value &= ~USB_OTG_HCCHAR_EPDIR;\r
+ \r
+ USBx_HC(i)->HCCHAR = value;\r
+ do \r
+ {\r
+ if (++count > 1000) \r
+ {\r
+ break;\r
+ }\r
+ } \r
+ while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\r
+ }\r
+\r
+ /* Clear any pending Host interrupts */\r
+ USBx_HOST->HAINT = 0xFFFFFFFF;\r
+ USBx->GINTSTS = 0xFFFFFFFF;\r
+ USB_EnableGlobalInt(USBx);\r
+ return HAL_OK; \r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / blobdiff