+++ /dev/null
-/* File: startup_ARMCM4.S\r
- * Purpose: startup file for Cortex-M4 devices. Should use with\r
- * GCC for ARM Embedded Processors\r
- * Version: V2.0\r
- * Date: 16 August 2013\r
- *\r
-/* Copyright (c) 2011 - 2013 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
- .syntax unified\r
- .arch armv7e-m\r
-\r
- .extern __SRAM_segment_end__\r
-\r
- .section .isr_vector,"a",%progbits\r
- .align 4\r
- .globl __isr_vector\r
- .global __Vectors\r
-\r
-__Vectors:\r
-__isr_vector:\r
- .long __SRAM_segment_end__ - 4 /* Top of Stack at top of RAM*/\r
- .long Reset_Handler /* Reset Handler */\r
- .long NMI_Handler /* NMI Handler */\r
- .long HardFault_Handler /* Hard Fault Handler */\r
- .long MemManage_Handler /* MPU Fault Handler */\r
- .long BusFault_Handler /* Bus Fault Handler */\r
- .long UsageFault_Handler /* Usage Fault Handler */\r
- .long 0 /* Reserved */\r
- .long 0 /* Reserved */\r
- .long 0 /* Reserved */\r
- .long 0 /* Reserved */\r
- .long SVC_Handler /* SVCall Handler */\r
- .long DebugMon_Handler /* Debug Monitor Handler */\r
- .long 0 /* Reserved */\r
- .long PendSV_Handler /* PendSV Handler */\r
- .long SysTick_Handler /* SysTick Handler */\r
-\r
- /* External interrupts */\r
- .long NVIC_Handler_GIRQ08 // 40h: 0, GIRQ08\r
- .long NVIC_Handler_GIRQ09 // 44h: 1, GIRQ09\r
- .long NVIC_Handler_GIRQ10 // 48h: 2, GIRQ10\r
- .long NVIC_Handler_GIRQ11 // 4Ch: 3, GIRQ11\r
- .long NVIC_Handler_GIRQ12 // 50h: 4, GIRQ12\r
- .long NVIC_Handler_GIRQ13 // 54h: 5, GIRQ13\r
- .long NVIC_Handler_GIRQ14 // 58h: 6, GIRQ14\r
- .long NVIC_Handler_GIRQ15 // 5Ch: 7, GIRQ15\r
- .long NVIC_Handler_GIRQ16 // 60h: 8, GIRQ16\r
- .long NVIC_Handler_GIRQ17 // 64h: 9, GIRQ17\r
- .long NVIC_Handler_GIRQ18 // 68h: 10, GIRQ18\r
- .long NVIC_Handler_GIRQ19 // 6Ch: 11, GIRQ19\r
- .long NVIC_Handler_GIRQ20 // 70h: 12, GIRQ20\r
- .long NVIC_Handler_GIRQ21 // 74h: 13, GIRQ21\r
- .long NVIC_Handler_GIRQ23 // 78h: 14, GIRQ23\r
- .long NVIC_Handler_GIRQ24 // 7Ch: 15, GIRQ24\r
- .long NVIC_Handler_GIRQ25 // 80h: 16, GIRQ25\r
- .long NVIC_Handler_GIRQ26 // 84h: 17, GIRQ26\r
- .long 0 // 88h: 18, RSVD\r
- .long 0 // 8Ch: 19, RSVD\r
- .long NVIC_Handler_I2C0 // 90h: 20, I2C/SMBus 0\r
- .long NVIC_Handler_I2C1 // 94h: 21, I2C/SMBus 1\r
- .long NVIC_Handler_I2C2 // 98h: 22, I2C/SMBus 2\r
- .long NVIC_Handler_I2C3 // 9Ch: 23, I2C/SMBus 3\r
- .long NVIC_Handler_DMA0 // A0h: 24, DMA Channel 0\r
- .long NVIC_Handler_DMA1 // A4h: 25, DMA Channel 1\r
- .long NVIC_Handler_DMA2 // A8h: 26, DMA Channel 2\r
- .long NVIC_Handler_DMA3 // ACh: 27, DMA Channel 3\r
- .long NVIC_Handler_DMA4 // B0h: 28, DMA Channel 4\r
- .long NVIC_Handler_DMA5 // B4h: 29, DMA Channel 5\r
- .long NVIC_Handler_DMA6 // B8h: 30, DMA Channel 6\r
- .long NVIC_Handler_DMA7 // BCh: 31, DMA Channel 7\r
- .long NVIC_Handler_DMA8 // C0h: 32, DMA Channel 8\r
- .long NVIC_Handler_DMA9 // C4h: 33, DMA Channel 9\r
- .long NVIC_Handler_DMA10 // C8h: 34, DMA Channel 10\r
- .long NVIC_Handler_DMA11 // CCh: 35, DMA Channel 11\r
- .long NVIC_Handler_DMA12 // D0h: 36, DMA Channel 12\r
- .long NVIC_Handler_DMA13 // D4h: 37, DMA Channel 13\r
- .long 0 // D8h: 38, Unused\r
- .long 0 // DCh: 39, Unused\r
- .long NVIC_Handler_UART0 // E0h: 40, UART0\r
- .long NVIC_Handler_UART1 // E4h: 41, UART1\r
- .long NVIC_Handler_EMI0 // E8h: 42, EMI0\r
- .long NVIC_Handler_EMI1 // ECh: 43, EMI0\r
- .long NVIC_Handler_EMI2 // F0h: 44, EMI0\r
- .long NVIC_Handler_ACPI_EC0_IBF // F4h: 45, ACPI_EC0_IBF\r
- .long NVIC_Handler_ACPI_EC0_OBF // F8h: 46, ACPI_EC0_OBF\r
- .long NVIC_Handler_ACPI_EC1_IBF // FCh: 47, ACPI_EC1_IBF\r
- .long NVIC_Handler_ACPI_EC1_OBF // 100h: 48, ACPI_EC1_OBF\r
- .long NVIC_Handler_ACPI_EC2_IBF // 104h: 49, ACPI_EC0_IBF\r
- .long NVIC_Handler_ACPI_EC2_OBF // 108h: 50, ACPI_EC0_OBF\r
- .long NVIC_Handler_ACPI_EC3_IBF // 10Ch: 51, ACPI_EC1_IBF\r
- .long NVIC_Handler_ACPI_EC3_OBF // 110h: 52, ACPI_EC1_OBF\r
- .long NVIC_Handler_ACPI_EC4_IBF // 114h: 53, ACPI_EC0_IBF\r
- .long NVIC_Handler_ACPI_EC4_OBF // 118h: 54, ACPI_EC0_OBF\r
- .long NVIC_Handler_PM1_CTL // 11Ch: 55, ACPI_PM1_CTL\r
- .long NVIC_Handler_PM1_EN // 120h: 56, ACPI_PM1_EN\r
- .long NVIC_Handler_PM1_STS // 124h: 57, ACPI_PM1_STS\r
- .long NVIC_Handler_MIF8042_OBF // 128h: 58, MIF8042_OBF\r
- .long NVIC_Handler_MIF8042_IBF // 12Ch: 59, MIF8042_IBF\r
- .long NVIC_Handler_MB_H2EC // 130h: 60, Mailbox Host to EC\r
- .long NVIC_Handler_MB_DATA // 134h: 61, Mailbox Host Data\r
- .long NVIC_Handler_P80A // 138h: 62, Port 80h A\r
- .long NVIC_Handler_P80B // 13Ch: 63, Port 80h B\r
- .long 0 // 140h: 64, Reserved\r
- .long NVIC_Handler_PKE_ERR // 144h: 65, PKE Error\r
- .long NVIC_Handler_PKE_END // 148h: 66, PKE End\r
- .long NVIC_Handler_TRNG // 14Ch: 67, Random Num Gen\r
- .long NVIC_Handler_AES // 150h: 68, AES\r
- .long NVIC_Handler_HASH // 154h: 69, HASH\r
- .long NVIC_Handler_PECI // 158h: 70, PECI\r
- .long NVIC_Handler_TACH0 // 15Ch: 71, TACH0\r
- .long NVIC_Handler_TACH1 // 160h: 72, TACH1\r
- .long NVIC_Handler_TACH2 // 164h: 73, TACH2\r
- .long NVIC_Handler_R2P0_FAIL // 168h: 74, RPM2PWM 0 Fan Fail\r
- .long NVIC_Handler_R2P0_STALL // 16Ch: 75, RPM2PWM 0 Fan Stall\r
- .long NVIC_Handler_R2P1_FAIL // 170h: 76, RPM2PWM 1 Fan Fail\r
- .long NVIC_Handler_R2P1_STALL // 174h: 77, RPM2PWM 1 Fan Stall\r
- .long NVIC_Handler_ADC_SNGL // 178h: 78, ADC_SNGL\r
- .long NVIC_Handler_ADC_RPT // 17Ch: 79, ADC_RPT\r
- .long NVIC_Handler_RCID0 // 180h: 80, RCID 0\r
- .long NVIC_Handler_RCID1 // 184h: 81, RCID 1\r
- .long NVIC_Handler_RCID2 // 188h: 82, RCID 2\r
- .long NVIC_Handler_LED0 // 18Ch: 83, LED0\r
- .long NVIC_Handler_LED1 // 190h: 84, LED1\r
- .long NVIC_Handler_LED2 // 194h: 85, LED2\r
- .long NVIC_Handler_LED3 // 198h: 86, LED2\r
- .long NVIC_Handler_PHOT // 19Ch: 87, ProcHot Monitor\r
- .long NVIC_Handler_PWRGD0 // 1A0h: 88, PowerGuard 0 Status\r
- .long NVIC_Handler_PWRGD1 // 1A4h: 89, PowerGuard 1 Status\r
- .long NVIC_Handler_LPCBERR // 1A8h: 90, LPC Bus Error\r
- .long NVIC_Handler_QMSPI0 // 1ACh: 91, QMSPI 0\r
- .long NVIC_Handler_GPSPI0_TX // 1B0h: 92, GP-SPI0 TX\r
- .long NVIC_Handler_GPSPI0_RX // 1B4h: 93, GP-SPI0 RX\r
- .long NVIC_Handler_GPSPI1_TX // 1B8h: 94, GP-SPI1 TX\r
- .long NVIC_Handler_GPSPI1_RX // 1BCh: 95, GP-SPI1 RX\r
- .long NVIC_Handler_BC0_BUSY // 1C0h: 96, BC-Link0 Busy-Clear\r
- .long NVIC_Handler_BC0_ERR // 1C4h: 97, BC-Link0 Error\r
- .long NVIC_Handler_BC1_BUSY // 1C8h: 98, BC-Link1 Busy-Clear\r
- .long NVIC_Handler_BC1_ERR // 1CCh: 99, BC-Link1 Error\r
- .long NVIC_Handler_PS2_0 // 1D0h: 100, PS2_0\r
- .long NVIC_Handler_PS2_1 // 1D4h: 101, PS2_1\r
- .long NVIC_Handler_PS2_2 // 1D8h: 102, PS2_2\r
- .long NVIC_Handler_ESPI_PC // 1DCh: 103, eSPI Periph Chan\r
- .long NVIC_Handler_ESPI_BM1 // 1E0h: 104, eSPI Bus Master 1\r
- .long NVIC_Handler_ESPI_BM2 // 1E4h: 105, eSPI Bus Master 2\r
- .long NVIC_Handler_ESPI_LTR // 1E8h: 106, eSPI LTR\r
- .long NVIC_Handler_ESPI_OOB_UP // 1ECh: 107, eSPI Bus Master 1\r
- .long NVIC_Handler_ESPI_OOB_DN // 1F0h: 108, eSPI Bus Master 2\r
- .long NVIC_Handler_ESPI_FLASH // 1F4h: 109, eSPI Flash Chan\r
- .long NVIC_Handler_ESPI_RESET // 1F8h: 110, eSPI Reset\r
- .long NVIC_Handler_RTMR // 1FCh: 111, RTOS Timer\r
- .long NVIC_Handler_HTMR0 // 200h: 112, Hibernation Timer 0\r
- .long NVIC_Handler_HTMR1 // 204h: 113, Hibernation Timer 1\r
- .long NVIC_Handler_WK // 208h: 114, Week Alarm\r
- .long NVIC_Handler_WKSUB // 20Ch: 115, Week Alarm, sub week\r
- .long NVIC_Handler_WKSEC // 210h: 116, Week Alarm, one sec\r
- .long NVIC_Handler_WKSUBSEC // 214h: 117, Week Alarm, sub sec\r
- .long NVIC_Handler_SYSPWR // 218h: 118, System Power Present pin\r
- .long NVIC_Handler_RTC // 21Ch: 119, RTC\r
- .long NVIC_Handler_RTC_ALARM // 220h: 120, RTC_ALARM\r
- .long NVIC_Handler_VCI_OVRD_IN // 224h: 121, VCI Override Input\r
- .long NVIC_Handler_VCI_IN0 // 228h: 122, VCI Input 0\r
- .long NVIC_Handler_VCI_IN1 // 22Ch: 123, VCI Input 1\r
- .long NVIC_Handler_VCI_IN2 // 230h: 124, VCI Input 2\r
- .long NVIC_Handler_VCI_IN3 // 234h: 125, VCI Input 3\r
- .long NVIC_Handler_VCI_IN4 // 238h: 126, VCI Input 4\r
- .long NVIC_Handler_VCI_IN5 // 23Ch: 127, VCI Input 5\r
- .long NVIC_Handler_VCI_IN6 // 240h: 128, VCI Input 6\r
- .long NVIC_Handler_PS20A_WAKE // 244h: 129, PS2 Port 0A Wake\r
- .long NVIC_Handler_PS20B_WAKE // 248h: 130, PS2 Port 0B Wake\r
- .long NVIC_Handler_PS21A_WAKE // 24Ch: 131, PS2 Port 1A Wake\r
- .long NVIC_Handler_PS21B_WAKE // 250h: 132, PS2 Port 1B Wake\r
- .long NVIC_Handler_PS21_WAKE // 254h: 133, PS2 Port 1 Wake\r
- .long NVIC_Handler_ENVMON // 258h: 134, Thernal Monitor\r
- .long NVIC_Handler_KEYSCAN // 25Ch: 135, Key Scan\r
- .long NVIC_Handler_BTMR16_0 // 260h: 136, 16-bit Basic Timer 0\r
- .long NVIC_Handler_BTMR16_1 // 264h: 137, 16-bit Basic Timer 1\r
- .long NVIC_Handler_BTMR16_2 // 268h: 138, 16-bit Basic Timer 2\r
- .long NVIC_Handler_BTMR16_3 // 26Ch: 139, 16-bit Basic Timer 3\r
- .long NVIC_Handler_BTMR32_0 // 270h: 140, 32-bit Basic Timer 0\r
- .long NVIC_Handler_BTMR32_1 // 274h: 141, 32-bit Basic Timer 1\r
- .long NVIC_Handler_EVTMR0 // 278h: 142, Event Counter/Timer 0\r
- .long NVIC_Handler_EVTMR1 // 27Ch: 143, Event Counter/Timer 1\r
- .long NVIC_Handler_EVTMR2 // 280h: 144, Event Counter/Timer 2\r
- .long NVIC_Handler_EVTMR3 // 284h: 145, Event Counter/Timer 3\r
- .long NVIC_Handler_CAPTMR // 288h: 146, Capture Timer\r
- .long NVIC_Handler_CAP0 // 28Ch: 147, Capture 0 Event\r
- .long NVIC_Handler_CAP1 // 290h: 148, Capture 1 Event\r
- .long NVIC_Handler_CAP2 // 294h: 149, Capture 2 Event\r
- .long NVIC_Handler_CAP3 // 298h: 150, Capture 3 Event\r
- .long NVIC_Handler_CAP4 // 29Ch: 151, Capture 4 Event\r
- .long NVIC_Handler_CAP5 // 2A0h: 152, Capture 5 Event\r
- .long NVIC_Handler_CMP0 // 2A4h: 153, Compare 0 Event\r
- .long NVIC_Handler_CMP1 // 2A8h: 154, Compare 1 Event\r
-\r
-\r
- .text\r
- .thumb\r
- .thumb_func\r
- .align 2\r
- .globl _start\r
- .extern main\r
- .globl Reset_Handler\r
- .type Reset_Handler, %function\r
-_start:\r
-Reset_Handler:\r
-/* Firstly it copies data from read only memory to RAM. There are two schemes\r
- * to copy. One can copy more than one sections. Another can only copy\r
- * one section. The former scheme needs more instructions and read-only\r
- * data to implement than the latter.\r
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */\r
-\r
-/* Single section scheme.\r
- *\r
- * The ranges of copy from/to are specified by following symbols\r
- * __etext: LMA of start of the section to copy from. Usually end of text\r
- * __data_start__: VMA of start of the section to copy to\r
- * __data_end__: VMA of end of the section to copy to\r
- *\r
- * All addresses must be aligned to 4 bytes boundary.\r
- */\r
- ldr sp, =__SRAM_segment_end__\r
- sub sp, sp, #4\r
-\r
- ldr r1, =__etext\r
- ldr r2, =__data_start__\r
- ldr r3, =__data_end__\r
-\r
-.L_loop1:\r
- cmp r2, r3\r
- ittt lt\r
- ldrlt r0, [r1], #4\r
- strlt r0, [r2], #4\r
- blt .L_loop1\r
-\r
-/* This part of work usually is done in C library startup code. Otherwise,\r
- * define this macro to enable it in this startup.\r
- *\r
- * There are two schemes too. One can clear multiple BSS sections. Another\r
- * can only clear one section. The former is more size expensive than the\r
- * latter.\r
- *\r
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.\r
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.\r
- */\r
-\r
- /* Single BSS section scheme.\r
- *\r
- * The BSS section is specified by following symbols\r
- * __bss_start__: start of the BSS section.\r
- * __bss_end__: end of the BSS section.\r
- *\r
- * Both addresses must be aligned to 4 bytes boundary.\r
- */\r
- ldr r1, =__bss_start__\r
- ldr r2, =__bss_end__\r
-\r
- movs r0, 0\r
-.L_loop3:\r
- cmp r1, r2\r
- itt lt\r
- strlt r0, [r1], #4\r
- blt .L_loop3\r
-\r
-#ifndef __NO_SYSTEM_INIT\r
-/* bl SystemInit */\r
-#endif\r
-\r
- bl main\r
-\r
- .pool\r
- .size Reset_Handler, . - Reset_Handler\r
-\r
- .align 1\r
- .thumb_func\r
- .weak Default_Handler\r
- .type Default_Handler, %function\r
-Default_Handler:\r
- b .\r
- .size Default_Handler, . - Default_Handler\r
-\r
-/* Macro to define default handlers. Default handler\r
- * will be weak symbol and just dead loops. They can be\r
- * overwritten by other handlers */\r
- .macro def_irq_handler handler_name\r
- .weak \handler_name\r
- .set \handler_name, Default_Handler\r
- .endm\r
-\r
- def_irq_handler NMI_Handler\r
- def_irq_handler HardFault_Handler\r
- def_irq_handler MemManage_Handler\r
- def_irq_handler BusFault_Handler\r
- def_irq_handler UsageFault_Handler\r
-/* def_irq_handler SVC_Handler */\r
- def_irq_handler DebugMon_Handler\r
-/* def_irq_handler PendSV_Handler */\r
-/* def_irq_handler SysTick_Handler */\r
- def_irq_handler DEF_IRQHandler\r
-\r
- def_irq_handler NVIC_Handler_GIRQ08 // 40h: 0, GIRQ08\r
- def_irq_handler NVIC_Handler_GIRQ09 // 44h: 1, GIRQ09\r
- def_irq_handler NVIC_Handler_GIRQ10 // 48h: 2, GIRQ10\r
- def_irq_handler NVIC_Handler_GIRQ11 // 4Ch: 3, GIRQ11\r
- def_irq_handler NVIC_Handler_GIRQ12 // 50h: 4, GIRQ12\r
- def_irq_handler NVIC_Handler_GIRQ13 // 54h: 5, GIRQ13\r
- def_irq_handler NVIC_Handler_GIRQ14 // 58h: 6, GIRQ14\r
- def_irq_handler NVIC_Handler_GIRQ15 // 5Ch: 7, GIRQ15\r
- def_irq_handler NVIC_Handler_GIRQ16 // 60h: 8, GIRQ16\r
- def_irq_handler NVIC_Handler_GIRQ17 // 64h: 9, GIRQ17\r
- def_irq_handler NVIC_Handler_GIRQ18 // 68h: 10, GIRQ18\r
- def_irq_handler NVIC_Handler_GIRQ19 // 6Ch: 11, GIRQ19\r
- def_irq_handler NVIC_Handler_GIRQ20 // 70h: 12, GIRQ20\r
- def_irq_handler NVIC_Handler_GIRQ21 // 74h: 13, GIRQ21\r
- def_irq_handler NVIC_Handler_GIRQ23 // 78h: 14, GIRQ23\r
- def_irq_handler NVIC_Handler_GIRQ24 // 7Ch: 15, GIRQ24\r
- def_irq_handler NVIC_Handler_GIRQ25 // 80h: 16, GIRQ25\r
- def_irq_handler NVIC_Handler_GIRQ26 // 84h: 17, GIRQ26\r
- def_irq_handler NVIC_Handler_I2C0 // 90h: 20, I2C/SMBus 0\r
- def_irq_handler NVIC_Handler_I2C1 // 94h: 21, I2C/SMBus 1\r
- def_irq_handler NVIC_Handler_I2C2 // 98h: 22, I2C/SMBus 2\r
- def_irq_handler NVIC_Handler_I2C3 // 9Ch: 23, I2C/SMBus 3\r
- def_irq_handler NVIC_Handler_DMA0 // A0h: 24, DMA Channel 0\r
- def_irq_handler NVIC_Handler_DMA1 // A4h: 25, DMA Channel 1\r
- def_irq_handler NVIC_Handler_DMA2 // A8h: 26, DMA Channel 2\r
- def_irq_handler NVIC_Handler_DMA3 // ACh: 27, DMA Channel 3\r
- def_irq_handler NVIC_Handler_DMA4 // B0h: 28, DMA Channel 4\r
- def_irq_handler NVIC_Handler_DMA5 // B4h: 29, DMA Channel 5\r
- def_irq_handler NVIC_Handler_DMA6 // B8h: 30, DMA Channel 6\r
- def_irq_handler NVIC_Handler_DMA7 // BCh: 31, DMA Channel 7\r
- def_irq_handler NVIC_Handler_DMA8 // C0h: 32, DMA Channel 8\r
- def_irq_handler NVIC_Handler_DMA9 // C4h: 33, DMA Channel 9\r
- def_irq_handler NVIC_Handler_DMA10 // C8h: 34, DMA Channel 10\r
- def_irq_handler NVIC_Handler_DMA11 // CCh: 35, DMA Channel 11\r
- def_irq_handler NVIC_Handler_DMA12 // D0h: 36, DMA Channel 12\r
- def_irq_handler NVIC_Handler_DMA13 // D4h: 37, DMA Channel 13\r
- def_irq_handler NVIC_Handler_UART0 // E0h: 40, UART0\r
- def_irq_handler NVIC_Handler_UART1 // E4h: 41, UART1\r
- def_irq_handler NVIC_Handler_EMI0 // E8h: 42, EMI0\r
- def_irq_handler NVIC_Handler_EMI1 // ECh: 43, EMI0\r
- def_irq_handler NVIC_Handler_EMI2 // F0h: 44, EMI0\r
- def_irq_handler NVIC_Handler_ACPI_EC0_IBF // F4h: 45, ACPI_EC0_IBF\r
- def_irq_handler NVIC_Handler_ACPI_EC0_OBF // F8h: 46, ACPI_EC0_OBF\r
- def_irq_handler NVIC_Handler_ACPI_EC1_IBF // FCh: 47, ACPI_EC1_IBF\r
- def_irq_handler NVIC_Handler_ACPI_EC1_OBF // 100h: 48, ACPI_EC1_OBF\r
- def_irq_handler NVIC_Handler_ACPI_EC2_IBF // 104h: 49, ACPI_EC0_IBF\r
- def_irq_handler NVIC_Handler_ACPI_EC2_OBF // 108h: 50, ACPI_EC0_OBF\r
- def_irq_handler NVIC_Handler_ACPI_EC3_IBF // 10Ch: 51, ACPI_EC1_IBF\r
- def_irq_handler NVIC_Handler_ACPI_EC3_OBF // 110h: 52, ACPI_EC1_OBF\r
- def_irq_handler NVIC_Handler_ACPI_EC4_IBF // 114h: 53, ACPI_EC0_IBF\r
- def_irq_handler NVIC_Handler_ACPI_EC4_OBF // 118h: 54, ACPI_EC0_OBF\r
- def_irq_handler NVIC_Handler_PM1_CTL // 11Ch: 55, ACPI_PM1_CTL\r
- def_irq_handler NVIC_Handler_PM1_EN // 120h: 56, ACPI_PM1_EN\r
- def_irq_handler NVIC_Handler_PM1_STS // 124h: 57, ACPI_PM1_STS\r
- def_irq_handler NVIC_Handler_MIF8042_OBF // 128h: 58, MIF8042_OBF\r
- def_irq_handler NVIC_Handler_MIF8042_IBF // 12Ch: 59, MIF8042_IBF\r
- def_irq_handler NVIC_Handler_MB_H2EC // 130h: 60, Mailbox Host to EC\r
- def_irq_handler NVIC_Handler_MB_DATA // 134h: 61, Mailbox Host Data\r
- def_irq_handler NVIC_Handler_P80A // 138h: 62, Port 80h A\r
- def_irq_handler NVIC_Handler_P80B // 13Ch: 63, Port 80h B\r
- def_irq_handler NVIC_Handler_PKE_ERR // 144h: 65, PKE Error\r
- def_irq_handler NVIC_Handler_PKE_END // 148h: 66, PKE End\r
- def_irq_handler NVIC_Handler_TRNG // 14Ch: 67, Random Num Gen\r
- def_irq_handler NVIC_Handler_AES // 150h: 68, AES\r
- def_irq_handler NVIC_Handler_HASH // 154h: 69, HASH\r
- def_irq_handler NVIC_Handler_PECI // 158h: 70, PECI\r
- def_irq_handler NVIC_Handler_TACH0 // 15Ch: 71, TACH0\r
- def_irq_handler NVIC_Handler_TACH1 // 160h: 72, TACH1\r
- def_irq_handler NVIC_Handler_TACH2 // 164h: 73, TACH2\r
- def_irq_handler NVIC_Handler_R2P0_FAIL // 168h: 74, RPM2PWM 0 Fan Fail\r
- def_irq_handler NVIC_Handler_R2P0_STALL // 16Ch: 75, RPM2PWM 0 Fan Stall\r
- def_irq_handler NVIC_Handler_R2P1_FAIL // 170h: 76, RPM2PWM 1 Fan Fail\r
- def_irq_handler NVIC_Handler_R2P1_STALL // 174h: 77, RPM2PWM 1 Fan Stall\r
- def_irq_handler NVIC_Handler_ADC_SNGL // 178h: 78, ADC_SNGL\r
- def_irq_handler NVIC_Handler_ADC_RPT // 17Ch: 79, ADC_RPT\r
- def_irq_handler NVIC_Handler_RCID0 // 180h: 80, RCID 0\r
- def_irq_handler NVIC_Handler_RCID1 // 184h: 81, RCID 1\r
- def_irq_handler NVIC_Handler_RCID2 // 188h: 82, RCID 2\r
- def_irq_handler NVIC_Handler_LED0 // 18Ch: 83, LED0\r
- def_irq_handler NVIC_Handler_LED1 // 190h: 84, LED1\r
- def_irq_handler NVIC_Handler_LED2 // 194h: 85, LED2\r
- def_irq_handler NVIC_Handler_LED3 // 198h: 86, LED2\r
- def_irq_handler NVIC_Handler_PHOT // 19Ch: 87, ProcHot Monitor\r
- def_irq_handler NVIC_Handler_PWRGD0 // 1A0h: 88, PowerGuard 0 Status\r
- def_irq_handler NVIC_Handler_PWRGD1 // 1A4h: 89, PowerGuard 1 Status\r
- def_irq_handler NVIC_Handler_LPCBERR // 1A8h: 90, LPC Bus Error\r
- def_irq_handler NVIC_Handler_QMSPI0 // 1ACh: 91, QMSPI 0\r
- def_irq_handler NVIC_Handler_GPSPI0_TX // 1B0h: 92, GP-SPI0 TX\r
- def_irq_handler NVIC_Handler_GPSPI0_RX // 1B4h: 93, GP-SPI0 RX\r
- def_irq_handler NVIC_Handler_GPSPI1_TX // 1B8h: 94, GP-SPI1 TX\r
- def_irq_handler NVIC_Handler_GPSPI1_RX // 1BCh: 95, GP-SPI1 RX\r
- def_irq_handler NVIC_Handler_BC0_BUSY // 1C0h: 96, BC-Link0 Busy-Clear\r
- def_irq_handler NVIC_Handler_BC0_ERR // 1C4h: 97, BC-Link0 Error\r
- def_irq_handler NVIC_Handler_BC1_BUSY // 1C8h: 98, BC-Link1 Busy-Clear\r
- def_irq_handler NVIC_Handler_BC1_ERR // 1CCh: 99, BC-Link1 Error\r
- def_irq_handler NVIC_Handler_PS2_0 // 1D0h: 100, PS2_0\r
- def_irq_handler NVIC_Handler_PS2_1 // 1D4h: 101, PS2_1\r
- def_irq_handler NVIC_Handler_PS2_2 // 1D8h: 102, PS2_2\r
- def_irq_handler NVIC_Handler_ESPI_PC // 1DCh: 103, eSPI Periph Chan\r
- def_irq_handler NVIC_Handler_ESPI_BM1 // 1E0h: 104, eSPI Bus Master 1\r
- def_irq_handler NVIC_Handler_ESPI_BM2 // 1E4h: 105, eSPI Bus Master 2\r
- def_irq_handler NVIC_Handler_ESPI_LTR // 1E8h: 106, eSPI LTR\r
- def_irq_handler NVIC_Handler_ESPI_OOB_UP // 1ECh: 107, eSPI Bus Master 1\r
- def_irq_handler NVIC_Handler_ESPI_OOB_DN // 1F0h: 108, eSPI Bus Master 2\r
- def_irq_handler NVIC_Handler_ESPI_FLASH // 1F4h: 109, eSPI Flash Chan\r
- def_irq_handler NVIC_Handler_ESPI_RESET // 1F8h: 110, eSPI Reset\r
- def_irq_handler NVIC_Handler_RTMR // 1FCh: 111, RTOS Timer\r
- def_irq_handler NVIC_Handler_HTMR0 // 200h: 112, Hibernation Timer 0\r
- def_irq_handler NVIC_Handler_HTMR1 // 204h: 113, Hibernation Timer 1\r
- def_irq_handler NVIC_Handler_WK // 208h: 114, Week Alarm\r
- def_irq_handler NVIC_Handler_WKSUB // 20Ch: 115, Week Alarm, sub week\r
- def_irq_handler NVIC_Handler_WKSEC // 210h: 116, Week Alarm, one sec\r
- def_irq_handler NVIC_Handler_WKSUBSEC // 214h: 117, Week Alarm, sub sec\r
- def_irq_handler NVIC_Handler_SYSPWR // 218h: 118, System Power Present pin\r
- def_irq_handler NVIC_Handler_RTC // 21Ch: 119, RTC\r
- def_irq_handler NVIC_Handler_RTC_ALARM // 220h: 120, RTC_ALARM\r
- def_irq_handler NVIC_Handler_VCI_OVRD_IN // 224h: 121, VCI Override Input\r
- def_irq_handler NVIC_Handler_VCI_IN0 // 228h: 122, VCI Input 0\r
- def_irq_handler NVIC_Handler_VCI_IN1 // 22Ch: 123, VCI Input 1\r
- def_irq_handler NVIC_Handler_VCI_IN2 // 230h: 124, VCI Input 2\r
- def_irq_handler NVIC_Handler_VCI_IN3 // 234h: 125, VCI Input 3\r
- def_irq_handler NVIC_Handler_VCI_IN4 // 238h: 126, VCI Input 4\r
- def_irq_handler NVIC_Handler_VCI_IN5 // 23Ch: 127, VCI Input 5\r
- def_irq_handler NVIC_Handler_VCI_IN6 // 240h: 128, VCI Input 6\r
- def_irq_handler NVIC_Handler_PS20A_WAKE // 244h: 129, PS2 Port 0A Wake\r
- def_irq_handler NVIC_Handler_PS20B_WAKE // 248h: 130, PS2 Port 0B Wake\r
- def_irq_handler NVIC_Handler_PS21A_WAKE // 24Ch: 131, PS2 Port 1A Wake\r
- def_irq_handler NVIC_Handler_PS21B_WAKE // 250h: 132, PS2 Port 1B Wake\r
- def_irq_handler NVIC_Handler_PS21_WAKE // 254h: 133, PS2 Port 1 Wake\r
- def_irq_handler NVIC_Handler_ENVMON // 258h: 134, Thernal Monitor\r
- def_irq_handler NVIC_Handler_KEYSCAN // 25Ch: 135, Key Scan\r
- def_irq_handler NVIC_Handler_BTMR16_0 // 260h: 136, 16-bit Basic Timer 0\r
- def_irq_handler NVIC_Handler_BTMR16_1 // 264h: 137, 16-bit Basic Timer 1\r
- def_irq_handler NVIC_Handler_BTMR16_2 // 268h: 138, 16-bit Basic Timer 2\r
- def_irq_handler NVIC_Handler_BTMR16_3 // 26Ch: 139, 16-bit Basic Timer 3\r
- def_irq_handler NVIC_Handler_BTMR32_0 // 270h: 140, 32-bit Basic Timer 0\r
- def_irq_handler NVIC_Handler_BTMR32_1 // 274h: 141, 32-bit Basic Timer 1\r
- def_irq_handler NVIC_Handler_EVTMR0 // 278h: 142, Event Counter/Timer 0\r
- def_irq_handler NVIC_Handler_EVTMR1 // 27Ch: 143, Event Counter/Timer 1\r
- def_irq_handler NVIC_Handler_EVTMR2 // 280h: 144, Event Counter/Timer 2\r
- def_irq_handler NVIC_Handler_EVTMR3 // 284h: 145, Event Counter/Timer 3\r
- def_irq_handler NVIC_Handler_CAPTMR // 288h: 146, Capture Timer\r
- def_irq_handler NVIC_Handler_CAP0 // 28Ch: 147, Capture 0 Event\r
- def_irq_handler NVIC_Handler_CAP1 // 290h: 148, Capture 1 Event\r
- def_irq_handler NVIC_Handler_CAP2 // 294h: 149, Capture 2 Event\r
- def_irq_handler NVIC_Handler_CAP3 // 298h: 150, Capture 3 Event\r
- def_irq_handler NVIC_Handler_CAP4 // 29Ch: 151, Capture 4 Event\r
- def_irq_handler NVIC_Handler_CAP5 // 2A0h: 152, Capture 5 Event\r
- def_irq_handler NVIC_Handler_CMP0 // 2A4h: 153, Compare 0 Event\r
- def_irq_handler NVIC_Handler_CMP1 // 2A8h: 154, Compare 1 Event\r
-\r
- .end\r
projects / freertos / blobdiff