--- /dev/null
+;/*****************************************************************************\r
+; * @file: startup_MPS_CM4.s\r
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File\r
+; * for the ARM 'Microcontroller Prototyping System'\r
+; * @version: V1.00\r
+; * @date: 1. Jun. 2010\r
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+; *\r
+; * Copyright (C) 2008-2010 ARM Limited. All rights reserved.\r
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M4\r
+; * processor based microcontrollers. This file can be freely distributed\r
+; * within development tools that are supporting such ARM based processors.\r
+; *\r
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+; *\r
+; ****************************************************************************/\r
+\r
+\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+Stack_Size EQU 0x00000800\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000000\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+\r
+; Vector Table Mapped to Address 0 at Reset\r
+\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+\r
+__Vectors DCD __initial_sp ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD MemManage_Handler ; MPU Fault Handler\r
+ DCD BusFault_Handler ; Bus Fault Handler\r
+ DCD UsageFault_Handler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; External Interrupts\r
+ DCD NVIC_Handler_GIRQ08 ; 40h: 0, GIRQ08\r
+ DCD NVIC_Handler_GIRQ09 ; 44h: 1, GIRQ09\r
+ DCD NVIC_Handler_GIRQ10 ; 48h: 2, GIRQ10\r
+ DCD NVIC_Handler_GIRQ11 ; 4Ch: 3, GIRQ11\r
+ DCD NVIC_Handler_GIRQ12 ; 50h: 4, GIRQ12\r
+ DCD NVIC_Handler_GIRQ13 ; 54h: 5, GIRQ13\r
+ DCD NVIC_Handler_GIRQ14 ; 58h: 6, GIRQ14\r
+ DCD NVIC_Handler_GIRQ15 ; 5Ch: 7, GIRQ15\r
+ DCD NVIC_Handler_GIRQ16 ; 60h: 8, GIRQ16\r
+ DCD NVIC_Handler_GIRQ17 ; 64h: 9, GIRQ17\r
+ DCD NVIC_Handler_GIRQ18 ; 68h: 10, GIRQ18\r
+ DCD NVIC_Handler_GIRQ19 ; 6Ch: 11, GIRQ19\r
+ DCD NVIC_Handler_GIRQ20 ; 70h: 12, GIRQ20\r
+ DCD NVIC_Handler_GIRQ21 ; 74h: 13, GIRQ21\r
+ DCD NVIC_Handler_GIRQ23 ; 78h: 14, GIRQ23\r
+ DCD NVIC_Handler_GIRQ24 ; 7Ch: 15, GIRQ24\r
+ DCD NVIC_Handler_GIRQ25 ; 80h: 16, GIRQ25\r
+ DCD NVIC_Handler_GIRQ26 ; 84h: 17, GIRQ26\r
+ DCD 0 ; 88h: 18, RSVD\r
+ DCD 0 ; 8Ch: 19, RSVD\r
+ DCD NVIC_Handler_I2C0 ; 90h: 20, I2C/SMBus 0\r
+ DCD NVIC_Handler_I2C1 ; 94h: 21, I2C/SMBus 1\r
+ DCD NVIC_Handler_I2C2 ; 98h: 22, I2C/SMBus 2\r
+ DCD NVIC_Handler_I2C3 ; 9Ch: 23, I2C/SMBus 3\r
+ DCD NVIC_Handler_DMA0 ; A0h: 24, DMA Channel 0\r
+ DCD NVIC_Handler_DMA1 ; A4h: 25, DMA Channel 1\r
+ DCD NVIC_Handler_DMA2 ; A8h: 26, DMA Channel 2\r
+ DCD NVIC_Handler_DMA3 ; ACh: 27, DMA Channel 3\r
+ DCD NVIC_Handler_DMA4 ; B0h: 28, DMA Channel 4\r
+ DCD NVIC_Handler_DMA5 ; B4h: 29, DMA Channel 5\r
+ DCD NVIC_Handler_DMA6 ; B8h: 30, DMA Channel 6\r
+ DCD NVIC_Handler_DMA7 ; BCh: 31, DMA Channel 7\r
+ DCD NVIC_Handler_DMA8 ; C0h: 32, DMA Channel 8\r
+ DCD NVIC_Handler_DMA9 ; C4h: 33, DMA Channel 9\r
+ DCD NVIC_Handler_DMA10 ; C8h: 34, DMA Channel 10\r
+ DCD NVIC_Handler_DMA11 ; CCh: 35, DMA Channel 11\r
+ DCD NVIC_Handler_DMA12 ; D0h: 36, DMA Channel 12\r
+ DCD NVIC_Handler_DMA13 ; D4h: 37, DMA Channel 13\r
+ DCD 0 ; D8h: 38, Unused\r
+ DCD 0 ; DCh: 39, Unused\r
+ DCD NVIC_Handler_UART0 ; E0h: 40, UART0\r
+ DCD NVIC_Handler_UART1 ; E4h: 41, UART1\r
+ DCD NVIC_Handler_EMI0 ; E8h: 42, EMI0\r
+ DCD NVIC_Handler_EMI1 ; ECh: 43, EMI0\r
+ DCD NVIC_Handler_EMI2 ; F0h: 44, EMI0\r
+ DCD NVIC_Handler_ACPI_EC0_IBF ; F4h: 45, ACPI_EC0_IBF\r
+ DCD NVIC_Handler_ACPI_EC0_OBF ; F8h: 46, ACPI_EC0_OBF\r
+ DCD NVIC_Handler_ACPI_EC1_IBF ; FCh: 47, ACPI_EC1_IBF\r
+ DCD NVIC_Handler_ACPI_EC1_OBF ; 100h: 48, ACPI_EC1_OBF\r
+ DCD NVIC_Handler_ACPI_EC2_IBF ; 104h: 49, ACPI_EC0_IBF\r
+ DCD NVIC_Handler_ACPI_EC2_OBF ; 108h: 50, ACPI_EC0_OBF\r
+ DCD NVIC_Handler_ACPI_EC3_IBF ; 10Ch: 51, ACPI_EC1_IBF\r
+ DCD NVIC_Handler_ACPI_EC3_OBF ; 110h: 52, ACPI_EC1_OBF\r
+ DCD NVIC_Handler_ACPI_EC4_IBF ; 114h: 53, ACPI_EC0_IBF\r
+ DCD NVIC_Handler_ACPI_EC4_OBF ; 118h: 54, ACPI_EC0_OBF\r
+ DCD NVIC_Handler_PM1_CTL ; 11Ch: 55, ACPI_PM1_CTL\r
+ DCD NVIC_Handler_PM1_EN ; 120h: 56, ACPI_PM1_EN\r
+ DCD NVIC_Handler_PM1_STS ; 124h: 57, ACPI_PM1_STS\r
+ DCD NVIC_Handler_MIF8042_OBF ; 128h: 58, MIF8042_OBF\r
+ DCD NVIC_Handler_MIF8042_IBF ; 12Ch: 59, MIF8042_IBF\r
+ DCD NVIC_Handler_MB_H2EC ; 130h: 60, Mailbox Host to EC\r
+ DCD NVIC_Handler_MB_DATA ; 134h: 61, Mailbox Host Data\r
+ DCD NVIC_Handler_P80A ; 138h: 62, Port 80h A\r
+ DCD NVIC_Handler_P80B ; 13Ch: 63, Port 80h B\r
+ DCD 0 ; 140h: 64, Reserved\r
+ DCD NVIC_Handler_PKE_ERR ; 144h: 65, PKE Error\r
+ DCD NVIC_Handler_PKE_END ; 148h: 66, PKE End\r
+ DCD NVIC_Handler_TRNG ; 14Ch: 67, Random Num Gen\r
+ DCD NVIC_Handler_AES ; 150h: 68, AES\r
+ DCD NVIC_Handler_HASH ; 154h: 69, HASH\r
+ DCD NVIC_Handler_PECI ; 158h: 70, PECI\r
+ DCD NVIC_Handler_TACH0 ; 15Ch: 71, TACH0\r
+ DCD NVIC_Handler_TACH1 ; 160h: 72, TACH1\r
+ DCD NVIC_Handler_TACH2 ; 164h: 73, TACH2\r
+ DCD NVIC_Handler_R2P0_FAIL ; 168h: 74, RPM2PWM 0 Fan Fail\r
+ DCD NVIC_Handler_R2P0_STALL ; 16Ch: 75, RPM2PWM 0 Fan Stall\r
+ DCD NVIC_Handler_R2P1_FAIL ; 170h: 76, RPM2PWM 1 Fan Fail\r
+ DCD NVIC_Handler_R2P1_STALL ; 174h: 77, RPM2PWM 1 Fan Stall\r
+ DCD NVIC_Handler_ADC_SNGL ; 178h: 78, ADC_SNGL\r
+ DCD NVIC_Handler_ADC_RPT ; 17Ch: 79, ADC_RPT\r
+ DCD NVIC_Handler_RCID0 ; 180h: 80, RCID 0\r
+ DCD NVIC_Handler_RCID1 ; 184h: 81, RCID 1\r
+ DCD NVIC_Handler_RCID2 ; 188h: 82, RCID 2\r
+ DCD NVIC_Handler_LED0 ; 18Ch: 83, LED0\r
+ DCD NVIC_Handler_LED1 ; 190h: 84, LED1\r
+ DCD NVIC_Handler_LED2 ; 194h: 85, LED2\r
+ DCD NVIC_Handler_LED3 ; 198h: 86, LED2\r
+ DCD NVIC_Handler_PHOT ; 19Ch: 87, ProcHot Monitor\r
+ DCD NVIC_Handler_PWRGD0 ; 1A0h: 88, PowerGuard 0 Status\r
+ DCD NVIC_Handler_PWRGD1 ; 1A4h: 89, PowerGuard 1 Status\r
+ DCD NVIC_Handler_LPCBERR ; 1A8h: 90, LPC Bus Error\r
+ DCD NVIC_Handler_QMSPI0 ; 1ACh: 91, QMSPI 0\r
+ DCD NVIC_Handler_GPSPI0_TX ; 1B0h: 92, GP-SPI0 TX\r
+ DCD NVIC_Handler_GPSPI0_RX ; 1B4h: 93, GP-SPI0 RX\r
+ DCD NVIC_Handler_GPSPI1_TX ; 1B8h: 94, GP-SPI1 TX\r
+ DCD NVIC_Handler_GPSPI1_RX ; 1BCh: 95, GP-SPI1 RX\r
+ DCD NVIC_Handler_BC0_BUSY ; 1C0h: 96, BC-Link0 Busy-Clear\r
+ DCD NVIC_Handler_BC0_ERR ; 1C4h: 97, BC-Link0 Error\r
+ DCD NVIC_Handler_BC1_BUSY ; 1C8h: 98, BC-Link1 Busy-Clear\r
+ DCD NVIC_Handler_BC1_ERR ; 1CCh: 99, BC-Link1 Error\r
+ DCD NVIC_Handler_PS2_0 ; 1D0h: 100, PS2_0\r
+ DCD NVIC_Handler_PS2_1 ; 1D4h: 101, PS2_1\r
+ DCD NVIC_Handler_PS2_2 ; 1D8h: 102, PS2_2\r
+ DCD NVIC_Handler_ESPI_PC ; 1DCh: 103, eSPI Periph Chan\r
+ DCD NVIC_Handler_ESPI_BM1 ; 1E0h: 104, eSPI Bus Master 1\r
+ DCD NVIC_Handler_ESPI_BM2 ; 1E4h: 105, eSPI Bus Master 2\r
+ DCD NVIC_Handler_ESPI_LTR ; 1E8h: 106, eSPI LTR\r
+ DCD NVIC_Handler_ESPI_OOB_UP ; 1ECh: 107, eSPI Bus Master 1\r
+ DCD NVIC_Handler_ESPI_OOB_DN ; 1F0h: 108, eSPI Bus Master 2\r
+ DCD NVIC_Handler_ESPI_FLASH ; 1F4h: 109, eSPI Flash Chan\r
+ DCD NVIC_Handler_ESPI_RESET ; 1F8h: 110, eSPI Reset\r
+ DCD NVIC_Handler_RTMR ; 1FCh: 111, RTOS Timer\r
+ DCD NVIC_Handler_HTMR0 ; 200h: 112, Hibernation Timer 0\r
+ DCD NVIC_Handler_HTMR1 ; 204h: 113, Hibernation Timer 1\r
+ DCD NVIC_Handler_WK ; 208h: 114, Week Alarm\r
+ DCD NVIC_Handler_WKSUB ; 20Ch: 115, Week Alarm, sub week\r
+ DCD NVIC_Handler_WKSEC ; 210h: 116, Week Alarm, one sec\r
+ DCD NVIC_Handler_WKSUBSEC ; 214h: 117, Week Alarm, sub sec\r
+ DCD NVIC_Handler_SYSPWR ; 218h: 118, System Power Present pin\r
+ DCD NVIC_Handler_RTC ; 21Ch: 119, RTC\r
+ DCD NVIC_Handler_RTC_ALARM ; 220h: 120, RTC_ALARM\r
+ DCD NVIC_Handler_VCI_OVRD_IN ; 224h: 121, VCI Override Input\r
+ DCD NVIC_Handler_VCI_IN0 ; 228h: 122, VCI Input 0\r
+ DCD NVIC_Handler_VCI_IN1 ; 22Ch: 123, VCI Input 1\r
+ DCD NVIC_Handler_VCI_IN2 ; 230h: 124, VCI Input 2\r
+ DCD NVIC_Handler_VCI_IN3 ; 234h: 125, VCI Input 3\r
+ DCD NVIC_Handler_VCI_IN4 ; 238h: 126, VCI Input 4\r
+ DCD NVIC_Handler_VCI_IN5 ; 23Ch: 127, VCI Input 5\r
+ DCD NVIC_Handler_VCI_IN6 ; 240h: 128, VCI Input 6\r
+ DCD NVIC_Handler_PS20A_WAKE ; 244h: 129, PS2 Port 0A Wake\r
+ DCD NVIC_Handler_PS20B_WAKE ; 248h: 130, PS2 Port 0B Wake\r
+ DCD NVIC_Handler_PS21A_WAKE ; 24Ch: 131, PS2 Port 1A Wake\r
+ DCD NVIC_Handler_PS21B_WAKE ; 250h: 132, PS2 Port 1B Wake\r
+ DCD NVIC_Handler_PS21_WAKE ; 254h: 133, PS2 Port 1 Wake\r
+ DCD NVIC_Handler_ENVMON ; 258h: 134, Thernal Monitor\r
+ DCD NVIC_Handler_KEYSCAN ; 25Ch: 135, Key Scan\r
+ DCD NVIC_Handler_BTMR16_0 ; 260h: 136, 16-bit Basic Timer 0\r
+ DCD NVIC_Handler_BTMR16_1 ; 264h: 137, 16-bit Basic Timer 1\r
+ DCD NVIC_Handler_BTMR16_2 ; 268h: 138, 16-bit Basic Timer 2\r
+ DCD NVIC_Handler_BTMR16_3 ; 26Ch: 139, 16-bit Basic Timer 3\r
+ DCD NVIC_Handler_BTMR32_0 ; 270h: 140, 32-bit Basic Timer 0\r
+ DCD NVIC_Handler_BTMR32_1 ; 274h: 141, 32-bit Basic Timer 1\r
+ DCD NVIC_Handler_EVTMR0 ; 278h: 142, Event Counter/Timer 0\r
+ DCD NVIC_Handler_EVTMR1 ; 27Ch: 143, Event Counter/Timer 1\r
+ DCD NVIC_Handler_EVTMR2 ; 280h: 144, Event Counter/Timer 2\r
+ DCD NVIC_Handler_EVTMR3 ; 284h: 145, Event Counter/Timer 3\r
+ DCD NVIC_Handler_CAPTMR ; 288h: 146, Capture Timer\r
+ DCD NVIC_Handler_CAP0 ; 28Ch: 147, Capture 0 Event\r
+ DCD NVIC_Handler_CAP1 ; 290h: 148, Capture 1 Event\r
+ DCD NVIC_Handler_CAP2 ; 294h: 149, Capture 2 Event\r
+ DCD NVIC_Handler_CAP3 ; 298h: 150, Capture 3 Event\r
+ DCD NVIC_Handler_CAP4 ; 29Ch: 151, Capture 4 Event\r
+ DCD NVIC_Handler_CAP5 ; 2A0h: 152, Capture 5 Event\r
+ DCD NVIC_Handler_CMP0 ; 2A4h: 153, Compare 0 Event\r
+ DCD NVIC_Handler_CMP1 ; 2A8h: 154, Compare 1 Event\r
+ ; Project build information\r
+\r
+ AREA |.text|, CODE, READONLY\r
+; AREA RESET, CODE, READONLY\r
+\r
+; Reset Handler\r
+\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT __main\r
+ IMPORT SystemInit\r
+\r
+ ; Remap vector table\r
+ LDR R0, =__Vectors\r
+ LDR R1, =0xE000ED08\r
+ STR R0, [r1]\r
+ NOP\r
+\r
+ IF {CPU} = "Cortex-M4.fp"\r
+ LDR R0, =0xE000ED88 ; Enable CP10,CP11\r
+ LDR R1,[R0]\r
+ ORR R1,R1,#(0xF << 20)\r
+ STR R1,[R0]\r
+ ENDIF\r
+\r
+ LDR R0, =__main\r
+ BX R0\r
+ ENDP\r
+\r
+\r
+; Dummy Exception Handlers (infinite loops which can be modified)\r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+MemManage_Handler\\r
+ PROC\r
+ EXPORT MemManage_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+BusFault_Handler\\r
+ PROC\r
+ EXPORT BusFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+UsageFault_Handler\\r
+ PROC\r
+ EXPORT UsageFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SVC_Handler PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+DebugMon_Handler\\r
+ PROC\r
+ EXPORT DebugMon_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+PendSV_Handler PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SysTick_Handler PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+Default_Handler PROC\r
+\r
+ EXPORT NVIC_Handler_GIRQ08 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ09 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ10 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ11 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ12 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ13 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ14 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ15 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ16 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ17 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ18 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ19 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ20 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ21 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ23 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ24 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ25 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ26 [WEAK]\r
+\r
+ EXPORT NVIC_Handler_I2C0 [WEAK]\r
+ EXPORT NVIC_Handler_I2C1 [WEAK]\r
+ EXPORT NVIC_Handler_I2C2 [WEAK]\r
+ EXPORT NVIC_Handler_I2C3 [WEAK]\r
+ EXPORT NVIC_Handler_DMA0 [WEAK]\r
+ EXPORT NVIC_Handler_DMA1 [WEAK]\r
+ EXPORT NVIC_Handler_DMA2 [WEAK]\r
+ EXPORT NVIC_Handler_DMA3 [WEAK]\r
+ EXPORT NVIC_Handler_DMA4 [WEAK]\r
+ EXPORT NVIC_Handler_DMA5 [WEAK]\r
+ EXPORT NVIC_Handler_DMA6 [WEAK]\r
+ EXPORT NVIC_Handler_DMA7 [WEAK]\r
+ EXPORT NVIC_Handler_DMA8 [WEAK]\r
+ EXPORT NVIC_Handler_DMA9 [WEAK]\r
+ EXPORT NVIC_Handler_DMA10 [WEAK]\r
+ EXPORT NVIC_Handler_DMA11 [WEAK]\r
+ EXPORT NVIC_Handler_DMA12 [WEAK]\r
+ EXPORT NVIC_Handler_DMA13 [WEAK]\r
+\r
+ EXPORT NVIC_Handler_UART0 [WEAK]\r
+ EXPORT NVIC_Handler_UART1 [WEAK]\r
+ EXPORT NVIC_Handler_EMI0 [WEAK]\r
+ EXPORT NVIC_Handler_EMI1 [WEAK]\r
+ EXPORT NVIC_Handler_EMI2 [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC0_IBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC0_OBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC1_IBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC1_OBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC2_IBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC2_OBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC3_IBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC3_OBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC4_IBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC4_OBF [WEAK]\r
+ EXPORT NVIC_Handler_PM1_CTL [WEAK]\r
+ EXPORT NVIC_Handler_PM1_EN [WEAK]\r
+ EXPORT NVIC_Handler_PM1_STS [WEAK]\r
+ EXPORT NVIC_Handler_MIF8042_OBF [WEAK]\r
+ EXPORT NVIC_Handler_MIF8042_IBF [WEAK]\r
+ EXPORT NVIC_Handler_MB_H2EC [WEAK]\r
+ EXPORT NVIC_Handler_MB_DATA [WEAK]\r
+ EXPORT NVIC_Handler_P80A [WEAK]\r
+ EXPORT NVIC_Handler_P80B [WEAK]\r
+\r
+ EXPORT NVIC_Handler_PKE_ERR [WEAK]\r
+ EXPORT NVIC_Handler_PKE_END [WEAK]\r
+ EXPORT NVIC_Handler_TRNG [WEAK]\r
+ EXPORT NVIC_Handler_AES [WEAK]\r
+ EXPORT NVIC_Handler_HASH [WEAK]\r
+ EXPORT NVIC_Handler_PECI [WEAK]\r
+ EXPORT NVIC_Handler_TACH0 [WEAK]\r
+ EXPORT NVIC_Handler_TACH1 [WEAK]\r
+ EXPORT NVIC_Handler_TACH2 [WEAK]\r
+ EXPORT NVIC_Handler_R2P0_FAIL [WEAK]\r
+ EXPORT NVIC_Handler_R2P0_STALL [WEAK]\r
+ EXPORT NVIC_Handler_R2P1_FAIL [WEAK]\r
+ EXPORT NVIC_Handler_R2P1_STALL [WEAK]\r
+ EXPORT NVIC_Handler_ADC_SNGL [WEAK]\r
+ EXPORT NVIC_Handler_ADC_RPT [WEAK]\r
+ EXPORT NVIC_Handler_RCID0 [WEAK]\r
+ EXPORT NVIC_Handler_RCID1 [WEAK]\r
+ EXPORT NVIC_Handler_RCID2 [WEAK]\r
+ EXPORT NVIC_Handler_LED0 [WEAK]\r
+ EXPORT NVIC_Handler_LED1 [WEAK]\r
+ EXPORT NVIC_Handler_LED2 [WEAK]\r
+ EXPORT NVIC_Handler_LED3 [WEAK]\r
+ EXPORT NVIC_Handler_PHOT [WEAK]\r
+ EXPORT NVIC_Handler_PWRGD0 [WEAK]\r
+ EXPORT NVIC_Handler_PWRGD1 [WEAK]\r
+ EXPORT NVIC_Handler_LPCBERR [WEAK]\r
+ EXPORT NVIC_Handler_QMSPI0 [WEAK]\r
+ EXPORT NVIC_Handler_GPSPI0_TX [WEAK]\r
+ EXPORT NVIC_Handler_GPSPI0_RX [WEAK]\r
+ EXPORT NVIC_Handler_GPSPI1_TX [WEAK]\r
+ EXPORT NVIC_Handler_GPSPI1_RX [WEAK]\r
+ EXPORT NVIC_Handler_BC0_BUSY [WEAK]\r
+ EXPORT NVIC_Handler_BC0_ERR [WEAK]\r
+ EXPORT NVIC_Handler_BC1_BUSY [WEAK]\r
+ EXPORT NVIC_Handler_BC1_ERR [WEAK]\r
+ EXPORT NVIC_Handler_PS2_0 [WEAK]\r
+ EXPORT NVIC_Handler_PS2_1 [WEAK]\r
+ EXPORT NVIC_Handler_PS2_2 [WEAK]\r
+ EXPORT NVIC_Handler_ESPI_PC [WEAK]\r
+ EXPORT NVIC_Handler_ESPI_BM1 [WEAK]\r
+ EXPORT NVIC_Handler_ESPI_BM2 [WEAK]\r
+ EXPORT NVIC_Handler_ESPI_LTR [WEAK]\r
+ EXPORT NVIC_Handler_ESPI_OOB_UP [WEAK]\r
+ EXPORT NVIC_Handler_ESPI_OOB_DN [WEAK]\r
+ EXPORT NVIC_Handler_ESPI_FLASH [WEAK]\r
+ EXPORT NVIC_Handler_ESPI_RESET [WEAK]\r
+ EXPORT NVIC_Handler_RTMR [WEAK]\r
+ EXPORT NVIC_Handler_HTMR0 [WEAK]\r
+ EXPORT NVIC_Handler_HTMR1 [WEAK]\r
+ EXPORT NVIC_Handler_WK [WEAK]\r
+ EXPORT NVIC_Handler_WKSUB [WEAK]\r
+ EXPORT NVIC_Handler_WKSEC [WEAK]\r
+ EXPORT NVIC_Handler_WKSUBSEC [WEAK]\r
+ EXPORT NVIC_Handler_SYSPWR [WEAK]\r
+ EXPORT NVIC_Handler_RTC [WEAK]\r
+ EXPORT NVIC_Handler_RTC_ALARM [WEAK]\r
+ EXPORT NVIC_Handler_VCI_OVRD_IN [WEAK]\r
+ EXPORT NVIC_Handler_VCI_IN0 [WEAK]\r
+ EXPORT NVIC_Handler_VCI_IN1 [WEAK]\r
+ EXPORT NVIC_Handler_VCI_IN2 [WEAK]\r
+ EXPORT NVIC_Handler_VCI_IN3 [WEAK]\r
+ EXPORT NVIC_Handler_VCI_IN4 [WEAK]\r
+ EXPORT NVIC_Handler_VCI_IN5 [WEAK]\r
+ EXPORT NVIC_Handler_VCI_IN6 [WEAK]\r
+ EXPORT NVIC_Handler_PS20A_WAKE [WEAK]\r
+ EXPORT NVIC_Handler_PS20B_WAKE [WEAK]\r
+ EXPORT NVIC_Handler_PS21A_WAKE [WEAK]\r
+ EXPORT NVIC_Handler_PS21B_WAKE [WEAK]\r
+ EXPORT NVIC_Handler_PS21_WAKE [WEAK]\r
+ EXPORT NVIC_Handler_ENVMON [WEAK]\r
+ EXPORT NVIC_Handler_KEYSCAN [WEAK]\r
+ EXPORT NVIC_Handler_BTMR16_0 [WEAK]\r
+ EXPORT NVIC_Handler_BTMR16_1 [WEAK]\r
+ EXPORT NVIC_Handler_BTMR16_2 [WEAK]\r
+ EXPORT NVIC_Handler_BTMR16_3 [WEAK]\r
+ EXPORT NVIC_Handler_BTMR32_0 [WEAK]\r
+ EXPORT NVIC_Handler_BTMR32_1 [WEAK]\r
+ EXPORT NVIC_Handler_EVTMR0 [WEAK]\r
+ EXPORT NVIC_Handler_EVTMR1 [WEAK]\r
+ EXPORT NVIC_Handler_EVTMR2 [WEAK]\r
+ EXPORT NVIC_Handler_EVTMR3 [WEAK]\r
+ EXPORT NVIC_Handler_CAPTMR [WEAK]\r
+ EXPORT NVIC_Handler_CAP0 [WEAK]\r
+ EXPORT NVIC_Handler_CAP1 [WEAK]\r
+ EXPORT NVIC_Handler_CAP2 [WEAK]\r
+ EXPORT NVIC_Handler_CAP3 [WEAK]\r
+ EXPORT NVIC_Handler_CAP4 [WEAK]\r
+ EXPORT NVIC_Handler_CAP5 [WEAK]\r
+ EXPORT NVIC_Handler_CMP0 [WEAK]\r
+ EXPORT NVIC_Handler_CMP1 [WEAK]\r
+\r
+NVIC_Handler_GIRQ08\r
+NVIC_Handler_GIRQ09\r
+NVIC_Handler_GIRQ10\r
+NVIC_Handler_GIRQ11\r
+NVIC_Handler_GIRQ12\r
+NVIC_Handler_GIRQ13\r
+NVIC_Handler_GIRQ14\r
+NVIC_Handler_GIRQ15\r
+NVIC_Handler_GIRQ16\r
+NVIC_Handler_GIRQ17\r
+NVIC_Handler_GIRQ18\r
+NVIC_Handler_GIRQ19\r
+NVIC_Handler_GIRQ20\r
+NVIC_Handler_GIRQ21\r
+NVIC_Handler_GIRQ23\r
+NVIC_Handler_GIRQ24\r
+NVIC_Handler_GIRQ25\r
+NVIC_Handler_GIRQ26\r
+\r
+NVIC_Handler_I2C0\r
+NVIC_Handler_I2C1\r
+NVIC_Handler_I2C2\r
+NVIC_Handler_I2C3\r
+NVIC_Handler_DMA0\r
+NVIC_Handler_DMA1\r
+NVIC_Handler_DMA2\r
+NVIC_Handler_DMA3\r
+NVIC_Handler_DMA4\r
+NVIC_Handler_DMA5\r
+NVIC_Handler_DMA6\r
+NVIC_Handler_DMA7\r
+NVIC_Handler_DMA8\r
+NVIC_Handler_DMA9\r
+NVIC_Handler_DMA10\r
+NVIC_Handler_DMA11\r
+NVIC_Handler_DMA12\r
+NVIC_Handler_DMA13\r
+\r
+NVIC_Handler_UART0\r
+NVIC_Handler_UART1\r
+NVIC_Handler_EMI0\r
+NVIC_Handler_EMI1\r
+NVIC_Handler_EMI2\r
+NVIC_Handler_ACPI_EC0_IBF\r
+NVIC_Handler_ACPI_EC0_OBF\r
+NVIC_Handler_ACPI_EC1_IBF\r
+NVIC_Handler_ACPI_EC1_OBF\r
+NVIC_Handler_ACPI_EC2_IBF\r
+NVIC_Handler_ACPI_EC2_OBF\r
+NVIC_Handler_ACPI_EC3_IBF\r
+NVIC_Handler_ACPI_EC3_OBF\r
+NVIC_Handler_ACPI_EC4_IBF\r
+NVIC_Handler_ACPI_EC4_OBF\r
+NVIC_Handler_PM1_CTL\r
+NVIC_Handler_PM1_EN\r
+NVIC_Handler_PM1_STS\r
+NVIC_Handler_MIF8042_OBF\r
+NVIC_Handler_MIF8042_IBF\r
+NVIC_Handler_MB_H2EC\r
+NVIC_Handler_MB_DATA\r
+NVIC_Handler_P80A\r
+NVIC_Handler_P80B\r
+\r
+NVIC_Handler_PKE_ERR\r
+NVIC_Handler_PKE_END\r
+NVIC_Handler_TRNG\r
+NVIC_Handler_AES\r
+NVIC_Handler_HASH\r
+NVIC_Handler_PECI\r
+NVIC_Handler_TACH0\r
+NVIC_Handler_TACH1\r
+NVIC_Handler_TACH2\r
+NVIC_Handler_R2P0_FAIL\r
+NVIC_Handler_R2P0_STALL\r
+NVIC_Handler_R2P1_FAIL\r
+NVIC_Handler_R2P1_STALL\r
+NVIC_Handler_ADC_SNGL\r
+NVIC_Handler_ADC_RPT\r
+NVIC_Handler_RCID0\r
+NVIC_Handler_RCID1\r
+NVIC_Handler_RCID2\r
+NVIC_Handler_LED0\r
+NVIC_Handler_LED1\r
+NVIC_Handler_LED2\r
+NVIC_Handler_LED3\r
+NVIC_Handler_PHOT\r
+NVIC_Handler_PWRGD0\r
+NVIC_Handler_PWRGD1\r
+NVIC_Handler_LPCBERR\r
+NVIC_Handler_QMSPI0\r
+NVIC_Handler_GPSPI0_TX\r
+NVIC_Handler_GPSPI0_RX\r
+NVIC_Handler_GPSPI1_TX\r
+NVIC_Handler_GPSPI1_RX\r
+NVIC_Handler_BC0_BUSY\r
+NVIC_Handler_BC0_ERR\r
+NVIC_Handler_BC1_BUSY\r
+NVIC_Handler_BC1_ERR\r
+NVIC_Handler_PS2_0\r
+NVIC_Handler_PS2_1\r
+NVIC_Handler_PS2_2\r
+NVIC_Handler_ESPI_PC\r
+NVIC_Handler_ESPI_BM1\r
+NVIC_Handler_ESPI_BM2\r
+NVIC_Handler_ESPI_LTR\r
+NVIC_Handler_ESPI_OOB_UP\r
+NVIC_Handler_ESPI_OOB_DN\r
+NVIC_Handler_ESPI_FLASH\r
+NVIC_Handler_ESPI_RESET\r
+NVIC_Handler_RTMR\r
+NVIC_Handler_HTMR0\r
+NVIC_Handler_HTMR1\r
+NVIC_Handler_WK\r
+NVIC_Handler_WKSUB\r
+NVIC_Handler_WKSEC\r
+NVIC_Handler_WKSUBSEC\r
+NVIC_Handler_SYSPWR\r
+NVIC_Handler_RTC\r
+NVIC_Handler_RTC_ALARM\r
+NVIC_Handler_VCI_OVRD_IN\r
+NVIC_Handler_VCI_IN0\r
+NVIC_Handler_VCI_IN1\r
+NVIC_Handler_VCI_IN2\r
+NVIC_Handler_VCI_IN3\r
+NVIC_Handler_VCI_IN4\r
+NVIC_Handler_VCI_IN5\r
+NVIC_Handler_VCI_IN6\r
+NVIC_Handler_PS20A_WAKE\r
+NVIC_Handler_PS20B_WAKE\r
+NVIC_Handler_PS21A_WAKE\r
+NVIC_Handler_PS21B_WAKE\r
+NVIC_Handler_PS21_WAKE\r
+NVIC_Handler_ENVMON\r
+NVIC_Handler_KEYSCAN\r
+NVIC_Handler_BTMR16_0\r
+NVIC_Handler_BTMR16_1\r
+NVIC_Handler_BTMR16_2\r
+NVIC_Handler_BTMR16_3\r
+NVIC_Handler_BTMR32_0\r
+NVIC_Handler_BTMR32_1\r
+NVIC_Handler_EVTMR0\r
+NVIC_Handler_EVTMR1\r
+NVIC_Handler_EVTMR2\r
+NVIC_Handler_EVTMR3\r
+NVIC_Handler_CAPTMR\r
+NVIC_Handler_CAP0\r
+NVIC_Handler_CAP1\r
+NVIC_Handler_CAP2\r
+NVIC_Handler_CAP3\r
+NVIC_Handler_CAP4\r
+NVIC_Handler_CAP5\r
+NVIC_Handler_CMP0\r
+NVIC_Handler_CMP1\r
+ B .\r
+\r
+ ENDP\r
+\r
+\r
+ ALIGN\r
+\r
+\r
+; User Initial Stack & Heap\r
+\r
+ IF :DEF:__MICROLIB\r
+\r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+\r
+ ELSE\r
+\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+\r
+ END\r
projects / freertos / blobdiff