+++ /dev/null
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #1 $ \r
-$DateTime: 2016/09/22 08:03:49 $ \r
-$Author: pramans $\r
-Last Change: Updated for tabs\r
-******************************************************************************/\r
-/** @file pcr.h\r
-* \brief Power, Clocks, and Resets Header file\r
-* \author jvasanth\r
-* \r
-* This file is the PCR header file \r
-******************************************************************************/\r
-\r
-/** @defgroup PCR\r
- * @{\r
- */\r
-\r
-#ifndef _PCR_H\r
-#define _PCR_H\r
-\r
-\r
-/******************************************************************************/\r
-/** PCR Register IDS \r
- *******************************************************************************/\r
-enum _PCR_REGSET_ID_\r
-{\r
- PCR_REG_SYSTEM_SLEEP_CTRL = 0, \r
- PCR_REG_PROCESSOR_CLK_CTRL, \r
- PCR_REG_SLOW_CLK_CTRL,\r
- PCR_REG_OSCILLATOR_ID,\r
- PCR_REG_PWR_RESET_STS,\r
- PCR_REG_PWR_RESET_CTRL,\r
- PCR_REG_SYSTEM_RESET,\r
- PCR_TEST0,\r
- PCR_TEST1,\r
- PCR_REG_EC_SLEEP_ENABLE_0 = 12,\r
- PCR_REG_EC_SLEEP_ENABLE_1,\r
- PCR_REG_EC_SLEEP_ENABLE_2,\r
- PCR_REG_EC_SLEEP_ENABLE_3, \r
- PCR_REG_EC_SLEEP_ENABLE_4, \r
- PCR_REG_EC_CLK_REQD_STS_0 = 20,\r
- PCR_REG_EC_CLK_REQD_STS_1,\r
- PCR_REG_EC_CLK_REQD_STS_2,\r
- PCR_REG_EC_CLK_REQD_STS_3,\r
- PCR_REG_EC_CLK_REQD_STS_4,\r
- PCR_REG_EC_RESET_ENABLE_0 = 28,\r
- PCR_REG_EC_RESET_ENABLE_1,\r
- PCR_REG_EC_RESET_ENABLE_2,\r
- PCR_REG_EC_RESET_ENABLE_3,\r
- PCR_REG_EC_RESET_ENABLE_4,\r
- \r
-};\r
-/* ---------------------------------------------------------------------- */\r
-\r
-// Encode the Register ids for Sleep Enable, Clock Required, Reset Enable\r
-//PCR register group 0 - EC 0\r
-#define PCR0_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_0) & 0xFF) + \\r
- (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_0) & 0xFF)<<8u) + \\r
- (((uint32_t)(PCR_REG_EC_RESET_ENABLE_0) & 0xFF)<<16u))\r
-\r
-//PCR register group 1 - EC 1\r
-#define PCR1_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_1) & 0xFF) + \\r
- (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_1) & 0xFF)<<8u) + \\r
- (((uint32_t)(PCR_REG_EC_RESET_ENABLE_1) & 0xFF)<<16u))\r
-\r
-//PCR register group 2 - EC 2\r
-#define PCR2_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_2) & 0xFF) + \\r
- (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_2) & 0xFF)<<8u) + \\r
- (((uint32_t)(PCR_REG_EC_RESET_ENABLE_2) & 0xFF)<<16u))\r
-\r
-//PCR register group 3 - EC 3\r
-#define PCR3_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_3) & 0xFF) + \\r
- (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_3) & 0xFF)<<8u) + \\r
- (((uint32_t)(PCR_REG_EC_RESET_ENABLE_3) & 0xFF)<<16u))\r
- \r
-//PCR register group 4 - EC 4\r
-#define PCR4_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_4) & 0xFF) + \\r
- (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_4) & 0xFF)<<8u) + \\r
- (((uint32_t)(PCR_REG_EC_RESET_ENABLE_4) & 0xFF)<<16u))\r
- \r
-//PCR0_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
-#define PCR0_EC_JTAG_STAP_BITPOS (0u)\r
-#define PCR0_EC_EFUSE_BITPOS (1u)\r
-#define PCR0_EC_ISPI_BITPOS (2u)\r
-\r
-//PCR1_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
-#define PCR1_EC_INT_BITPOS (0u)\r
-#define PCR1_EC_PECI_BITPOS (1u)\r
-#define PCR1_EC_TACH0_BITPOS (2u)\r
-#define PCR1_EC_PWM0_BITPOS (4u)\r
-#define PCR1_EC_PMC_BITPOS (5u)\r
-#define PCR1_EC_DMA_BITPOS (6u)\r
-#define PCR1_EC_TFDP_BITPOS (7u)\r
-#define PCR1_EC_CPU_BITPOS (8u)\r
-#define PCR1_EC_WDT_BITPOS (9u)\r
-#define PCR1_EC_SMB0_BITPOS (10u)\r
-#define PCR1_EC_TACH1_BITPOS (11u)\r
-#define PCR1_EC_TACH2_BITPOS (12u)\r
-#define PCR1_EC_PWM1_BITPOS (20u)\r
-#define PCR1_EC_PWM2_BITPOS (21u)\r
-#define PCR1_EC_PWM3_BITPOS (22u)\r
-#define PCR1_EC_PWM4_BITPOS (23u)\r
-#define PCR1_EC_PWM5_BITPOS (24u)\r
-#define PCR1_EC_PWM6_BITPOS (25u)\r
-#define PCR1_EC_PWM7_BITPOS (26u)\r
-#define PCR1_EC_PWM8_BITPOS (27u)\r
-#define PCR1_EC_REG_BITPOS (29u)\r
-#define PCR1_EC_BTIMER0_BITPOS (30u)\r
-#define PCR1_EC_BTIMER1_BITPOS (31u)\r
-\r
-//PCR2_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
-#define PCR2_EC_LPC_BITPOS (0u)\r
-#define PCR2_EC_UART0_BITPOS (1u)\r
-#define PCR2_EC_UART1_BITPOS (2u)\r
-#define PCR2_EC_GLBL_CFG_BITPOS (12u)\r
-#define PCR2_EC_ACPI_EC0_BITPOS (13u)\r
-#define PCR2_EC_ACPI_EC1_BITPOS (14u)\r
-#define PCR2_EC_ACPI_PM1_BITPOS (15u)\r
-#define PCR2_EC_8042EM_BITPOS (16u)\r
-#define PCR2_EC_MBOX_BITPOS (17u)\r
-#define PCR2_EC_RTC_BITPOS (18u)\r
-#define PCR2_EC_ESPI_BITPOS (19u)\r
-#define PCR2_EC_ACPI_EC_2_BITPOS (21u)\r
-#define PCR2_EC_ACPI_EC_3_BITPOS (22u)\r
-#define PCR2_EC_ACPI_EC_BITPOS (23u)\r
-#define PCR2_EC_PORT80_0_BITPOS (25u)\r
-#define PCR2_EC_PORT80_1_BITPOS (26u)\r
-\r
-//PCR3_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
-#define PCR3_EC_ADC_BITPOS (3u)\r
-#define PCR3_EC_PS2_0_BITPOS (5u)\r
-#define PCR3_EC_PS2_1_BITPOS (6u)\r
-#define PCR3_EC_PS2_2_BITPOS (7u)\r
-#define PCR3_EC_SPI0_BITPOS (9u)\r
-#define PCR3_EC_HTIMER_BITPOS (10u)\r
-#define PCR3_EC_KEYSCAN_BITPOS (11u)\r
-#define PCR3_EC_RPM_PWM_BITPOS (12u)\r
-#define PCR3_EC_SMB1_BITPOS (13u)\r
-#define PCR3_EC_SMB2_BITPOS (14u)\r
-#define PCR3_EC_SMB3_BITPOS (15u)\r
-#define PCR3_EC_LED0_BITPOS (16u)\r
-#define PCR3_EC_LED1_BITPOS (17u)\r
-#define PCR3_EC_LED2_BITPOS (18u)\r
-#define PCR3_EC_BCM_BITPOS (19u)\r
-#define PCR3_EC_SPI1_BITPOS (20u)\r
-#define PCR3_EC_BTIMER2_BITPOS (21u)\r
-#define PCR3_EC_BTIMER3_BITPOS (22u)\r
-#define PCR3_EC_BTIMER4_BITPOS (23u)\r
-#define PCR3_EC_BTIMER5_BITPOS (24u)\r
-#define PCR3_EC_LED3_BITPOS (25u)\r
-#define PCR3_EC_PKE_BITPOS (26u)\r
-#define PCR3_EC_RNG_BITPOS (27u)\r
-#define PCR3_EC_AES_BITPOS (28u)\r
-#define PCR3_EC_HTIMER_1_BITPOS (29u)\r
-#define PCR3_EC_C_C_TIMER_BITPOS (30u)\r
-#define PCR3_EC_PWM9_BITPOS (31u)\r
-\r
-\r
-//PCR4_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
-#define PCR4_EC_PWM10_BITPOS (0u)\r
-#define PCR4_EC_PWM11_BITPOS (1u)\r
-#define PCR4_EC_CTIMER0_BITPOS (2u)\r
-#define PCR4_EC_CTIMER1_BITPOS (3u)\r
-#define PCR4_EC_CTIMER2_BITPOS (4u)\r
-#define PCR4_EC_CTIMER3_BITPOS (5u)\r
-#define PCR4_EC_RTOS_TIMER_BITPOS (6u)\r
-#define PCR4_EC_RPM2_PWM_BITPOS (7u)\r
-#define PCR4_EC_QMSPI_BITPOS (8u)\r
-#define PCR4_EC_BCM_1_BITPOS (9u)\r
-#define PCR4_EC_RC_ID0_BITPOS (10u)\r
-#define PCR4_EC_RC_ID1_BITPOS (11u)\r
-#define PCR4_EC_RC_ID2_BITPOS (12u)\r
-#define PCR4_EC_PROCHOT_BITPOS (13u)\r
-#define PCR4_EC_EEPROM_BITPOS (14u)\r
-#define PCR4_EC_CUST_LOG_BITPOS (15u)\r
-\r
-\r
-/*\r
- * n = b[7:0] = PCR Reg Bit Position\r
- * m = b[31:8] = PCRx Regs IDs\r
- */\r
-//#define PCRx_REGS_BIT(m,n) ((((uint32_t)(m)&0xFFFFFFul)<<8u) + ((uint32_t)(n)&0xFFul)) \r
-\r
-//PCRx_REGS_BIT positions \r
-#define PCRx_REGS_POS_SLEEP_ENABLE (8u)\r
-#define PCRx_REGS_POS_CLK_REQD_STS (16u)\r
-#define PCRx_REGS_POS_RESET_ENABLE (24u) \r
-\r
-\r
-/******************************************************************************/\r
-/** PCR Block IDS. \r
- * These IDs are used to directly refer to a block \r
- *******************************************************************************/\r
-typedef enum {\r
- PCR_JTAG = (((uint32_t)(PCR0_REGS_EC) << 8) + (uint32_t)(PCR0_EC_JTAG_STAP_BITPOS & 0xFFu)),\r
- PCR_EFUSE = (((uint32_t)(PCR0_REGS_EC) << 8) + (uint32_t)(PCR0_EC_EFUSE_BITPOS & 0xFFu)),\r
- PCR_ISPI = (((uint32_t)(PCR0_REGS_EC) << 8) + (uint32_t)(PCR0_EC_ISPI_BITPOS & 0xFFu)),\r
- \r
- PCR_INT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_INT_BITPOS & 0xFFu)), \r
- PCR_PECI = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PECI_BITPOS & 0xFFu)), \r
- PCR_TACH0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH0_BITPOS & 0xFFu)), \r
- PCR_PWM0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM0_BITPOS & 0xFFu)), \r
- PCR_PMC = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PMC_BITPOS & 0xFFu)), \r
- PCR_DMA = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_DMA_BITPOS & 0xFFu)), \r
- PCR_TFDP = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TFDP_BITPOS & 0xFFu)), \r
- PCR_CPU = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_CPU_BITPOS & 0xFFu)), \r
- PCR_WDT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_WDT_BITPOS & 0xFFu)), \r
- PCR_SMB0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_SMB0_BITPOS & 0xFFu)), \r
- PCR_TACH1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH1_BITPOS & 0xFFu)),\r
- PCR_TACH2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH2_BITPOS & 0xFFu)), \r
- PCR_PWM1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM1_BITPOS & 0xFFu)), \r
- PCR_PWM2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM2_BITPOS & 0xFFu)), \r
- PCR_PWM3 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM3_BITPOS & 0xFFu)), \r
- PCR_PWM4 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM4_BITPOS & 0xFFu)), \r
- PCR_PWM5 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM5_BITPOS & 0xFFu)), \r
- PCR_PWM6 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM6_BITPOS & 0xFFu)), \r
- PCR_PWM7 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM7_BITPOS & 0xFFu)), \r
- PCR_PWM8 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM8_BITPOS & 0xFFu)), \r
- PCR_REG = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_REG_BITPOS & 0xFFu)), \r
- PCR_BTIMER0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER0_BITPOS & 0xFFu)), \r
- PCR_BTIMER1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER1_BITPOS & 0xFFu)), \r
- \r
- PCR_LPC = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_LPC_BITPOS & 0xFFu)),\r
- PCR_UART0 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_UART0_BITPOS & 0xFFu)),\r
- PCR_UART1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_UART1_BITPOS & 0xFFu)),\r
- PCR_GLBL_CFG = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_GLBL_CFG_BITPOS & 0xFFu)),\r
- PCR_ACPI_EC0 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC0_BITPOS & 0xFFu)),\r
- PCR_ACPI_EC1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC1_BITPOS & 0xFFu)),\r
- PCR_ACPI_PM1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_PM1_BITPOS & 0xFFu)),\r
- PCR_8042EM = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_8042EM_BITPOS & 0xFFu)),\r
- PCR_MBOX = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_MBOX_BITPOS & 0xFFu)),\r
- PCR_RTC = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_RTC_BITPOS & 0xFFu)),\r
- PCR_ESPI = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ESPI_BITPOS & 0xFFu)),\r
- PCR_ACPI_EC2 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC_2_BITPOS & 0xFFu)),\r
- PCR_ACPI_EC3 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC_3_BITPOS & 0xFFu)),\r
- PCR_ACPI_EC = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC_BITPOS & 0xFFu)),\r
- PCR_PORT80_0 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_PORT80_0_BITPOS & 0xFFu)),\r
- PCR_PORT80_1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_PORT80_1_BITPOS & 0xFFu)),\r
- \r
- PCR_ADC = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_ADC_BITPOS & 0xFFu)),\r
- PCR_PS2_0 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PS2_0_BITPOS & 0xFFu)), \r
- PCR_PS2_1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PS2_1_BITPOS & 0xFFu)), \r
- PCR_PS2_2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PS2_2_BITPOS & 0xFFu)), \r
- PCR_SPI0 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SPI0_BITPOS & 0xFFu)), \r
- PCR_HTIMER = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_HTIMER_BITPOS & 0xFFu)), \r
- PCR_KEYSCAN = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_KEYSCAN_BITPOS & 0xFFu)), \r
- PCR_RPM_PWM = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_RPM_PWM_BITPOS & 0xFFu)), \r
- PCR_SMB1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SMB1_BITPOS & 0xFFu)), \r
- PCR_SMB2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SMB2_BITPOS & 0xFFu)), \r
- PCR_SMB3 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SMB3_BITPOS & 0xFFu)), \r
- PCR_LED0 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED0_BITPOS & 0xFFu)), \r
- PCR_LED1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED1_BITPOS & 0xFFu)), \r
- PCR_LED2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED2_BITPOS & 0xFFu)), \r
- PCR_BCM = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BCM_BITPOS & 0xFFu)), \r
- PCR_SPI1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SPI1_BITPOS & 0xFFu)), \r
- PCR_BTIMER2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER2_BITPOS & 0xFFu)), \r
- PCR_BTIMER3 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER3_BITPOS & 0xFFu)), \r
- PCR_BTIMER4 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER4_BITPOS & 0xFFu)), \r
- PCR_BTIMER5 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER5_BITPOS & 0xFFu)), \r
- PCR_LED3 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED3_BITPOS & 0xFFu)), \r
- PCR_PKE = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PKE_BITPOS & 0xFFu)), \r
- PCR_RNG = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_RNG_BITPOS & 0xFFu)), \r
- PCR_AES = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_AES_BITPOS & 0xFFu)), \r
- PCR_HTIMER_1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_HTIMER_1_BITPOS & 0xFFu)), \r
- PCR_C_C_TIMER = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_C_C_TIMER_BITPOS & 0xFFu)), \r
- PCR_PWM9 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PWM9_BITPOS & 0xFFu)),\r
- \r
- PCR_PWM10 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_PWM10_BITPOS & 0xFFu)), \r
- PCR_PWM11 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_PWM11_BITPOS & 0xFFu)), \r
- PCR_CTIMER0 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER0_BITPOS & 0xFFu)), \r
- PCR_CTIMER1 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER1_BITPOS & 0xFFu)), \r
- PCR_CTIMER2 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER2_BITPOS & 0xFFu)), \r
- PCR_CTIMER3 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER3_BITPOS & 0xFFu)), \r
- PCR_RTOS_TIMER = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RTOS_TIMER_BITPOS & 0xFFu)), \r
- PCR_RPM2_PWM = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RPM2_PWM_BITPOS & 0xFFu)), \r
- PCR_QMSPI = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_QMSPI_BITPOS & 0xFFu)), \r
- PCR_BCM1 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_BCM_1_BITPOS & 0xFFu)), \r
- PCR_RCID0 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RC_ID0_BITPOS & 0xFFu)), \r
- PCR_RCID1 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RC_ID1_BITPOS & 0xFFu)), \r
- PCR_RCID2 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RC_ID2_BITPOS & 0xFFu)), \r
- PCR_PROCHOT = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_PROCHOT_BITPOS & 0xFFu)), \r
- PCR_EEPROM = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_EEPROM_BITPOS & 0xFFu)), \r
- PCR_CUST_LOG = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CUST_LOG_BITPOS & 0xFFu)), \r
-} PCR_BLK_ID;\r
-\r
-\r
-/******************************************************************************/\r
-/** PCR Processor ClK Divide Values \r
- *******************************************************************************/\r
-enum PROCESSOR_CLK_DIVIDE_VALUE\r
-{\r
- PCR_CPU_CLK_DIVIDE_1 = 1,\r
- PCR_CPU_CLK_DIVIDE_2 = 2,\r
- PCR_CPU_CLK_DIVIDE_3 = 3,\r
- PCR_CPU_CLK_DIVIDE_4 = 4,\r
- PCR_CPU_CLK_DIVIDE_16 = 16,\r
- PCR_CPU_CLK_DIVIDE_48 = 48 \r
-};\r
-\r
-/******************************************************************************/\r
-/** System Sleep Modes \r
- *******************************************************************************/\r
-enum SYSTEM_SLEEP_MODES\r
-{\r
- SYSTEM_LIGHT_SLEEP = 0, \r
- SYSTEM_HEAVY_SLEEP = 1,\r
- SYSTEM_SLEEP_ALL = 4\r
-};\r
-\r
-/* Bitmask for Power Reset Status Register */\r
-#define PCR_PWR_RESET_STS_VCC_PWRGD_RESET_STS_BITMASK (1UL<<2)\r
-#define PCR_PWR_RESET_STS_HOST_RESET_STS_BITMASK (1UL<<3)\r
-#define PCR_PWR_RESET_STS_VBAT_RESET_STS_BITMASK (1UL<<5)\r
-#define PCR_PWR_RESET_STS_VTR_RESET_STS_BITMASK (1UL<<6)\r
-#define PCR_PWR_RESET_STS_JTAG_RESET_STS_BITMASK (1UL<<7)\r
-#define PCR_PWR_RESET_STS_32K_ACTIVE_STS_BITMASK (1UL<<10)\r
-#define PCR_PWR_RESET_STS_PCICLK_ACTIVE_STS_BITMASK (1UL<<11)\r
-#define PCR_PWR_RESET_STS_ESPICLK_ACTIVE_STS_BITMASK (1UL<<12)\r
-\r
-/* Bitmask for Processor Clock Control Register */\r
-#define PCR_OSCILLATOR_LOCK_STATUS_BITMASK (1UL<<8)\r
-\r
-/* Bitmask for Power Reset Control Register */\r
-#define PCR_PWR_RESET_CTRL_PWR_INV_BITMASK (1UL<<0)\r
-#define PCR_PWR_RESET_CTRL_HOST_RST_SELECT_BITMASK (1UL<<8)\r
-\r
-/* Bitmask for OScillator ID register */\r
-#define PCR_OSCILLATOR_ID_FOUNDARY_BITMASK (3UL<<5)\r
-#define PCR_OSCILLATOR_ID_REVISION_BITMASK (0xFUL)\r
-\r
-#define PCR_OSCILLATOR_ID_FOUNDARY_CHART_TSMC (0UL)\r
-#define PCR_OSCILLATOR_ID_FOUNDARY_TSMC (0x10u)\r
-#define PCR_OSCILLATOR_ID_FOUNDARY_CHART (0x20u)\r
-#define PCR_OSCILLATOR_ID_FOUNDARY_GRACE (0x30u)\r
-\r
-/* Bitmask for PKE Clock register */\r
-#define PCR_PKE_CLOCK_REG_PKE_CLK_BITMASK (1UL<<1)\r
-#define PCR_PKE_CLOCK_REG_AUTO_SWITCH_BITMASK (1UL<<0)\r
-\r
-#define PCR_PKE_CLOCK_REG_PKE_CLK_48MHZ (1UL<<1)\r
-#define PCR_PKE_CLOCK_REG_PKE_CLK_96MHZ (0UL<<0)\r
-#define PCR_PKE_CLOCK_REG_AUTO_SWITCH_EN (1UL<<0)\r
-#define PCR_PKE_CLOCK_REG_AUTO_SWITCH_DIS (0UL<<0)\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions to program Sleep Enable, CLK Reqd Status, *\r
- * Reset Enable for a block *\r
- * ---------------------------------------------------------------------- */\r
- /** Sets or Clears block specific bit in PCR Sleep Enable Register\r
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
- * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register\r
- */\r
-void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);\r
-\r
-/** Get Clock Required Status for the block\r
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
- * @return uint8_t - 1 if Clock Required Status set, else 0\r
- */\r
-uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id);\r
-\r
-/** Sets or Clears Reset Enable register bit for the block\r
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
- * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register\r
- */\r
-void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions for entering low power modes */\r
-/* ---------------------------------------------------------------------- */\r
-/** Instructs all blocks to sleep by setting the Sleep Enable bits */\r
-void pcr_all_blocks_sleep(void);\r
-\r
-/** Clears the Sleep Enable bits for all blocks */\r
-void pcr_all_blocks_wake(void);\r
-\r
-/** Programs required sleep mode in System Sleep Control Register\r
- * @param sleep_mode - see enum SYSTEM_SLEEP_MODES\r
- */\r
-void pcr_system_sleep(uint8_t sleep_mode);\r
-\r
-/** Reads the value of Power Reset status register\r
- * @param none\r
- * @return Power Status Reg value\r
- */\r
-uint16_t pcr_power_reset_status_read(void);\r
-\r
-/** Reads the value of Power Reset control register\r
- * @param none\r
- * @return Power reset control Reg value\r
- */\r
-uint16_t pcr_power_reset_ctrl_read(void);\r
-\r
-/** Sets the value of PWR_INV bit to 1 or 0\r
-* @param set_clr: 1 or 0\r
- * @return none\r
- */\r
-void pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr);\r
-\r
-/** Sets the value of HOST_RESET bit to 1 or 0\r
-* @param set_clr: 1 or 0\r
- * @return none\r
- */\r
-void pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr);\r
-\r
-/** Sets the SOFT SYS RESET bit to 1\r
-* @param none\r
- * @return none\r
- */\r
-void pcr_system_reset_set(void);\r
-\r
-/** Writes to the PKE Clock register\r
-* @param clock value\r
- * @return none\r
- */\r
-void pcr_pke_clock_write(uint8_t pke_clk_val);\r
-\r
-/** Reads the PKE clock register\r
-* @param none\r
- * @return clock value\r
- */\r
-uint8_t pcr_pke_clock_read(void);\r
-\r
-/** Writes to the OSC cal register\r
-* @param calibration value: 1 or 0\r
- * @return none\r
- */\r
-void pcr_osc_cal_write(uint8_t pke_clk_val);\r
-\r
-/** Reads the osc cal register\r
-* @param none\r
- * @return cal value\r
- */\r
-uint8_t pcr_osc_cal_read(void);\r
-\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions to program and read 32-bit values *\r
- * from PCR Registers *\r
- * ---------------------------------------------------------------------- */\r
- /** Write 32-bit value in the PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param value - 32-bit value\r
- */\r
-void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value);\r
-\r
-/** Reads 32-bit value from the PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @return value - 32-bit value\r
- */\r
-uint32_t p_pcr_reg_read(uint8_t pcr_reg_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions to set, clr and get bits in *\r
- * PCR Registers * \r
- * ---------------------------------------------------------------------- */\r
- /** Sets bits in a PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to set \r
- */\r
-void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask);\r
-\r
-/** Clears bits in a PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to clear \r
- */\r
-void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask);\r
-\r
-/** Read bits in a PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to read \r
- * @return value - 32-bit value\r
- */\r
-uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask);\r
-\r
-/** Sets or Clears bits in a PCR Register - Helper Function\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to set or clear\r
- * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register\r
- */\r
-void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag);\r
- \r
-//Functions to operate on System Sleep Control Register \r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions to operate on System Sleep Control *\r
- * Register * \r
- * ---------------------------------------------------------------------- */\r
-/** Writes required sleep mode in System Sleep Control Register\r
- * @param sleep_value - System Sleep control value - [D2, D1, D0]\r
- */\r
-void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value);\r
-\r
-/** Reads the System Sleep Control PCR Register\r
- * @return value - byte 0 of the system sleep control PCR register\r
- */\r
-uint8_t p_pcr_system_sleep_ctrl_read(void);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Function to program to CLK Divide Value * \r
- * ---------------------------------------------------------------------- */\r
- /** Writes the clock divide value in the Processor Clock Control Register\r
- * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE\r
- */\r
-void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Function to program the Slow Clock Control *\r
- * Register *\r
- * ---------------------------------------------------------------------- */\r
- /** Write the slow clock divide value in the Slow Clock Control Register\r
- * @param slow_clk_divide_value - slow clk divide value\r
- */\r
-void p_pcr_slow_clk_ctrl_write(uint16_t slow_clk_divide_value);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Function to read the Oscillator Lock Status */ \r
-/* ---------------------------------------------------------------------- */\r
-/** Reads the Oscillator Lock status bit in the Oscillator ID Register\r
- * @return 1 if Oscillator Lock Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_oscillator_lock_sts_get(void);\r
-\r
-/** Reads the Oscillator ID Register\r
- * @return oscillator ID value\r
- */\r
-uint16_t p_pcr_oscillator_id_reg_read(void);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions to read various power status in *\r
- * Power Reset register *\r
- * ---------------------------------------------------------------------- */\r
- /** Reads the VCC Reset Status bit \r
- * in the Power Reset Status Register\r
- * @return 1 if VCC Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_pwr_reset_vcc_reset_sts_get(void);\r
-\r
-/** Reads the Host Reset Status bit \r
- * in the Power Reset Status Register\r
- * @return 1 if Host Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_pwr_reset_host_reset_sts_get(void);\r
-\r
-/** Reads the VBAT Reset Status bit \r
- * in the Power Reset Status Register\r
- * @return 1 if VBAT Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_pwr_reset_vbat_reset_sts_get(void);\r
-\r
-/** Clears the VBAT Reset Status bit \r
- * in the Power Reset Status Register \r
- */\r
-void p_pcr_pwr_reset_vbat_reset_sts_clr(void);\r
-\r
-/** Reads the VTR Reset Status bit \r
- * in the Power Reset Status Register\r
- * @return 1 if VCC1 Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_pwr_reset_vtr_reset_sts_get(void);\r
-\r
-/** Clears the VTR Reset Status bit \r
- * in the Power Reset Status Register \r
- */\r
-void p_pcr_chip_subsystem_vtr_reset_sts_clr(void);\r
-\r
-/** Reads the 32K_ACTIVE status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if 32_ACTIVE bit is set, else 0\r
- */\r
-uint8_t p_pcr_pwr_reset_32K_active_sts_get(void);\r
-\r
-/** Reads the PCICLK_ACTIVE status bit \r
- * in the Power Reset Status Register\r
- * @return 1 if CICLK_ACTIVE bit is set, else 0\r
- */\r
-uint8_t p_pcr_pwr_reset_pciclk_active_sts_get(void);\r
-\r
-/** Reads the ESPICLK_ACTIVE status bit \r
- * in the Power Reset Status Register\r
- * @return 1 if ESPICLK_ACTIVE bit is set, else 0\r
- */\r
-uint8_t p_pcr_pwr_reset_espiclk_active_sts_get(void);\r
-\r
-/** Reads the Power status reg\r
- * @return Power Status Reg value\r
- */\r
-uint16_t p_pcr_pwr_reset_sts_get(void);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions for Power Reset Control Register */ \r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Reads the Power Reset Control Register\r
- * @return Power Reset Control Register value\r
- */\r
-uint16_t p_pcr_pwr_reset_ctrl_read(void);\r
-\r
-/** Set the PWR_INV bit in the Power Reset Control Register\r
- * @param set_clr value 1 or 0\r
- * @return none\r
- */\r
-void p_pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr);\r
-\r
-/** Set the HOST RESET SELECT bit in the Power Reset Control Register\r
- * @param set_clr value 1 or 0\r
- * @return none\r
- */\r
-void p_pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions for System Reset Register */ \r
-/* ---------------------------------------------------------------------- */\r
-/** Set the SOFT_SYS_RESET bit in the System Reset Register\r
- * @param none\r
- * @return none\r
- */\r
-void p_pcr_system_reset_set(void);\r
-\r
-\r
-/** Set the value in PKE CLOCK Register\r
- * @param PKE Clock value \r
- * @return none\r
- */\r
-void p_pcr_pke_clock_write(uint8_t pke_clk_val);\r
-\r
-/** Read the value in PKE CLOCK Register\r
- * @none \r
- * @return PKE Clock value \r
- */\r
-uint8_t p_pcr_pke_clock_read(void);\r
-\r
-/** Set the value in Oscillator calibration Register\r
- * @param Oscillator calibration value \r
- * @return none\r
- */\r
-void p_pcr_osc_cal_write(uint8_t osc_cal_val);\r
-\r
-/** Read the value in Osc cal Register\r
- * @none \r
- * @return Osc cal value \r
- */\r
-uint8_t p_pcr_osc_cal_read(void);\r
-\r
-#endif // #ifndef _PCR_H\r
-/* end pcr.h */\r
-/** @}\r
- */\r
-\r
-\r
-\r
projects / freertos / blobdiff