--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2016/09/22 08:03:49 $ \r
+$Author: pramans $\r
+Last Change: Updated for tabs\r
+******************************************************************************/\r
+/** @file pcr_perphl.c\r
+* \brief Power, Clocks, and Resets Peripheral Source file\r
+* \author jvasanth\r
+* \r
+* This file implements the PCR Peripheral functions \r
+******************************************************************************/\r
+\r
+/** @defgroup PCR\r
+ * @{\r
+ */\r
+\r
+#include "common_lib.h"\r
+#include "pcr.h"\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Generic functions to program and read 32-bit values from PCR Registers */\r
+/* ---------------------------------------------------------------------- */\r
+/** Writes 32-bit value in the PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param value - 32-bit value\r
+ */\r
+void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE); \r
+\r
+ pPCR_Reg += pcr_reg_id;\r
+\r
+ *pPCR_Reg = value; \r
+}\r
+\r
+/** Reads 32-bit value from the PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @return value - 32-bit value\r
+ */\r
+uint32_t p_pcr_reg_read(uint8_t pcr_reg_id)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint32_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE); \r
+\r
+ pPCR_Reg += pcr_reg_id; \r
+\r
+ retVal = *pPCR_Reg;\r
+\r
+ return retVal;\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions to set, clr and get bits in PCR Registers */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Sets bits in a PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to set \r
+ */\r
+void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE); \r
+\r
+ pPCR_Reg += pcr_reg_id;\r
+\r
+ *pPCR_Reg |= bit_mask; \r
+}\r
+\r
+/** Clears bits in a PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to clear \r
+ */\r
+void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE); \r
+\r
+ pPCR_Reg += pcr_reg_id;\r
+\r
+ *pPCR_Reg &= ~bit_mask; \r
+}\r
+\r
+/** Read bits in a PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to read \r
+ * @return value - 32-bit value\r
+ */\r
+uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint32_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE); \r
+\r
+ pPCR_Reg += pcr_reg_id; \r
+\r
+ retVal = (*pPCR_Reg) & bit_mask;\r
+\r
+ return retVal;\r
+}\r
+\r
+/** Sets or Clears bits in a PCR Register - Helper Function\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to set or clear\r
+ * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register\r
+ */\r
+void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag)\r
+{\r
+ if (set_clr_flag)\r
+ {\r
+ p_pcr_reg_set(pcr_reg_id, bit_mask);\r
+ }\r
+ else\r
+ {\r
+ p_pcr_reg_clr(pcr_reg_id, bit_mask);\r
+ } \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions to operate on System Sleep Control Register */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+\r
+/** Writes required sleep mode in System Sleep Control Register\r
+ * @param sleep_value - System Sleep control value (Heavy/Light/Sleep All)\r
+ */\r
+void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ \r
+ /* Check for valid value */\r
+ if ((sleep_value == SYSTEM_LIGHT_SLEEP) || \r
+ (sleep_value == SYSTEM_LIGHT_SLEEP) ||\r
+ (sleep_value == SYSTEM_LIGHT_SLEEP))\r
+ { \r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; \r
+\r
+ *pPCR_Reg = (sleep_value & 0x7); \r
+ }\r
+}\r
+\r
+/** Reads the System Sleep Control PCR Register\r
+ * @return value - byte 0 of the system sleep control PCR register\r
+ */\r
+uint8_t p_pcr_system_sleep_ctrl_read(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+ \r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; \r
+\r
+ retVal = (uint8_t)((*pPCR_Reg) & 0xFF);\r
+\r
+ return retVal;\r
+}\r
+\r
+\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Function to program to CLK Divide Value */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Writes the clock divide value in the Processor Clock Control Register\r
+ * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE\r
+ */\r
+void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ /* Check for valid value */\r
+ if (((clk_divide_value >= PCR_CPU_CLK_DIVIDE_1) && \r
+ (clk_divide_value <= PCR_CPU_CLK_DIVIDE_4)) ||\r
+ (clk_divide_value == PCR_CPU_CLK_DIVIDE_16) ||\r
+ (clk_divide_value == PCR_CPU_CLK_DIVIDE_48))\r
+ { \r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL; \r
+\r
+ *pPCR_Reg = (clk_divide_value & 0xFF);\r
+ }\r
+ \r
+}\r
+\r
+/** Writes the clock divide value in the Processor Clock Control Register\r
+ * @param none\r
+ * @ return value - clk divide value, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE\r
+ */\r
+uint8_t p_pcr_processor_clk_ctrl_read(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL; \r
+\r
+ retVal = ((uint8_t)((*pPCR_Reg) & 0xFF));\r
+ \r
+ return retVal;\r
+ \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Function to program the slow clock divide value */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Write the slow clock divide value in the Slow Clock Control Register\r
+ * @param slow_clk_divide_value - slow clk divide value\r
+ */\r
+void p_pcr_slow_clk_ctrl_write(uint16_t slow_clk_divide_value)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SLOW_CLK_CTRL; \r
+\r
+ *pPCR_Reg = (slow_clk_divide_value & 0x3FF); \r
+\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Function to read the Oscillator Lock Status */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Reads the Oscillator Lock status bit in the Oscillator ID Register\r
+ * @return 1 if Oscillator Lock Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_oscillator_lock_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_OSCILLATOR_LOCK_STATUS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal;\r
+ \r
+}\r
+\r
+\r
+/** Reads the Oscillator ID Register\r
+ * @return oscillator ID value\r
+ */\r
+uint16_t p_pcr_oscillator_id_reg_read(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint16_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID; \r
+\r
+ retVal = ((uint16_t)((*pPCR_Reg) & 0x1FFu));\r
+ \r
+ return retVal;\r
+ \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions to read various power status in Power Reset register */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Reads the VCC PWRGD Status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if VCC PWRGD Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_vcc_pwrdg_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_PWR_RESET_STS_VCC_PWRGD_RESET_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Reads the Host Reset Status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if Host Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_host_reset_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_PWR_RESET_STS_HOST_RESET_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Reads the VBAT Reset Status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if VBAT Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_vbat_reset_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_PWR_RESET_STS_VBAT_RESET_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Clears the VBAT Reset Status bit \r
+ * in the Power Reset Status Register \r
+ */\r
+void p_pcr_pwr_reset_vbat_reset_sts_clr(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;\r
+\r
+ // Write to clear\r
+ *pPCR_Reg |= PCR_PWR_RESET_STS_VBAT_RESET_STS_BITMASK;\r
+ \r
+}\r
+\r
+/** Reads the VTR Reset Status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if VTR Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_vtr_reset_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_PWR_RESET_STS_VTR_RESET_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Clears the VTR Reset Status bit \r
+ * in the Power Reset Status Register \r
+ */\r
+void p_pcr_pwr_reset_vtr_reset_sts_clr(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;\r
+\r
+ // Write to clear\r
+ *pPCR_Reg |= PCR_PWR_RESET_STS_VTR_RESET_STS_BITMASK;\r
+ \r
+}\r
+\r
+/** Reads the JTAG Reset Status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if JTAG Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_jtag_reset_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_PWR_RESET_STS_JTAG_RESET_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Clears the JTAG Reset Status bit \r
+ * in the Power Reset Status Register \r
+ */\r
+void p_pcr_pwr_reset_jtag_reset_sts_clr(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;\r
+\r
+ // Write to clear\r
+ *pPCR_Reg |= PCR_PWR_RESET_STS_JTAG_RESET_STS_BITMASK;\r
+ \r
+}\r
+\r
+/** Reads the 32K_ACTIVE status bit \r
+ * in the Chip Subsystem Power Reset Status Register\r
+ * @return 1 if 32_ACTIVE bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_32K_active_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_PWR_RESET_STS_32K_ACTIVE_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Reads the PCICLK_ACTIVE status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if PCICLK_ACTIVE bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_pciclk_active_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_PWR_RESET_STS_PCICLK_ACTIVE_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ } \r
+ return retVal; \r
+}\r
+\r
+/** Reads the ESPI status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if ESPICLK_ACTIVE bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_espiclk_active_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_PWR_RESET_STS_ESPICLK_ACTIVE_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ } \r
+ return retVal; \r
+}\r
+\r
+/** Reads the Power status reg\r
+ * @return Power Status Reg value\r
+ */\r
+uint16_t p_pcr_pwr_reset_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint16_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = (uint16_t)((*pPCR_Reg) & 0xFFF);\r
+ \r
+ return (retVal); \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for Power Reset Control Register */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Reads the Power Reset Control Register\r
+ * @return Power Reset Control Register value\r
+ */\r
+uint16_t p_pcr_pwr_reset_ctrl_read(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint16_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL; \r
+\r
+ retVal = (uint16_t)((*pPCR_Reg) & 0x1FFUL); \r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Set the PWR_INV bit in the Power Reset Control Register\r
+ * @param set_clr value 1 or 0\r
+ * @return none\r
+ */\r
+void p_pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL; \r
+\r
+ if (set_clr)\r
+ {\r
+ *pPCR_Reg |= (PCR_PWR_RESET_CTRL_PWR_INV_BITMASK);\r
+ }\r
+ else\r
+ {\r
+ *pPCR_Reg &= ~(PCR_PWR_RESET_CTRL_PWR_INV_BITMASK);\r
+ }\r
+}\r
+\r
+/** Set the HOST RESET SELECT bit in the Power Reset Control Register\r
+ * @param set_clr value 1 or 0\r
+ * @return none\r
+ */\r
+void p_pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL; \r
+\r
+ if (set_clr)\r
+ {\r
+ *pPCR_Reg |= (PCR_PWR_RESET_CTRL_HOST_RST_SELECT_BITMASK); \r
+ }\r
+ else\r
+ {\r
+ *pPCR_Reg &= ~(PCR_PWR_RESET_CTRL_HOST_RST_SELECT_BITMASK); \r
+ }\r
+}\r
+\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for System Reset Register */\r
+/* ---------------------------------------------------------------------- */\r
+/** Set the SOFT_SYS_RESET bit in the System Reset Register\r
+ * @param none\r
+ * @return none\r
+ */\r
+void p_pcr_system_reset_set()\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_RESET; \r
+\r
+ *pPCR_Reg |= (1<<8); \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for PKE Clock Register */\r
+/* ---------------------------------------------------------------------- */\r
+/** Set the value in PKE CLOCK Register\r
+ * @param PKE Clock value \r
+ * @return none\r
+ */\r
+void p_pcr_pke_clock_write(uint8_t pke_clk_val)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST0; \r
+\r
+ *pPCR_Reg = pke_clk_val;\r
+}\r
+\r
+/** Read the value in PKE CLOCK Register\r
+ * @none \r
+ * @return PKE Clock value \r
+ */\r
+uint8_t p_pcr_pke_clock_read(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST0; \r
+\r
+ return ((uint8_t)(*pPCR_Reg & 0xFF));\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for Oscillator calibration Register */\r
+/* ---------------------------------------------------------------------- */\r
+/** Set the value in Oscillator calibration Register\r
+ * @param Oscillator calibration value \r
+ * @return none\r
+ */\r
+void p_pcr_osc_cal_write(uint8_t osc_cal_val)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST1; \r
+\r
+ *pPCR_Reg = osc_cal_val;\r
+}\r
+\r
+/** Read the value in Osc cal Register\r
+ * @none \r
+ * @return Osc cal value \r
+ */\r
+uint8_t p_pcr_osc_cal_read(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST1; \r
+\r
+ return ((uint8_t)(*pPCR_Reg & 0xFF));\r
+}\r
+\r
+/* end pcr_perphl.c */\r
+/** @}\r
+ */\r
projects / freertos / blobdiff