--- /dev/null
+/*\r
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_common.h"\r
+#define SDK_MEM_MAGIC_NUMBER 12345U\r
+\r
+typedef struct _mem_align_control_block\r
+{\r
+ uint16_t identifier; /*!< Identifier for the memory control block. */\r
+ uint16_t offset; /*!< offset from aligned address to real address */\r
+} mem_align_cb_t;\r
+\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.common"\r
+#endif\r
+\r
+#ifndef __GIC_PRIO_BITS\r
+#if defined(ENABLE_RAM_VECTOR_TABLE)\r
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)\r
+{\r
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */\r
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)\r
+ extern uint32_t Image$$VECTOR_ROM$$Base[];\r
+ extern uint32_t Image$$VECTOR_RAM$$Base[];\r
+ extern uint32_t Image$$RW_m_data$$Base[];\r
+\r
+#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base\r
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base\r
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))\r
+#elif defined(__ICCARM__)\r
+ extern uint32_t __RAM_VECTOR_TABLE_SIZE[];\r
+ extern uint32_t __VECTOR_TABLE[];\r
+ extern uint32_t __VECTOR_RAM[];\r
+#elif defined(__GNUC__)\r
+ extern uint32_t __VECTOR_TABLE[];\r
+ extern uint32_t __VECTOR_RAM[];\r
+ extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];\r
+ uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);\r
+#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */\r
+ uint32_t n;\r
+ uint32_t ret;\r
+ uint32_t irqMaskValue;\r
+\r
+ irqMaskValue = DisableGlobalIRQ();\r
+ if (SCB->VTOR != (uint32_t)__VECTOR_RAM)\r
+ {\r
+ /* Copy the vector table from ROM to RAM */\r
+ for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)\r
+ {\r
+ __VECTOR_RAM[n] = __VECTOR_TABLE[n];\r
+ }\r
+ /* Point the VTOR to the position of vector table */\r
+ SCB->VTOR = (uint32_t)__VECTOR_RAM;\r
+ }\r
+\r
+ ret = __VECTOR_RAM[irq + 16];\r
+ /* make sure the __VECTOR_RAM is noncachable */\r
+ __VECTOR_RAM[irq + 16] = irqHandler;\r
+\r
+ EnableGlobalIRQ(irqMaskValue);\r
+\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+\r
+ return ret;\r
+}\r
+#endif /* ENABLE_RAM_VECTOR_TABLE. */\r
+#endif /* __GIC_PRIO_BITS. */\r
+\r
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))\r
+#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)\r
+\r
+void EnableDeepSleepIRQ(IRQn_Type interrupt)\r
+{\r
+ uint32_t intNumber = (uint32_t)interrupt;\r
+\r
+ uint32_t index = 0;\r
+\r
+ while (intNumber >= 32u)\r
+ {\r
+ index++;\r
+ intNumber -= 32u;\r
+ }\r
+\r
+ SYSCON->STARTERSET[index] = 1u << intNumber;\r
+ EnableIRQ(interrupt); /* also enable interrupt at NVIC */\r
+}\r
+\r
+void DisableDeepSleepIRQ(IRQn_Type interrupt)\r
+{\r
+ uint32_t intNumber = (uint32_t)interrupt;\r
+\r
+ DisableIRQ(interrupt); /* also disable interrupt at NVIC */\r
+ uint32_t index = 0;\r
+\r
+ while (intNumber >= 32u)\r
+ {\r
+ index++;\r
+ intNumber -= 32u;\r
+ }\r
+\r
+ SYSCON->STARTERCLR[index] = 1u << intNumber;\r
+}\r
+#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */\r
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */\r
+\r
+void *SDK_Malloc(size_t size, size_t alignbytes)\r
+{\r
+ mem_align_cb_t *p_cb = NULL;\r
+ uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);\r
+ union\r
+ {\r
+ void *pointer_value;\r
+ uint32_t unsigned_value;\r
+ } p_align_addr, p_addr;\r
+\r
+ p_addr.pointer_value = malloc(alignedsize);\r
+\r
+ if (p_addr.pointer_value == NULL)\r
+ {\r
+ return NULL;\r
+ }\r
+\r
+ p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);\r
+\r
+ p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);\r
+ p_cb->identifier = SDK_MEM_MAGIC_NUMBER;\r
+ p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);\r
+\r
+ return p_align_addr.pointer_value;\r
+}\r
+\r
+void SDK_Free(void *ptr)\r
+{\r
+ union\r
+ {\r
+ void *pointer_value;\r
+ uint32_t unsigned_value;\r
+ } p_free;\r
+ p_free.pointer_value = ptr;\r
+ mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);\r
+\r
+ if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)\r
+ {\r
+ return;\r
+ }\r
+\r
+ p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;\r
+\r
+ free(p_free.pointer_value);\r
+}\r
+\r
+/*!\r
+ * @brief Delay function bases on while loop, every loop includes three instructions.\r
+ *\r
+ * @param count Counts of loop needed for dalay.\r
+ */\r
+#ifndef __XCC__\r
+#if defined(__CC_ARM) /* This macro is arm v5 specific */\r
+/* clang-format off */\r
+__ASM static void DelayLoop(uint32_t count)\r
+{\r
+loop\r
+ SUBS R0, R0, #1\r
+ CMP R0, #0\r
+ BNE loop\r
+ BX LR\r
+}\r
+/* clang-format on */\r
+#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)\r
+/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,\r
+ * use SUB and CMP here for compatibility */\r
+static void DelayLoop(uint32_t count)\r
+{\r
+ __ASM volatile(" MOV R0, %0" : : "r"(count));\r
+ __ASM volatile(\r
+ "loop: \n"\r
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)\r
+ " SUB R0, R0, #1 \n"\r
+#else\r
+ " SUBS R0, R0, #1 \n"\r
+#endif\r
+ " CMP R0, #0 \n"\r
+\r
+ " BNE loop \n");\r
+}\r
+#endif /* defined(__CC_ARM) */\r
+\r
+/*!\r
+ * @brief Delay at least for some time.\r
+ * Please note that, this API uses while loop for delay, different run-time environments make the time not precise,\r
+ * if precise delay count was needed, please implement a new delay function with hardware timer.\r
+ *\r
+ * @param delay_us Delay time in unit of microsecond.\r
+ * @param coreClock_Hz Core clock frequency with Hz.\r
+ */\r
+void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz)\r
+{\r
+ assert(0U != delay_us);\r
+ uint64_t count = USEC_TO_COUNT(delay_us, coreClock_Hz);\r
+ assert(count <= UINT32_MAX);\r
+\r
+ /* Divide value may be different in various environment to ensure delay is precise.\r
+ * Every loop count includes three instructions, due to Cortex-M7 sometimes executes\r
+ * two instructions in one period, through test here set divide 2. Other M cores use\r
+ * divide 4. By the way, divide 2 or 4 could let odd count lost precision, but it does\r
+ * not matter because other instructions outside while loop is enough to fill the time.\r
+ */\r
+#if (__CORTEX_M == 7)\r
+ count = count / 2U;\r
+#else\r
+ count = count / 4U;\r
+#endif\r
+ DelayLoop((uint32_t)count);\r
+}\r
+#endif\r
projects / freertos / blobdiff