--- /dev/null
+/*\r
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _FSL_COMMON_H_\r
+#define _FSL_COMMON_H_\r
+\r
+#include <assert.h>\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include <string.h>\r
+#include <stdlib.h>\r
+\r
+#if defined(__ICCARM__)\r
+#include <stddef.h>\r
+#endif\r
+\r
+/*\r
+ * For CMSIS pack RTE.\r
+ * CMSIS pack RTE generates "RTC_Components.h" which contains the statements\r
+ * of the related <RTE_Components_h> element for all selected software components.\r
+ */\r
+#ifdef _RTE_\r
+#include "RTE_Components.h"\r
+#endif\r
+\r
+#include "fsl_device_registers.h"\r
+\r
+/*!\r
+ * @addtogroup ksdk_common\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @brief Construct a status code value from a group and code number. */\r
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))\r
+\r
+/*! @brief Construct the version number for drivers. */\r
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief common driver version 2.2.2. */\r
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))\r
+/*@}*/\r
+\r
+/* Debug console type definition. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */\r
+\r
+/*! @brief Status group numbers. */\r
+enum _status_groups\r
+{\r
+ kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */\r
+ kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */\r
+ kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */\r
+ kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */\r
+ kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */\r
+ kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */\r
+ kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */\r
+ kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */\r
+ kStatusGroup_UART = 10, /*!< Group number for UART status codes. */\r
+ kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */\r
+ kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */\r
+ kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */\r
+ kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/\r
+ kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/\r
+ kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/\r
+ kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */\r
+ kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */\r
+ kStatusGroup_SAI = 19, /*!< Group number for SAI status code */\r
+ kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */\r
+ kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */\r
+ kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */\r
+ kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */\r
+ kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */\r
+ kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */\r
+ kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */\r
+ kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */\r
+ kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */\r
+ kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */\r
+ kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */\r
+ kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */\r
+ kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */\r
+ kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */\r
+ kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */\r
+ kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */\r
+ kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */\r
+ kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */\r
+ kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */\r
+ kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */\r
+ kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */\r
+ kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */\r
+ kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */\r
+ kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */\r
+ kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */\r
+ kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */\r
+ kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */\r
+ kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */\r
+ kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/\r
+ kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */\r
+ kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */\r
+ kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */\r
+ kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */\r
+ kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */\r
+ kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/\r
+ kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/\r
+ kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/\r
+ kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/\r
+ kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */\r
+ kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */\r
+ kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */\r
+ kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */\r
+ kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */\r
+ kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */\r
+ kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */\r
+ kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */\r
+ kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */\r
+ kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */\r
+ kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */\r
+ kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */\r
+ kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */\r
+ kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */\r
+ kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */\r
+ kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */\r
+ kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */\r
+\r
+ kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */\r
+ kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */\r
+ kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */\r
+ kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */\r
+ kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */\r
+ kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */\r
+ kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */\r
+ kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */\r
+ kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */\r
+ kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */\r
+ kStatusGroup_LED = 137, /*!< Group number for LED status codes. */\r
+ kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */\r
+ kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */\r
+ kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */\r
+ kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */\r
+ kStatusGroup_LIST = 142, /*!< Group number for List status codes. */\r
+ kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */\r
+ kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */\r
+ kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */\r
+ kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */\r
+ kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/\r
+ kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */\r
+ kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */\r
+ kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */\r
+};\r
+\r
+/*! @brief Generic status return codes. */\r
+enum\r
+{\r
+ kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),\r
+ kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),\r
+ kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),\r
+ kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),\r
+ kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),\r
+ kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),\r
+ kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),\r
+};\r
+\r
+/*! @brief Type used for all status and error return values. */\r
+typedef int32_t status_t;\r
+\r
+/*\r
+ * Macro guard for whether to use default weak IRQ implementation in drivers\r
+ */\r
+#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ\r
+#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1\r
+#endif\r
+\r
+/*! @name Min/max macros */\r
+/* @{ */\r
+#if !defined(MIN)\r
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))\r
+#endif\r
+\r
+#if !defined(MAX)\r
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))\r
+#endif\r
+/* @} */\r
+\r
+/*! @brief Computes the number of elements in an array. */\r
+#if !defined(ARRAY_SIZE)\r
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))\r
+#endif\r
+\r
+/*! @name UINT16_MAX/UINT32_MAX value */\r
+/* @{ */\r
+#if !defined(UINT16_MAX)\r
+#define UINT16_MAX ((uint16_t)-1)\r
+#endif\r
+\r
+#if !defined(UINT32_MAX)\r
+#define UINT32_MAX ((uint32_t)-1)\r
+#endif\r
+/* @} */\r
+\r
+/*! @name Timer utilities */\r
+/* @{ */\r
+/*! Macro to convert a microsecond period to raw count value */\r
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)\r
+/*! Macro to convert a raw count value to microsecond */\r
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)\r
+\r
+/*! Macro to convert a millisecond period to raw count value */\r
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)\r
+/*! Macro to convert a raw count value to millisecond */\r
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)\r
+/* @} */\r
+\r
+/*! @name Alignment variable definition macros */\r
+/* @{ */\r
+#if (defined(__ICCARM__))\r
+/**\r
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.\r
+ * http:/ /supp.iar.com/Support/?note=24725\r
+ */\r
+_Pragma("diag_suppress=Pm120")\r
+#define SDK_PRAGMA(x) _Pragma(#x)\r
+ _Pragma("diag_error=Pm120")\r
+/*! Macro to define a variable with alignbytes alignment */\r
+#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var\r
+/*! Macro to define a variable with L1 d-cache line size alignment */\r
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)\r
+#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var\r
+#endif\r
+/*! Macro to define a variable with L2 cache line size alignment */\r
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)\r
+#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var\r
+#endif\r
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)\r
+/*! Macro to define a variable with alignbytes alignment */\r
+#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var\r
+/*! Macro to define a variable with L1 d-cache line size alignment */\r
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)\r
+#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var\r
+#endif\r
+/*! Macro to define a variable with L2 cache line size alignment */\r
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)\r
+#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var\r
+#endif\r
+#elif defined(__GNUC__)\r
+/*! Macro to define a variable with alignbytes alignment */\r
+#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))\r
+/*! Macro to define a variable with L1 d-cache line size alignment */\r
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)\r
+#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))\r
+#endif\r
+/*! Macro to define a variable with L2 cache line size alignment */\r
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)\r
+#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))\r
+#endif\r
+#else\r
+#error Toolchain not supported\r
+#define SDK_ALIGN(var, alignbytes) var\r
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)\r
+#define SDK_L1DCACHE_ALIGN(var) var\r
+#endif\r
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)\r
+#define SDK_L2CACHE_ALIGN(var) var\r
+#endif\r
+#endif\r
+\r
+/*! Macro to change a value to a given size aligned value */\r
+#define SDK_SIZEALIGN(var, alignbytes) \\r
+ ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))\r
+/* @} */\r
+\r
+/*! @name Non-cacheable region definition macros */\r
+/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or\r
+ * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,\r
+ * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables\r
+ * will be initialized to zero in system startup.\r
+ */\r
+/* @{ */\r
+#if (defined(__ICCARM__))\r
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))\r
+#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"\r
+#else\r
+#define AT_NONCACHEABLE_SECTION(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var\r
+#endif\r
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))\r
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \\r
+ __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var\r
+#if(defined(__CC_ARM))\r
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \\r
+ __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var\r
+#else\r
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \\r
+ __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var\r
+#endif\r
+#else\r
+#define AT_NONCACHEABLE_SECTION(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var\r
+#endif\r
+#elif(defined(__XCC__))\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \\r
+ __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))\r
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \\r
+ __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes)))\r
+#elif(defined(__GNUC__))\r
+/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"\r
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.\r
+ */\r
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \\r
+ __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))\r
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \\r
+ __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))\r
+#else\r
+#define AT_NONCACHEABLE_SECTION(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))\r
+#endif\r
+#else\r
+#error Toolchain not supported.\r
+#define AT_NONCACHEABLE_SECTION(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var\r
+#endif\r
+/* @} */\r
+\r
+/*! @name Time sensitive region */\r
+/* @{ */\r
+#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE\r
+#if (defined(__ICCARM__))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"\r
+#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"\r
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func\r
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func\r
+#elif(defined(__GNUC__))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func\r
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func\r
+#else\r
+#error Toolchain not supported.\r
+#endif /* defined(__ICCARM__) */\r
+#else\r
+#if (defined(__ICCARM__))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) func\r
+#define AT_QUICKACCESS_SECTION_DATA(func) func\r
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) func\r
+#define AT_QUICKACCESS_SECTION_DATA(func) func\r
+#elif(defined(__GNUC__))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) func\r
+#define AT_QUICKACCESS_SECTION_DATA(func) func\r
+#else\r
+#error Toolchain not supported.\r
+#endif\r
+#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */\r
+/* @} */\r
+\r
+/*! @name Ram Function */\r
+#if (defined(__ICCARM__))\r
+#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"\r
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))\r
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func\r
+#elif(defined(__GNUC__))\r
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func\r
+#else\r
+#error Toolchain not supported.\r
+#endif /* defined(__ICCARM__) */\r
+/* @} */\r
+\r
+/*! @name Suppress fallthrough warning macro */\r
+/* For switch case code block, if case section ends without "break;" statement, there wil be\r
+ fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.\r
+ To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each\r
+ case section which misses "break;"statement.\r
+ */\r
+/* @{ */\r
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)\r
+#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__ ((fallthrough))\r
+#else\r
+#define SUPPRESS_FALL_THROUGH_WARNING()\r
+#endif\r
+/* @} */\r
+\r
+#if defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
+void DefaultISR(void);\r
+#endif\r
+/*\r
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t\r
+ * defined in previous of this file.\r
+ */\r
+#include "fsl_clock.h"\r
+\r
+/*\r
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral\r
+ */\r
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \\r
+ (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))\r
+#include "fsl_reset.h"\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+ extern "C"\r
+{\r
+#endif\r
+\r
+ /*!\r
+ * @brief Enable specific interrupt.\r
+ *\r
+ * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt\r
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected\r
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.\r
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed\r
+ * to NVIC first then routed to core.\r
+ *\r
+ * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts\r
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.\r
+ *\r
+ * @param interrupt The IRQ number.\r
+ * @retval kStatus_Success Interrupt enabled successfully\r
+ * @retval kStatus_Fail Failed to enable the interrupt\r
+ */\r
+ static inline status_t EnableIRQ(IRQn_Type interrupt)\r
+ {\r
+ if (NotAvail_IRQn == interrupt)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+\r
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)\r
+ if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+#endif\r
+\r
+#if defined(__GIC_PRIO_BITS)\r
+ GIC_EnableIRQ(interrupt);\r
+#else\r
+ NVIC_EnableIRQ(interrupt);\r
+#endif\r
+ return kStatus_Success;\r
+ }\r
+\r
+ /*!\r
+ * @brief Disable specific interrupt.\r
+ *\r
+ * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt\r
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected\r
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.\r
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed\r
+ * to NVIC first then routed to core.\r
+ *\r
+ * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts\r
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.\r
+ *\r
+ * @param interrupt The IRQ number.\r
+ * @retval kStatus_Success Interrupt disabled successfully\r
+ * @retval kStatus_Fail Failed to disable the interrupt\r
+ */\r
+ static inline status_t DisableIRQ(IRQn_Type interrupt)\r
+ {\r
+ if (NotAvail_IRQn == interrupt)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+\r
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)\r
+ if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+#endif\r
+\r
+#if defined(__GIC_PRIO_BITS)\r
+ GIC_DisableIRQ(interrupt);\r
+#else\r
+ NVIC_DisableIRQ(interrupt);\r
+#endif\r
+ return kStatus_Success;\r
+ }\r
+\r
+ /*!\r
+ * @brief Disable the global IRQ\r
+ *\r
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask\r
+ * register for the EnableGlobalIRQ().\r
+ *\r
+ * @return Current primask value.\r
+ */\r
+ static inline uint32_t DisableGlobalIRQ(void)\r
+ {\r
+#if defined (__XCC__)\r
+ return 0;\r
+#else\r
+#if defined(CPSR_I_Msk)\r
+ uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;\r
+\r
+ __disable_irq();\r
+\r
+ return cpsr;\r
+#else\r
+ uint32_t regPrimask = __get_PRIMASK();\r
+\r
+ __disable_irq();\r
+\r
+ return regPrimask;\r
+#endif\r
+#endif\r
+ }\r
+\r
+ /*!\r
+ * @brief Enable the global IRQ\r
+ *\r
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the\r
+ * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to\r
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.\r
+ *\r
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the\r
+ * DisableGlobalIRQ().\r
+ */\r
+ static inline void EnableGlobalIRQ(uint32_t primask)\r
+ {\r
+#if defined (__XCC__)\r
+#else\r
+#if defined(CPSR_I_Msk)\r
+ __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);\r
+#else\r
+ __set_PRIMASK(primask);\r
+#endif\r
+#endif\r
+ }\r
+\r
+#if defined(ENABLE_RAM_VECTOR_TABLE)\r
+ /*!\r
+ * @brief install IRQ handler\r
+ *\r
+ * @param irq IRQ number\r
+ * @param irqHandler IRQ handler address\r
+ * @return The old IRQ handler address\r
+ */\r
+ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);\r
+#endif /* ENABLE_RAM_VECTOR_TABLE. */\r
+\r
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))\r
+ /*!\r
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.\r
+ *\r
+ * Enable the interrupt for wake-up from deep sleep mode.\r
+ * Some interrupts are typically used in sleep mode only and will not occur during\r
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable\r
+ * those clocks (significantly increasing power consumption in the reduced power mode),\r
+ * making these wake-ups possible.\r
+ *\r
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).\r
+ *\r
+ * @param interrupt The IRQ number.\r
+ */\r
+ void EnableDeepSleepIRQ(IRQn_Type interrupt);\r
+\r
+ /*!\r
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.\r
+ *\r
+ * Disable the interrupt for wake-up from deep sleep mode.\r
+ * Some interrupts are typically used in sleep mode only and will not occur during\r
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable\r
+ * those clocks (significantly increasing power consumption in the reduced power mode),\r
+ * making these wake-ups possible.\r
+ *\r
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).\r
+ *\r
+ * @param interrupt The IRQ number.\r
+ */\r
+ void DisableDeepSleepIRQ(IRQn_Type interrupt);\r
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */\r
+\r
+ /*!\r
+ * @brief Allocate memory with given alignment and aligned size.\r
+ *\r
+ * This is provided to support the dynamically allocated memory\r
+ * used in cache-able region.\r
+ * @param size The length required to malloc.\r
+ * @param alignbytes The alignment size.\r
+ * @retval The allocated memory.\r
+ */\r
+ void *SDK_Malloc(size_t size, size_t alignbytes);\r
+\r
+ /*!\r
+ * @brief Free memory.\r
+ *\r
+ * @param ptr The memory to be release.\r
+ */\r
+ void SDK_Free(void *ptr);\r
+\r
+ /*!\r
+ * @brief Delay at least for some time.\r
+ * Please note that, this API uses while loop for delay, different run-time environments make the time not precise,\r
+ * if precise delay count was needed, please implement a new delay function with hardware timer.\r
+ *\r
+ * @param delay_us Delay time in unit of microsecond.\r
+ * @param coreClock_Hz Core clock frequency with Hz.\r
+ */\r
+ void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+/*! @} */\r
+\r
+#endif /* _FSL_COMMON_H_ */\r
projects / freertos / blobdiff