--- /dev/null
+/*\r
+ * Copyright 2017-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+/***********************************************************************************************************************\r
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file\r
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.\r
+ **********************************************************************************************************************/\r
+/*\r
+ * How to set up clock using clock driver functions:\r
+ *\r
+ * 1. Setup clock sources.\r
+ *\r
+ * 2. Set up wait states of the flash.\r
+ *\r
+ * 3. Set up all dividers.\r
+ *\r
+ * 4. Set up all selectors to provide selected clocks.\r
+ */\r
+\r
+/* clang-format off */\r
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+!!GlobalInfo\r
+product: Clocks v5.0\r
+processor: LPC55S69\r
+package_id: LPC55S69JBD100\r
+mcu_data: ksdk2_0\r
+processor_version: 0.0.6\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/\r
+/* clang-format on */\r
+\r
+#include "fsl_power.h"\r
+#include "fsl_clock.h"\r
+#include "clock_config.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+/* System clock frequency. */\r
+extern uint32_t SystemCoreClock;\r
+\r
+/*******************************************************************************\r
+ ************************ BOARD_InitBootClocks function ************************\r
+ ******************************************************************************/\r
+void BOARD_InitBootClocks(void)\r
+{\r
+ BOARD_BootClockFROHF96M();\r
+}\r
+\r
+/*******************************************************************************\r
+ ******************** Configuration BOARD_BootClockFRO12M **********************\r
+ ******************************************************************************/\r
+/* clang-format off */\r
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+!!Configuration\r
+name: BOARD_BootClockFRO12M\r
+outputs:\r
+- {id: System_clock.outFreq, value: 12 MHz}\r
+settings:\r
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}\r
+sources:\r
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/\r
+/* clang-format on */\r
+\r
+/*******************************************************************************\r
+ * Variables for BOARD_BootClockFRO12M configuration\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Code for BOARD_BootClockFRO12M configuration\r
+ ******************************************************************************/\r
+void BOARD_BootClockFRO12M(void)\r
+{\r
+#ifndef SDK_SECONDARY_CORE\r
+ /*!< Set up the clock sources */\r
+ /*!< Configure FRO192M */\r
+ POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */\r
+ CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */\r
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */\r
+\r
+ CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */\r
+\r
+ POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */\r
+ CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */\r
+\r
+ /*!< Set up dividers */\r
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */\r
+\r
+ /*!< Set up clock selectors - Attach clocks to the peripheries */\r
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */\r
+\r
+ /*< Set SystemCoreClock variable. */\r
+ SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;\r
+#endif\r
+}\r
+\r
+/*******************************************************************************\r
+ ******************* Configuration BOARD_BootClockFROHF96M *********************\r
+ ******************************************************************************/\r
+/* clang-format off */\r
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+!!Configuration\r
+name: BOARD_BootClockFROHF96M\r
+called_from_default_init: true\r
+outputs:\r
+- {id: System_clock.outFreq, value: 96 MHz}\r
+settings:\r
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}\r
+- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}\r
+sources:\r
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/\r
+/* clang-format on */\r
+\r
+/*******************************************************************************\r
+ * Variables for BOARD_BootClockFROHF96M configuration\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Code for BOARD_BootClockFROHF96M configuration\r
+ ******************************************************************************/\r
+void BOARD_BootClockFROHF96M(void)\r
+{\r
+#ifndef SDK_SECONDARY_CORE\r
+ /*!< Set up the clock sources */\r
+ /*!< Configure FRO192M */\r
+ POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */\r
+ CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */\r
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */\r
+\r
+ CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */\r
+\r
+ POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */\r
+ CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */\r
+\r
+ /*!< Set up dividers */\r
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */\r
+\r
+ /*!< Set up clock selectors - Attach clocks to the peripheries */\r
+ CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */\r
+\r
+ /*< Set SystemCoreClock variable. */\r
+ SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;\r
+#endif\r
+}\r
+\r
+/*******************************************************************************\r
+ ******************** Configuration BOARD_BootClockPLL100M *********************\r
+ ******************************************************************************/\r
+/* clang-format off */\r
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+!!Configuration\r
+name: BOARD_BootClockPLL100M\r
+outputs:\r
+- {id: System_clock.outFreq, value: 100 MHz}\r
+settings:\r
+- {id: PLL0_Mode, value: Normal}\r
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}\r
+- {id: ENABLE_CLKIN_ENA, value: Enabled}\r
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}\r
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}\r
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}\r
+- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}\r
+- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}\r
+- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}\r
+sources:\r
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}\r
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/\r
+/* clang-format on */\r
+\r
+/*******************************************************************************\r
+ * Variables for BOARD_BootClockPLL100M configuration\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Code for BOARD_BootClockPLL100M configuration\r
+ ******************************************************************************/\r
+void BOARD_BootClockPLL100M(void)\r
+{\r
+#ifndef SDK_SECONDARY_CORE\r
+ /*!< Set up the clock sources */\r
+ /*!< Configure FRO192M */\r
+ POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */\r
+ CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */\r
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */\r
+\r
+ CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */\r
+\r
+ POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */\r
+ POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */\r
+ CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */\r
+ SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */\r
+ ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */\r
+\r
+ POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */\r
+ CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */\r
+\r
+ /*!< Set up PLL */\r
+ CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */\r
+ POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */\r
+ POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); \r
+ const pll_setup_t pll0Setup = {\r
+ .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(54U) | SYSCON_PLL0CTRL_SELP(26U),\r
+ .pllndec = SYSCON_PLL0NDEC_NDIV(4U),\r
+ .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),\r
+ .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},\r
+ .pllRate = 100000000U,\r
+ .flags = PLL_SETUPFLAG_WAITLOCK\r
+ };\r
+ CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */\r
+\r
+ /*!< Set up dividers */\r
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */\r
+\r
+ /*!< Set up clock selectors - Attach clocks to the peripheries */\r
+ CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */\r
+\r
+ /*< Set SystemCoreClock variable. */\r
+ SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;\r
+#endif\r
+}\r
+\r
projects / freertos / blobdiff