--- /dev/null
+/*\r
+** ###################################################################\r
+** Version: rev. 1.0, 2018-08-22\r
+** Build: b190122\r
+**\r
+** Abstract:\r
+** Chip specific module features.\r
+**\r
+** Copyright 2016 Freescale Semiconductor, Inc.\r
+** Copyright 2016-2019 NXP\r
+** All rights reserved.\r
+**\r
+** SPDX-License-Identifier: BSD-3-Clause\r
+**\r
+** http: www.nxp.com\r
+** mail: support@nxp.com\r
+**\r
+** Revisions:\r
+** - rev. 1.0 (2018-08-22)\r
+** Initial version based on v0.2UM\r
+**\r
+** ###################################################################\r
+*/\r
+\r
+#ifndef _LPC55S69_cm33_core0_FEATURES_H_\r
+#define _LPC55S69_cm33_core0_FEATURES_H_\r
+\r
+/* SOC module features */\r
+\r
+/* @brief CASPER availability on the SoC. */\r
+#define FSL_FEATURE_SOC_CASPER_COUNT (1)\r
+/* @brief CRC availability on the SoC. */\r
+#define FSL_FEATURE_SOC_CRC_COUNT (1)\r
+/* @brief CTIMER availability on the SoC. */\r
+#define FSL_FEATURE_SOC_CTIMER_COUNT (5)\r
+/* @brief DMA availability on the SoC. */\r
+#define FSL_FEATURE_SOC_DMA_COUNT (2)\r
+/* @brief FLASH availability on the SoC. */\r
+#define FSL_FEATURE_SOC_FLASH_COUNT (1)\r
+/* @brief FLEXCOMM availability on the SoC. */\r
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9)\r
+/* @brief GINT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_GINT_COUNT (2)\r
+/* @brief GPIO availability on the SoC. */\r
+#define FSL_FEATURE_SOC_GPIO_COUNT (1)\r
+/* @brief SECGPIO availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SECGPIO_COUNT (1)\r
+/* @brief HASHCRYPT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1)\r
+/* @brief I2C availability on the SoC. */\r
+#define FSL_FEATURE_SOC_I2C_COUNT (8)\r
+/* @brief I2S availability on the SoC. */\r
+#define FSL_FEATURE_SOC_I2S_COUNT (8)\r
+/* @brief INPUTMUX availability on the SoC. */\r
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)\r
+/* @brief IOCON availability on the SoC. */\r
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)\r
+/* @brief LPADC availability on the SoC. */\r
+#define FSL_FEATURE_SOC_LPADC_COUNT (1)\r
+/* @brief MAILBOX availability on the SoC. */\r
+#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)\r
+/* @brief MRT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_MRT_COUNT (1)\r
+/* @brief OSTIMER availability on the SoC. */\r
+#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)\r
+/* @brief PINT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_PINT_COUNT (1)\r
+/* @brief SECPINT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SECPINT_COUNT (1)\r
+/* @brief PMC availability on the SoC. */\r
+#define FSL_FEATURE_SOC_PMC_COUNT (1)\r
+/* @brief POWERQUAD availability on the SoC. */\r
+#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)\r
+/* @brief PUF availability on the SoC. */\r
+#define FSL_FEATURE_SOC_PUF_COUNT (1)\r
+/* @brief RNG1 availability on the SoC. */\r
+#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)\r
+/* @brief RTC availability on the SoC. */\r
+#define FSL_FEATURE_SOC_RTC_COUNT (1)\r
+/* @brief SCT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SCT_COUNT (1)\r
+/* @brief SDIF availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SDIF_COUNT (1)\r
+/* @brief SPI availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SPI_COUNT (9)\r
+/* @brief SYSCON availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)\r
+/* @brief SYSCTL1 availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1)\r
+/* @brief USART availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USART_COUNT (8)\r
+/* @brief USB availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USB_COUNT (1)\r
+/* @brief USBFSH availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USBFSH_COUNT (1)\r
+/* @brief USBHSD availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USBHSD_COUNT (1)\r
+/* @brief USBHSH availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USBHSH_COUNT (1)\r
+/* @brief USBPHY availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USBPHY_COUNT (1)\r
+/* @brief UTICK availability on the SoC. */\r
+#define FSL_FEATURE_SOC_UTICK_COUNT (1)\r
+/* @brief WWDT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)\r
+\r
+/* LPADC module features */\r
+\r
+/* @brief FIFO availability on the SoC. */\r
+#define FSL_FEATURE_LPADC_FIFO_COUNT (2)\r
+/* @brief Has differential mode (bitfield CMDLn[DIFF]). */\r
+#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)\r
+/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */\r
+#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)\r
+/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */\r
+#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)\r
+/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */\r
+#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)\r
+/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */\r
+#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)\r
+/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */\r
+#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)\r
+/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */\r
+#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)\r
+/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */\r
+#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)\r
+/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */\r
+#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)\r
+/* @brief Has internal clock (bitfield CFG[ADCKEN]). */\r
+#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)\r
+/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */\r
+#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)\r
+/* @brief Has calibration (bitfield CFG[CALOFS]). */\r
+#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)\r
+/* @brief Has offset trim (register OFSTRIM). */\r
+#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)\r
+\r
+/* CASPER module features */\r
+\r
+/* @brief Base address of the CASPER dedicated RAM */\r
+#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)\r
+/* @brief Interleaving of the CASPER dedicated RAM */\r
+#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)\r
+\r
+/* DMA module features */\r
+\r
+/* @brief Number of channels */\r
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)\r
+\r
+/* HASHCRYPT module features */\r
+\r
+/* @brief the address of alias offset */\r
+#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000)\r
+\r
+/* I2S module features */\r
+\r
+/* @brief I2S support dual channel transfer. */\r
+#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)\r
+\r
+/* IOCON module features */\r
+\r
+/* @brief Func bit field width */\r
+#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)\r
+\r
+/* MAILBOX module features */\r
+\r
+/* @brief Mailbox side for current core */\r
+#define FSL_FEATURE_MAILBOX_SIDE_A (1)\r
+\r
+/* MRT module features */\r
+\r
+/* @brief number of channels. */\r
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)\r
+\r
+/* PINT module features */\r
+\r
+/* @brief Number of connected outputs */\r
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (10)\r
+\r
+/* POWERLIB module features */\r
+\r
+/* @brief Niobe4's Powerlib API is different with other LPC series devices. */\r
+#define FSL_FEATURE_POWERLIB_NIOBE4_EXTEND (1)\r
+\r
+/* POWERQUAD module features */\r
+\r
+/* @brief Sine and Cossine fix errata */\r
+#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1)\r
+\r
+/* PUF module features */\r
+\r
+/* @brief Number of PUF key slots available on device. */\r
+#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4)\r
+/* @brief the shift status value */\r
+#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)\r
+\r
+/* SCT module features */\r
+\r
+/* @brief Number of events */\r
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)\r
+/* @brief Number of states */\r
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32)\r
+/* @brief Number of match capture */\r
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)\r
+/* @brief Number of outputs */\r
+#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)\r
+\r
+/* SDIF module features */\r
+\r
+/* @brief FIFO depth, every location is a WORD */\r
+#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)\r
+/* @brief Max DMA buffer size */\r
+#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)\r
+/* @brief Max source clock in HZ */\r
+#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)\r
+/* @brief support 2 cards */\r
+#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)\r
+\r
+/* SECPINT module features */\r
+\r
+/* @brief Number of connected outputs */\r
+#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2)\r
+\r
+/* SYSCON module features */\r
+\r
+/* @brief Pointer to ROM IAP entry functions */\r
+#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)\r
+/* @brief Flash page size in bytes */\r
+#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)\r
+/* @brief Flash sector size in bytes */\r
+#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)\r
+/* @brief Flash size in bytes */\r
+#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592)\r
+/* @brief Has Power Down mode */\r
+#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)\r
+/* @brief CCM_ANALOG availability on the SoC. */\r
+#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)\r
+\r
+/* USB module features */\r
+\r
+/* @brief Size of the USB dedicated RAM */\r
+#define FSL_FEATURE_USB_USB_RAM (0x00004000)\r
+/* @brief Base address of the USB dedicated RAM */\r
+#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)\r
+/* @brief USB version */\r
+#define FSL_FEATURE_USB_VERSION (200)\r
+/* @brief Number of the endpoint in USB FS */\r
+#define FSL_FEATURE_USB_EP_NUM (5)\r
+\r
+/* USBFSH module features */\r
+\r
+/* @brief Size of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000)\r
+/* @brief Base address of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)\r
+/* @brief USBFSH version */\r
+#define FSL_FEATURE_USBFSH_VERSION (200)\r
+\r
+/* USBHSD module features */\r
+\r
+/* @brief Size of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000)\r
+/* @brief Base address of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)\r
+/* @brief USBHSD version */\r
+#define FSL_FEATURE_USBHSD_VERSION (300)\r
+/* @brief Number of the endpoint in USB HS */\r
+#define FSL_FEATURE_USBHSD_EP_NUM (6)\r
+\r
+/* USBHSH module features */\r
+\r
+/* @brief Size of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000)\r
+/* @brief Base address of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)\r
+/* @brief USBHSH version */\r
+#define FSL_FEATURE_USBHSH_VERSION (300)\r
+\r
+/* UTICK module features */\r
+\r
+/* @brief UTICK does not support PD configure. */\r
+#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)\r
+\r
+/* WWDT module features */\r
+\r
+/* @brief WWDT does not support oscillator lock. */\r
+#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)\r
+/* @brief WWDT does not support power down configure */\r
+#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)\r
+\r
+#endif /* _LPC55S69_cm33_core0_FEATURES_H_ */\r
+\r
projects / freertos / blobdiff