--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32l4xx.c\r
+ * @author MCD Application Team\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File\r
+ *\r
+ * This file provides two functions and one global variable to be called from\r
+ * user application:\r
+ * - SystemInit(): This function is called at startup just after reset and\r
+ * before branch to main program. This call is made inside\r
+ * the "startup_stm32l4xx.s" file.\r
+ *\r
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
+ * by the user application to setup the SysTick\r
+ * timer or configure other parameters.\r
+ *\r
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
+ * be called whenever the core clock is changed\r
+ * during program execution.\r
+ *\r
+ * After each device reset the MSI (4 MHz) is used as system clock source.\r
+ * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to\r
+ * configure the system clock before to branch to main program.\r
+ *\r
+ * This file configures the system clock as follows:\r
+ *=============================================================================\r
+ *-----------------------------------------------------------------------------\r
+ * System Clock source | MSI\r
+ *-----------------------------------------------------------------------------\r
+ * SYSCLK(Hz) | 4000000\r
+ *-----------------------------------------------------------------------------\r
+ * HCLK(Hz) | 4000000\r
+ *-----------------------------------------------------------------------------\r
+ * AHB Prescaler | 1\r
+ *-----------------------------------------------------------------------------\r
+ * APB1 Prescaler | 1\r
+ *-----------------------------------------------------------------------------\r
+ * APB2 Prescaler | 1\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_M | 1\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_N | 8\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_P | 7\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_Q | 2\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_R | 2\r
+ *-----------------------------------------------------------------------------\r
+ * PLLSAI1_P | NA\r
+ *-----------------------------------------------------------------------------\r
+ * PLLSAI1_Q | NA\r
+ *-----------------------------------------------------------------------------\r
+ * PLLSAI1_R | NA\r
+ *-----------------------------------------------------------------------------\r
+ * PLLSAI2_P | NA\r
+ *-----------------------------------------------------------------------------\r
+ * PLLSAI2_Q | NA\r
+ *-----------------------------------------------------------------------------\r
+ * PLLSAI2_R | NA\r
+ *-----------------------------------------------------------------------------\r
+ * Require 48MHz for USB OTG FS, | Disabled\r
+ * SDIO and RNG clock |\r
+ *-----------------------------------------------------------------------------\r
+ *=============================================================================\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32l4xx_system\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM32L4xx_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32l4xx.h"\r
+\r
+#if !defined (HSE_VALUE)\r
+ #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */\r
+#endif /* HSE_VALUE */\r
+\r
+#if !defined (MSI_VALUE)\r
+ #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* MSI_VALUE */\r
+\r
+#if !defined (HSI_VALUE)\r
+ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L4xx_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L4xx_System_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/************************* Miscellaneous Configuration ************************/\r
+/*!< Uncomment the following line if you need to relocate your vector Table in\r
+ Internal SRAM. */\r
+/* #define VECT_TAB_SRAM */\r
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.\r
+ This value must be a multiple of 0x200. */\r
+/******************************************************************************/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L4xx_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L4xx_System_Private_Variables\r
+ * @{\r
+ */\r
+ /* The SystemCoreClock variable is updated in three ways:\r
+ 1) by calling CMSIS function SystemCoreClockUpdate()\r
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()\r
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\r
+ Note: If you use this function to configure the system clock; then there\r
+ is no need to call the 2 first functions listed above, since SystemCoreClock\r
+ variable is updated automatically.\r
+ */\r
+ uint32_t SystemCoreClock = 4000000U;\r
+\r
+ const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};\r
+ const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};\r
+ const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \\r
+ 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L4xx_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+\r
+void SystemInit(void)\r
+{\r
+ /* FPU settings ------------------------------------------------------------*/\r
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */\r
+ #endif\r
+\r
+ /* Reset the RCC clock configuration to the default reset state ------------*/\r
+ /* Set MSION bit */\r
+ RCC->CR |= RCC_CR_MSION;\r
+\r
+ /* Reset CFGR register */\r
+ RCC->CFGR = 0x00000000U;\r
+\r
+ /* Reset HSEON, CSSON , HSION, and PLLON bits */\r
+ RCC->CR &= 0xEAF6FFFFU;\r
+\r
+ /* Reset PLLCFGR register */\r
+ RCC->PLLCFGR = 0x00001000U;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= 0xFFFBFFFFU;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIER = 0x00000000U;\r
+\r
+ /* Configure the Vector Table location add offset address ------------------*/\r
+#ifdef VECT_TAB_SRAM\r
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r
+#else\r
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock variable according to Clock Register Values.\r
+ * The SystemCoreClock variable contains the core clock (HCLK), it can\r
+ * be used by the user application to setup the SysTick timer or configure\r
+ * other parameters.\r
+ *\r
+ * @note Each time the core clock (HCLK) changes, this function must be called\r
+ * to update SystemCoreClock variable value. Otherwise, any configuration\r
+ * based on this variable will be incorrect.\r
+ *\r
+ * @note - The system frequency computed by this function is not the real\r
+ * frequency in the chip. It is calculated based on the predefined\r
+ * constant and the selected clock source:\r
+ *\r
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)\r
+ *\r
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)\r
+ *\r
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)\r
+ *\r
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)\r
+ * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ *\r
+ * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value\r
+ * 4 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature.\r
+ *\r
+ * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature.\r
+ *\r
+ * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value\r
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ *\r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ *\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U;\r
+\r
+ /* Get MSI Range frequency--------------------------------------------------*/\r
+ if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)\r
+ { /* MSISRANGE from RCC_CSR applies */\r
+ msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;\r
+ }\r
+ else\r
+ { /* MSIRANGE from RCC_CR applies */\r
+ msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;\r
+ }\r
+ /*MSI frequency range in HZ*/\r
+ msirange = MSIRangeTable[msirange];\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ switch (RCC->CFGR & RCC_CFGR_SWS)\r
+ {\r
+ case 0x00: /* MSI used as system clock source */\r
+ SystemCoreClock = msirange;\r
+ break;\r
+\r
+ case 0x04: /* HSI used as system clock source */\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+\r
+ case 0x08: /* HSE used as system clock source */\r
+ SystemCoreClock = HSE_VALUE;\r
+ break;\r
+\r
+ case 0x0C: /* PLL used as system clock source */\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN\r
+ SYSCLK = PLL_VCO / PLLR\r
+ */\r
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);\r
+ pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;\r
+\r
+ switch (pllsource)\r
+ {\r
+ case 0x02: /* HSI used as PLL clock source */\r
+ pllvco = (HSI_VALUE / pllm);\r
+ break;\r
+\r
+ case 0x03: /* HSE used as PLL clock source */\r
+ pllvco = (HSE_VALUE / pllm);\r
+ break;\r
+\r
+ default: /* MSI used as PLL clock source */\r
+ pllvco = (msirange / pllm);\r
+ break;\r
+ }\r
+ pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);\r
+ pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;\r
+ SystemCoreClock = pllvco/pllr;\r
+ break;\r
+\r
+ default:\r
+ SystemCoreClock = msirange;\r
+ break;\r
+ }\r
+ /* Compute HCLK clock frequency --------------------------------------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];\r
+ /* HCLK clock frequency */\r
+ SystemCoreClock >>= tmp;\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / blobdiff