--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l4xx_hal_qspi.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of QSPI HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_QSPI_H\r
+#define STM32L4xx_HAL_QSPI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+#if defined(QUADSPI)\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup QSPI\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup QSPI_Exported_Types QSPI Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief QSPI Init structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.\r
+ This parameter can be a number between 0 and 255 */\r
+ uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)\r
+ This parameter can be a value between 1 and 16 */\r
+ uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to\r
+ take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)\r
+ This parameter can be a value of @ref QSPI_SampleShifting */\r
+ uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits\r
+ required to address the flash memory. The flash capacity can be up to 4GB\r
+ (addressed using 32 bits) in indirect mode, but the addressable space in\r
+ memory-mapped mode is limited to 256MB\r
+ This parameter can be a number between 0 and 31 */\r
+ uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number\r
+ of clock cycles which the chip select must remain high between commands.\r
+ This parameter can be a value of @ref QSPI_ChipSelectHighTime */\r
+ uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.\r
+ This parameter can be a value of @ref QSPI_ClockMode */\r
+#if defined(QUADSPI_CR_DFM)\r
+ uint32_t FlashID; /* Specifies the Flash which will be used,\r
+ This parameter can be a value of @ref QSPI_Flash_Select */\r
+ uint32_t DualFlash; /* Specifies the Dual Flash Mode State\r
+ This parameter can be a value of @ref QSPI_DualFlash_Mode */\r
+#endif\r
+}QSPI_InitTypeDef;\r
+\r
+/**\r
+ * @brief HAL QSPI State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */\r
+ HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */\r
+ HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */\r
+ HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */\r
+ HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */\r
+ HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */\r
+ HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */\r
+ HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */\r
+ HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */\r
+}HAL_QSPI_StateTypeDef;\r
+\r
+/**\r
+ * @brief QSPI Handle Structure definition\r
+ */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+typedef struct __QSPI_HandleTypeDef\r
+#else\r
+typedef struct\r
+#endif\r
+{\r
+ QUADSPI_TypeDef *Instance; /* QSPI registers base address */\r
+ QSPI_InitTypeDef Init; /* QSPI communication parameters */\r
+ uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */\r
+ __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */\r
+ __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */\r
+ uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */\r
+ __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */\r
+ __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */\r
+ DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */\r
+ __IO HAL_LockTypeDef Lock; /* Locking object */\r
+ __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */\r
+ __IO uint32_t ErrorCode; /* QSPI Error code */\r
+ uint32_t Timeout; /* Timeout for the QSPI memory access */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+ void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi);\r
+ void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);\r
+ void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);\r
+ void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);\r
+ void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);\r
+ void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);\r
+ void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);\r
+ void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);\r
+ void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi);\r
+ void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi);\r
+\r
+ void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi);\r
+ void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi);\r
+#endif\r
+}QSPI_HandleTypeDef;\r
+\r
+/**\r
+ * @brief QSPI Command structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Instruction; /* Specifies the Instruction to be sent\r
+ This parameter can be a value (8-bit) between 0x00 and 0xFF */\r
+ uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)\r
+ This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */\r
+ uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)\r
+ This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */\r
+ uint32_t AddressSize; /* Specifies the Address Size\r
+ This parameter can be a value of @ref QSPI_AddressSize */\r
+ uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size\r
+ This parameter can be a value of @ref QSPI_AlternateBytesSize */\r
+ uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.\r
+ This parameter can be a number between 0 and 31 */\r
+ uint32_t InstructionMode; /* Specifies the Instruction Mode\r
+ This parameter can be a value of @ref QSPI_InstructionMode */\r
+ uint32_t AddressMode; /* Specifies the Address Mode\r
+ This parameter can be a value of @ref QSPI_AddressMode */\r
+ uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode\r
+ This parameter can be a value of @ref QSPI_AlternateBytesMode */\r
+ uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)\r
+ This parameter can be a value of @ref QSPI_DataMode */\r
+ uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)\r
+ This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length\r
+ until end of memory)*/\r
+ uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase\r
+ This parameter can be a value of @ref QSPI_DdrMode */\r
+ uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data\r
+ output by one half of system clock in DDR mode.\r
+ Not available on all devices.\r
+ This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */\r
+ uint32_t SIOOMode; /* Specifies the send instruction only once mode\r
+ This parameter can be a value of @ref QSPI_SIOOMode */\r
+}QSPI_CommandTypeDef;\r
+\r
+/**\r
+ * @brief QSPI Auto Polling mode configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.\r
+ This parameter can be any value between 0 and 0xFFFFFFFF */\r
+ uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.\r
+ This parameter can be any value between 0 and 0xFFFFFFFF */\r
+ uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.\r
+ This parameter can be any value between 0 and 0xFFFF */\r
+ uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.\r
+ This parameter can be any value between 1 and 4 */\r
+ uint32_t MatchMode; /* Specifies the method used for determining a match.\r
+ This parameter can be a value of @ref QSPI_MatchMode */\r
+ uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.\r
+ This parameter can be a value of @ref QSPI_AutomaticStop */\r
+}QSPI_AutoPollingTypeDef;\r
+\r
+/**\r
+ * @brief QSPI Memory Mapped mode configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.\r
+ This parameter can be any value between 0 and 0xFFFF */\r
+ uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.\r
+ This parameter can be a value of @ref QSPI_TimeOutActivation */\r
+}QSPI_MemoryMappedTypeDef;\r
+\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief HAL QSPI Callback ID enumeration definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */\r
+ HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */\r
+ HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */\r
+ HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */\r
+ HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */\r
+ HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */\r
+ HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */\r
+ HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */\r
+ HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */\r
+ HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */\r
+\r
+ HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */\r
+ HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */\r
+}HAL_QSPI_CallbackIDTypeDef;\r
+\r
+/**\r
+ * @brief HAL QSPI Callback pointer definition\r
+ */\r
+typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup QSPI_Exported_Constants QSPI Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup QSPI_ErrorCode QSPI Error Code\r
+ * @{\r
+ */\r
+#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */\r
+#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */\r
+#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */\r
+#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */\r
+#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_SampleShifting QSPI Sample Shifting\r
+ * @{\r
+ */\r
+#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/\r
+#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time\r
+ * @{\r
+ */\r
+#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/\r
+#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_ClockMode QSPI Clock Mode\r
+ * @{\r
+ */\r
+#define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/\r
+#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(QUADSPI_CR_DFM)\r
+/** @defgroup QSPI_Flash_Select QSPI Flash Select\r
+ * @{\r
+ */\r
+#define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/\r
+#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode\r
+ * @{\r
+ */\r
+#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/\r
+#define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif\r
+/** @defgroup QSPI_AddressSize QSPI Address Size\r
+ * @{\r
+ */\r
+#define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/\r
+#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/\r
+#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/\r
+#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size\r
+ * @{\r
+ */\r
+#define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/\r
+#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/\r
+#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/\r
+#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_InstructionMode QSPI Instruction Mode\r
+* @{\r
+*/\r
+#define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/\r
+#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/\r
+#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/\r
+#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_AddressMode QSPI Address Mode\r
+* @{\r
+*/\r
+#define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/\r
+#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/\r
+#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/\r
+#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode\r
+* @{\r
+*/\r
+#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/\r
+#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/\r
+#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/\r
+#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_DataMode QSPI Data Mode\r
+ * @{\r
+ */\r
+#define QSPI_DATA_NONE 0x00000000U /*!<No data*/\r
+#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/\r
+#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/\r
+#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_DdrMode QSPI DDR Mode\r
+ * @{\r
+ */\r
+#define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/\r
+#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay\r
+ * @{\r
+ */\r
+#define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/\r
+#if defined(QUADSPI_CCR_DHHC)\r
+#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode\r
+ * @{\r
+ */\r
+#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/\r
+#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_MatchMode QSPI Match Mode\r
+ * @{\r
+ */\r
+#define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/\r
+#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop\r
+ * @{\r
+ */\r
+#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/\r
+#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation\r
+ * @{\r
+ */\r
+#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/\r
+#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_Flags QSPI Flags\r
+ * @{\r
+ */\r
+#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/\r
+#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/\r
+#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/\r
+#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/\r
+#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/\r
+#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_Interrupts QSPI Interrupts\r
+ * @{\r
+ */\r
+#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/\r
+#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/\r
+#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/\r
+#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/\r
+#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_Timeout_definition QSPI Timeout definition\r
+ * @brief QSPI Timeout definition\r
+ * @{\r
+ */\r
+#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup QSPI_Exported_Macros QSPI Exported Macros\r
+ * @{\r
+ */\r
+/** @brief Reset QSPI handle state.\r
+ * @param __HANDLE__ : QSPI handle.\r
+ * @retval None\r
+ */\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \\r
+ (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \\r
+ (__HANDLE__)->MspInitCallback = NULL; \\r
+ (__HANDLE__)->MspDeInitCallback = NULL; \\r
+ } while(0)\r
+#else\r
+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)\r
+#endif\r
+\r
+/** @brief Enable the QSPI peripheral.\r
+ * @param __HANDLE__ : specifies the QSPI Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)\r
+\r
+/** @brief Disable the QSPI peripheral.\r
+ * @param __HANDLE__ : specifies the QSPI Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)\r
+\r
+/** @brief Enable the specified QSPI interrupt.\r
+ * @param __HANDLE__ : specifies the QSPI Handle.\r
+ * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg QSPI_IT_TO: QSPI Timeout interrupt\r
+ * @arg QSPI_IT_SM: QSPI Status match interrupt\r
+ * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r
+ * @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r
+ * @arg QSPI_IT_TE: QSPI Transfer error interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\r
+\r
+\r
+/** @brief Disable the specified QSPI interrupt.\r
+ * @param __HANDLE__ : specifies the QSPI Handle.\r
+ * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg QSPI_IT_TO: QSPI Timeout interrupt\r
+ * @arg QSPI_IT_SM: QSPI Status match interrupt\r
+ * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r
+ * @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r
+ * @arg QSPI_IT_TE: QSPI Transfer error interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\r
+\r
+/** @brief Check whether the specified QSPI interrupt source is enabled or not.\r
+ * @param __HANDLE__ : specifies the QSPI Handle.\r
+ * @param __INTERRUPT__ : specifies the QSPI interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg QSPI_IT_TO: QSPI Timeout interrupt\r
+ * @arg QSPI_IT_SM: QSPI Status match interrupt\r
+ * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r
+ * @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r
+ * @arg QSPI_IT_TE: QSPI Transfer error interrupt\r
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Check whether the selected QSPI flag is set or not.\r
+ * @param __HANDLE__ : specifies the QSPI Handle.\r
+ * @param __FLAG__ : specifies the QSPI flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg QSPI_FLAG_BUSY: QSPI Busy flag\r
+ * @arg QSPI_FLAG_TO: QSPI Timeout flag\r
+ * @arg QSPI_FLAG_SM: QSPI Status match flag\r
+ * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag\r
+ * @arg QSPI_FLAG_TC: QSPI Transfer complete flag\r
+ * @arg QSPI_FLAG_TE: QSPI Transfer error flag\r
+ * @retval None\r
+ */\r
+#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)\r
+\r
+/** @brief Clears the specified QSPI's flag status.\r
+ * @param __HANDLE__ : specifies the QSPI Handle.\r
+ * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set\r
+ * This parameter can be one of the following values:\r
+ * @arg QSPI_FLAG_TO: QSPI Timeout flag\r
+ * @arg QSPI_FLAG_SM: QSPI Status match flag\r
+ * @arg QSPI_FLAG_TC: QSPI Transfer complete flag\r
+ * @arg QSPI_FLAG_TE: QSPI Transfer error flag\r
+ * @retval None\r
+ */\r
+#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup QSPI_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup QSPI_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization/de-initialization functions ********************************/\r
+HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);\r
+HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup QSPI_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* IO operation functions *****************************************************/\r
+/* QSPI IRQ handler method */\r
+void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);\r
+\r
+/* QSPI indirect mode */\r
+HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);\r
+HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r
+HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r
+HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r
+HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r
+\r
+/* QSPI status flag polling mode */\r
+HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);\r
+\r
+/* QSPI memory-mapped mode */\r
+HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);\r
+\r
+/* Callback functions in non-blocking modes ***********************************/\r
+void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);\r
+\r
+/* QSPI indirect mode */\r
+void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);\r
+\r
+/* QSPI status flag polling mode */\r
+void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);\r
+\r
+/* QSPI memory-mapped mode */\r
+void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);\r
+\r
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)\r
+/* QSPI callback registering/unregistering */\r
+HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup QSPI_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral Control and State functions ************************************/\r
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);\r
+uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);\r
+HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);\r
+HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);\r
+uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);\r
+#if defined(QUADSPI_CR_DFM)\r
+HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported functions -------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup QSPI_Private_Macros QSPI Private Macros\r
+ * @{\r
+ */\r
+#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)\r
+\r
+#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 16U))\r
+\r
+#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \\r
+ ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))\r
+\r
+#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))\r
+\r
+#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \\r
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \\r
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \\r
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \\r
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \\r
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \\r
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \\r
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))\r
+\r
+#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \\r
+ ((CLKMODE) == QSPI_CLOCK_MODE_3))\r
+\r
+#if defined(QUADSPI_CR_DFM)\r
+#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \\r
+ ((FLASH_ID) == QSPI_FLASH_ID_2))\r
+\r
+#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \\r
+ ((MODE) == QSPI_DUALFLASH_DISABLE))\r
+\r
+#endif\r
+#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)\r
+\r
+#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \\r
+ ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \\r
+ ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \\r
+ ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))\r
+\r
+#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \\r
+ ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \\r
+ ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \\r
+ ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))\r
+\r
+#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)\r
+\r
+#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \\r
+ ((MODE) == QSPI_INSTRUCTION_1_LINE) || \\r
+ ((MODE) == QSPI_INSTRUCTION_2_LINES) || \\r
+ ((MODE) == QSPI_INSTRUCTION_4_LINES))\r
+\r
+#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \\r
+ ((MODE) == QSPI_ADDRESS_1_LINE) || \\r
+ ((MODE) == QSPI_ADDRESS_2_LINES) || \\r
+ ((MODE) == QSPI_ADDRESS_4_LINES))\r
+\r
+#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \\r
+ ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \\r
+ ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \\r
+ ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))\r
+\r
+#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \\r
+ ((MODE) == QSPI_DATA_1_LINE) || \\r
+ ((MODE) == QSPI_DATA_2_LINES) || \\r
+ ((MODE) == QSPI_DATA_4_LINES))\r
+\r
+#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \\r
+ ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))\r
+\r
+#if defined(QUADSPI_CCR_DHHC)\r
+#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \\r
+ ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))\r
+\r
+#else\r
+#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))\r
+\r
+#endif\r
+#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \\r
+ ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))\r
+\r
+#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)\r
+\r
+#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))\r
+\r
+#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \\r
+ ((MODE) == QSPI_MATCH_MODE_OR))\r
+\r
+#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \\r
+ ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))\r
+\r
+#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \\r
+ ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))\r
+\r
+#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)\r
+/**\r
+* @}\r
+*/\r
+/* End of private macros -----------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_QSPI_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
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