--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l4xx_hal_dma.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of DMA HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_DMA_H\r
+#define STM32L4xx_HAL_DMA_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup DMA_Exported_Types DMA Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief DMA Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Request; /*!< Specifies the request selected for the specified channel.\r
+ This parameter can be a value of @ref DMA_request */\r
+\r
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,\r
+ from memory to memory or from peripheral to memory.\r
+ This parameter can be a value of @ref DMA_Data_transfer_direction */\r
+\r
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.\r
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */\r
+\r
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.\r
+ This parameter can be a value of @ref DMA_Memory_incremented_mode */\r
+\r
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.\r
+ This parameter can be a value of @ref DMA_Peripheral_data_size */\r
+\r
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.\r
+ This parameter can be a value of @ref DMA_Memory_data_size */\r
+\r
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.\r
+ This parameter can be a value of @ref DMA_mode\r
+ @note The circular buffer mode cannot be used if the memory-to-memory\r
+ data transfer is configured on the selected Channel */\r
+\r
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.\r
+ This parameter can be a value of @ref DMA_Priority_level */\r
+} DMA_InitTypeDef;\r
+\r
+/**\r
+ * @brief HAL DMA State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */\r
+ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */\r
+ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */\r
+ HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */\r
+}HAL_DMA_StateTypeDef;\r
+\r
+/**\r
+ * @brief HAL DMA Error Code structure definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */\r
+ HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */\r
+}HAL_DMA_LevelCompleteTypeDef;\r
+\r
+\r
+/**\r
+ * @brief HAL DMA Callback ID structure definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */\r
+ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */\r
+ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */\r
+ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */\r
+ HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */\r
+}HAL_DMA_CallbackIDTypeDef;\r
+\r
+/**\r
+ * @brief DMA handle Structure definition\r
+ */\r
+typedef struct __DMA_HandleTypeDef\r
+{\r
+ DMA_Channel_TypeDef *Instance; /*!< Register base address */\r
+\r
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< DMA locking object */\r
+\r
+ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */\r
+\r
+ void *Parent; /*!< Parent object state */\r
+\r
+ void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */\r
+\r
+ void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */\r
+\r
+ void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */\r
+\r
+ void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */\r
+\r
+ __IO uint32_t ErrorCode; /*!< DMA Error code */\r
+\r
+ DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */\r
+\r
+ uint32_t ChannelIndex; /*!< DMA Channel Index */\r
+\r
+#if defined(DMAMUX1)\r
+ DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */\r
+\r
+ DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */\r
+\r
+ uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */\r
+\r
+ DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */\r
+\r
+ DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */\r
+\r
+ uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */\r
+\r
+#endif /* DMAMUX1 */\r
+\r
+}DMA_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Constants DMA Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Error_Code DMA Error Code\r
+ * @{\r
+ */\r
+#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */\r
+#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */\r
+#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */\r
+#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */\r
+#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */\r
+#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */\r
+#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_request DMA request\r
+ * @{\r
+ */\r
+#if !defined (DMAMUX1)\r
+\r
+#define DMA_REQUEST_0 0U\r
+#define DMA_REQUEST_1 1U\r
+#define DMA_REQUEST_2 2U\r
+#define DMA_REQUEST_3 3U\r
+#define DMA_REQUEST_4 4U\r
+#define DMA_REQUEST_5 5U\r
+#define DMA_REQUEST_6 6U\r
+#define DMA_REQUEST_7 7U\r
+\r
+#endif\r
+\r
+#if defined(DMAMUX1)\r
+\r
+#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */\r
+\r
+#define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */\r
+#define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */\r
+#define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */\r
+#define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */\r
+\r
+#define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */\r
+\r
+#define DMA_REQUEST_DAC1_CH1 6U /*!< DMAMUX1 DAC1 CH1 request */\r
+#define DMA_REQUEST_DAC1_CH2 7U /*!< DMAMUX1 DAC1 CH2 request */\r
+\r
+#define DMA_REQUEST_TIM6_UP 8U /*!< DMAMUX1 TIM6 UP request */\r
+#define DMA_REQUEST_TIM7_UP 9U /*!< DMAMUX1 TIM7 UP request */\r
+\r
+#define DMA_REQUEST_SPI1_RX 10U /*!< DMAMUX1 SPI1 RX request */\r
+#define DMA_REQUEST_SPI1_TX 11U /*!< DMAMUX1 SPI1 TX request */\r
+#define DMA_REQUEST_SPI2_RX 12U /*!< DMAMUX1 SPI2 RX request */\r
+#define DMA_REQUEST_SPI2_TX 13U /*!< DMAMUX1 SPI2 TX request */\r
+#define DMA_REQUEST_SPI3_RX 14U /*!< DMAMUX1 SPI3 RX request */\r
+#define DMA_REQUEST_SPI3_TX 15U /*!< DMAMUX1 SPI3 TX request */\r
+\r
+#define DMA_REQUEST_I2C1_RX 16U /*!< DMAMUX1 I2C1 RX request */\r
+#define DMA_REQUEST_I2C1_TX 17U /*!< DMAMUX1 I2C1 TX request */\r
+#define DMA_REQUEST_I2C2_RX 18U /*!< DMAMUX1 I2C2 RX request */\r
+#define DMA_REQUEST_I2C2_TX 19U /*!< DMAMUX1 I2C2 TX request */\r
+#define DMA_REQUEST_I2C3_RX 20U /*!< DMAMUX1 I2C3 RX request */\r
+#define DMA_REQUEST_I2C3_TX 21U /*!< DMAMUX1 I2C3 TX request */\r
+#define DMA_REQUEST_I2C4_RX 22U /*!< DMAMUX1 I2C4 RX request */\r
+#define DMA_REQUEST_I2C4_TX 23U /*!< DMAMUX1 I2C4 TX request */\r
+\r
+#define DMA_REQUEST_USART1_RX 24U /*!< DMAMUX1 USART1 RX request */\r
+#define DMA_REQUEST_USART1_TX 25U /*!< DMAMUX1 USART1 TX request */\r
+#define DMA_REQUEST_USART2_RX 26U /*!< DMAMUX1 USART2 RX request */\r
+#define DMA_REQUEST_USART2_TX 27U /*!< DMAMUX1 USART2 TX request */\r
+#define DMA_REQUEST_USART3_RX 28U /*!< DMAMUX1 USART3 RX request */\r
+#define DMA_REQUEST_USART3_TX 29U /*!< DMAMUX1 USART3 TX request */\r
+\r
+#define DMA_REQUEST_UART4_RX 30U /*!< DMAMUX1 UART4 RX request */\r
+#define DMA_REQUEST_UART4_TX 31U /*!< DMAMUX1 UART4 TX request */\r
+#define DMA_REQUEST_UART5_RX 32U /*!< DMAMUX1 UART5 RX request */\r
+#define DMA_REQUEST_UART5_TX 33U /*!< DMAMUX1 UART5 TX request */\r
+\r
+#define DMA_REQUEST_LPUART1_RX 34U /*!< DMAMUX1 LP_UART1_RX request */\r
+#define DMA_REQUEST_LPUART1_TX 35U /*!< DMAMUX1 LP_UART1_RX request */\r
+\r
+#define DMA_REQUEST_SAI1_A 36U /*!< DMAMUX1 SAI1 A request */\r
+#define DMA_REQUEST_SAI1_B 37U /*!< DMAMUX1 SAI1 B request */\r
+#define DMA_REQUEST_SAI2_A 38U /*!< DMAMUX1 SAI2 A request */\r
+#define DMA_REQUEST_SAI2_B 39U /*!< DMAMUX1 SAI2 B request */\r
+\r
+#define DMA_REQUEST_OCTOSPI1 40U /*!< DMAMUX1 OCTOSPI1 request */\r
+#define DMA_REQUEST_OCTOSPI2 41U /*!< DMAMUX1 OCTOSPI2 request */\r
+\r
+#define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */\r
+#define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */\r
+#define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */\r
+#define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */\r
+#define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */\r
+#define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */\r
+#define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */\r
+\r
+#define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */\r
+#define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */\r
+#define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */\r
+#define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */\r
+#define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */\r
+#define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */\r
+#define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */\r
+\r
+#define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */\r
+#define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */\r
+#define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */\r
+#define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */\r
+#define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */\r
+\r
+#define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */\r
+#define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */\r
+#define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */\r
+#define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */\r
+#define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */\r
+#define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */\r
+\r
+#define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */\r
+#define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */\r
+#define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */\r
+#define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */\r
+#define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */\r
+\r
+#define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */\r
+#define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */\r
+#define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */\r
+#define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */\r
+#define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */\r
+#define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */\r
+\r
+#define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */\r
+#define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */\r
+#define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */\r
+#define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */\r
+\r
+#define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */\r
+#define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */\r
+#define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */\r
+#define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */\r
+\r
+#define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */\r
+#define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */\r
+#define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */\r
+#define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */\r
+\r
+#define DMA_REQUEST_DCMI 90U /*!< DMAMUX1 DCMI request */\r
+\r
+#define DMA_REQUEST_AES_IN 91U /*!< DMAMUX1 AES IN request */\r
+#define DMA_REQUEST_AES_OUT 92U /*!< DMAMUX1 AES OUT request */\r
+\r
+#define DMA_REQUEST_HASH_IN 93U /*!< DMAMUX1 HASH IN request */\r
+\r
+#endif /* DMAMUX1 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction\r
+ * @{\r
+ */\r
+#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */\r
+#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */\r
+#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode\r
+ * @{\r
+ */\r
+#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */\r
+#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode\r
+ * @{\r
+ */\r
+#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */\r
+#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size\r
+ * @{\r
+ */\r
+#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */\r
+#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */\r
+#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Memory_data_size DMA Memory data size\r
+ * @{\r
+ */\r
+#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */\r
+#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */\r
+#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_mode DMA mode\r
+ * @{\r
+ */\r
+#define DMA_NORMAL 0x00000000U /*!< Normal mode */\r
+#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Priority_level DMA Priority level\r
+ * @{\r
+ */\r
+#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */\r
+#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */\r
+#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */\r
+#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions\r
+ * @{\r
+ */\r
+#define DMA_IT_TC DMA_CCR_TCIE\r
+#define DMA_IT_HT DMA_CCR_HTIE\r
+#define DMA_IT_TE DMA_CCR_TEIE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_flag_definitions DMA flag definitions\r
+ * @{\r
+ */\r
+#define DMA_FLAG_GL1 DMA_ISR_GIF1\r
+#define DMA_FLAG_TC1 DMA_ISR_TCIF1\r
+#define DMA_FLAG_HT1 DMA_ISR_HTIF1\r
+#define DMA_FLAG_TE1 DMA_ISR_TEIF1\r
+#define DMA_FLAG_GL2 DMA_ISR_GIF2\r
+#define DMA_FLAG_TC2 DMA_ISR_TCIF2\r
+#define DMA_FLAG_HT2 DMA_ISR_HTIF2\r
+#define DMA_FLAG_TE2 DMA_ISR_TEIF2\r
+#define DMA_FLAG_GL3 DMA_ISR_GIF3\r
+#define DMA_FLAG_TC3 DMA_ISR_TCIF3\r
+#define DMA_FLAG_HT3 DMA_ISR_HTIF3\r
+#define DMA_FLAG_TE3 DMA_ISR_TEIF3\r
+#define DMA_FLAG_GL4 DMA_ISR_GIF4\r
+#define DMA_FLAG_TC4 DMA_ISR_TCIF4\r
+#define DMA_FLAG_HT4 DMA_ISR_HTIF4\r
+#define DMA_FLAG_TE4 DMA_ISR_TEIF4\r
+#define DMA_FLAG_GL5 DMA_ISR_GIF5\r
+#define DMA_FLAG_TC5 DMA_ISR_TCIF5\r
+#define DMA_FLAG_HT5 DMA_ISR_HTIF5\r
+#define DMA_FLAG_TE5 DMA_ISR_TEIF5\r
+#define DMA_FLAG_GL6 DMA_ISR_GIF6\r
+#define DMA_FLAG_TC6 DMA_ISR_TCIF6\r
+#define DMA_FLAG_HT6 DMA_ISR_HTIF6\r
+#define DMA_FLAG_TE6 DMA_ISR_TEIF6\r
+#define DMA_FLAG_GL7 DMA_ISR_GIF7\r
+#define DMA_FLAG_TC7 DMA_ISR_TCIF7\r
+#define DMA_FLAG_HT7 DMA_ISR_HTIF7\r
+#define DMA_FLAG_TE7 DMA_ISR_TEIF7\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup DMA_Exported_Macros DMA Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset DMA handle state.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)\r
+\r
+/**\r
+ * @brief Enable the specified DMA Channel.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)\r
+\r
+/**\r
+ * @brief Disable the specified DMA Channel.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)\r
+\r
+\r
+/* Interrupt & Flag management */\r
+\r
+/**\r
+ * @brief Return the current DMA Channel transfer complete flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified transfer complete flag index.\r
+ */\r
+\r
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\\r
+ DMA_FLAG_TC7)\r
+\r
+/**\r
+ * @brief Return the current DMA Channel half transfer complete flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified half transfer complete flag index.\r
+ */\r
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\\r
+ DMA_FLAG_HT7)\r
+\r
+/**\r
+ * @brief Return the current DMA Channel transfer error flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified transfer error flag index.\r
+ */\r
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\\r
+ DMA_FLAG_TE7)\r
+\r
+/**\r
+ * @brief Return the current DMA Channel Global interrupt flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified transfer error flag index.\r
+ */\r
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\\r
+ DMA_ISR_GIF7)\r
+\r
+/**\r
+ * @brief Get the DMA Channel pending flags.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __FLAG__ Get the specified flag.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_FLAG_TCx: Transfer complete flag\r
+ * @arg DMA_FLAG_HTx: Half transfer complete flag\r
+ * @arg DMA_FLAG_TEx: Transfer error flag\r
+ * @arg DMA_FLAG_GLx: Global interrupt flag\r
+ * Where x can be from 1 to 7 to select the DMA Channel x flag.\r
+ * @retval The state of FLAG (SET or RESET).\r
+ */\r
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \\r
+ (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))\r
+\r
+/**\r
+ * @brief Clear the DMA Channel pending flags.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __FLAG__ specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_FLAG_TCx: Transfer complete flag\r
+ * @arg DMA_FLAG_HTx: Half transfer complete flag\r
+ * @arg DMA_FLAG_TEx: Transfer error flag\r
+ * @arg DMA_FLAG_GLx: Global interrupt flag\r
+ * Where x can be from 1 to 7 to select the DMA Channel x flag.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \\r
+ (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))\r
+\r
+/**\r
+ * @brief Enable the specified DMA Channel interrupts.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the specified DMA Channel interrupts.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Check whether the specified DMA Channel interrupt is enabled or not.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __INTERRUPT__ specifies the DMA interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask\r
+ * @retval The state of DMA_IT (SET or RESET).\r
+ */\r
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Return the number of remaining data units in the current DMA Channel transfer.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The number of remaining data units in the current DMA Channel transfer.\r
+ */\r
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(DMAMUX1)\r
+/* Include DMA HAL Extension module */\r
+#include "stm32l4xx_hal_dma_ex.h"\r
+#endif /* DMAMUX1 */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup DMA_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *****************************/\r
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* IO operation functions *****************************************************/\r
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);\r
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));\r
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral State and Error functions ***************************************/\r
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);\r
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Macros DMA Private Macros\r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \\r
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \\r
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))\r
+\r
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))\r
+\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \\r
+ ((STATE) == DMA_PINC_DISABLE))\r
+\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \\r
+ ((STATE) == DMA_MINC_DISABLE))\r
+\r
+#if !defined (DMAMUX1)\r
+\r
+#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \\r
+ ((REQUEST) == DMA_REQUEST_1) || \\r
+ ((REQUEST) == DMA_REQUEST_2) || \\r
+ ((REQUEST) == DMA_REQUEST_3) || \\r
+ ((REQUEST) == DMA_REQUEST_4) || \\r
+ ((REQUEST) == DMA_REQUEST_5) || \\r
+ ((REQUEST) == DMA_REQUEST_6) || \\r
+ ((REQUEST) == DMA_REQUEST_7))\r
+#endif\r
+\r
+#if defined(DMAMUX1)\r
+\r
+#define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN)\r
+\r
+#endif /* DMAMUX1 */\r
+\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \\r
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \\r
+ ((SIZE) == DMA_PDATAALIGN_WORD))\r
+\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \\r
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \\r
+ ((SIZE) == DMA_MDATAALIGN_WORD ))\r
+\r
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \\r
+ ((MODE) == DMA_CIRCULAR))\r
+\r
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \\r
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \\r
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \\r
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_DMA_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / blobdiff