+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l4xx_hal_rcc.h\r
- * @author MCD Application Team\r
- * @brief Header file of RCC HAL module.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
- * All rights reserved.</center></h2>\r
- *\r
- * This software component is licensed by ST under BSD 3-Clause license,\r
- * the "License"; You may not use this file except in compliance with the\r
- * License. You may obtain a copy of the License at:\r
- * opensource.org/licenses/BSD-3-Clause\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32L4xx_HAL_RCC_H\r
-#define __STM32L4xx_HAL_RCC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_def.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup RCC\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/** @defgroup RCC_Exported_Types RCC Exported Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief RCC PLL configuration structure definition\r
- */\r
-typedef struct\r
-{\r
- uint32_t PLLState; /*!< The new state of the PLL.\r
- This parameter can be a value of @ref RCC_PLL_Config */\r
-\r
- uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.\r
- This parameter must be a value of @ref RCC_PLL_Clock_Source */\r
-\r
- uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.\r
- This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.\r
- This parameter must be a number between Min_Data = 1 and Max_Data = 8 on the other devices */\r
-\r
- uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.\r
- This parameter must be a number between Min_Data = 8 and Max_Data = 86 */\r
-\r
-#if defined(RCC_PLLP_SUPPORT)\r
- uint32_t PLLP; /*!< PLLP: Division factor for SAI clock.\r
- This parameter must be a value of @ref RCC_PLLP_Clock_Divider */\r
-#endif /* RCC_PLLP_SUPPORT */\r
-\r
- uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.\r
- This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */\r
-\r
- uint32_t PLLR; /*!< PLLR: Division for the main system clock.\r
- User have to set the PLLR parameter correctly to not exceed max frequency 120MHZ\r
- on STM32L4Rx/STM32L4Sx devices else 80MHz on the other devices.\r
- This parameter must be a value of @ref RCC_PLLR_Clock_Divider */\r
-\r
-}RCC_PLLInitTypeDef;\r
-\r
-/**\r
- * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition\r
- */\r
-typedef struct\r
-{\r
- uint32_t OscillatorType; /*!< The oscillators to be configured.\r
- This parameter can be a value of @ref RCC_Oscillator_Type */\r
-\r
- uint32_t HSEState; /*!< The new state of the HSE.\r
- This parameter can be a value of @ref RCC_HSE_Config */\r
-\r
- uint32_t LSEState; /*!< The new state of the LSE.\r
- This parameter can be a value of @ref RCC_LSE_Config */\r
-\r
- uint32_t HSIState; /*!< The new state of the HSI.\r
- This parameter can be a value of @ref RCC_HSI_Config */\r
-\r
- uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).\r
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices.\r
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */\r
-\r
- uint32_t LSIState; /*!< The new state of the LSI.\r
- This parameter can be a value of @ref RCC_LSI_Config */\r
-#if defined(RCC_CSR_LSIPREDIV)\r
-\r
- uint32_t LSIDiv; /*!< The division factor of the LSI.\r
- This parameter can be a value of @ref RCC_LSI_Div */\r
-#endif /* RCC_CSR_LSIPREDIV */\r
-\r
- uint32_t MSIState; /*!< The new state of the MSI.\r
- This parameter can be a value of @ref RCC_MSI_Config */\r
-\r
- uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).\r
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */\r
-\r
- uint32_t MSIClockRange; /*!< The MSI frequency range.\r
- This parameter can be a value of @ref RCC_MSI_Clock_Range */\r
-\r
- uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices).\r
- This parameter can be a value of @ref RCC_HSI48_Config */\r
-\r
- RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */\r
-\r
-}RCC_OscInitTypeDef;\r
-\r
-/**\r
- * @brief RCC System, AHB and APB busses clock configuration structure definition\r
- */\r
-typedef struct\r
-{\r
- uint32_t ClockType; /*!< The clock to be configured.\r
- This parameter can be a value of @ref RCC_System_Clock_Type */\r
-\r
- uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).\r
- This parameter can be a value of @ref RCC_System_Clock_Source */\r
-\r
- uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).\r
- This parameter can be a value of @ref RCC_AHB_Clock_Source */\r
-\r
- uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).\r
- This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r
-\r
- uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).\r
- This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r
-\r
-}RCC_ClkInitTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported constants --------------------------------------------------------*/\r
-/** @defgroup RCC_Exported_Constants RCC Exported Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup RCC_Timeout_Value Timeout Values\r
- * @{\r
- */\r
-#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */\r
-#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Oscillator_Type Oscillator Type\r
- * @{\r
- */\r
-#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */\r
-#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */\r
-#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */\r
-#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */\r
-#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */\r
-#define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */\r
-#endif /* RCC_HSI48_SUPPORT */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_HSE_Config HSE Config\r
- * @{\r
- */\r
-#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */\r
-#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */\r
-#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_LSE_Config LSE Config\r
- * @{\r
- */\r
-#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */\r
-#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */\r
-#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */\r
-#if defined(RCC_BDCR_LSESYSDIS)\r
-#define RCC_LSE_ON_RTC_ONLY (RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< LSE clock activation without propagation to system */\r
-#define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< External clock source for LSE clock without propagation to system */\r
-#endif /* RCC_BDCR_LSESYSDIS */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_HSI_Config HSI Config\r
- * @{\r
- */\r
-#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */\r
-#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */\r
-\r
-#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \\r
- defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)\r
-#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */\r
-#else\r
-#define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */\r
-#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */\r
- /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_LSI_Config LSI Config\r
- * @{\r
- */\r
-#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */\r
-#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */\r
-/**\r
- * @}\r
- */\r
-#if defined(RCC_CSR_LSIPREDIV)\r
-\r
-/** @defgroup RCC_LSI_Div LSI Div\r
- * @{\r
- */\r
-#define RCC_LSI_DIV1 0x00000000U /*!< LSI clock not divided */\r
-#define RCC_LSI_DIV128 RCC_CSR_LSIPREDIV /*!< LSI clock divided by 128 */\r
-/**\r
- * @}\r
- */\r
-#endif /* RCC_CSR_LSIPREDIV */\r
-\r
-/** @defgroup RCC_MSI_Config MSI Config\r
- * @{\r
- */\r
-#define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */\r
-#define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */\r
-\r
-#define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined(RCC_HSI48_SUPPORT)\r
-/** @defgroup RCC_HSI48_Config HSI48 Config\r
- * @{\r
- */\r
-#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */\r
-#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */\r
-/**\r
- * @}\r
- */\r
-#else\r
-/** @defgroup RCC_HSI48_Config HSI48 Config\r
- * @{\r
- */\r
-#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */\r
-/**\r
- * @}\r
- */\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-/** @defgroup RCC_PLL_Config PLL Config\r
- * @{\r
- */\r
-#define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */\r
-#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */\r
-#define RCC_PLL_ON 0x00000002U /*!< PLL activation */\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined(RCC_PLLP_SUPPORT)\r
-/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider\r
- * @{\r
- */\r
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
-#define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */\r
-#define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */\r
-#define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */\r
-#define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */\r
-#define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */\r
-#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */\r
-#define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */\r
-#define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */\r
-#define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */\r
-#define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */\r
-#define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */\r
-#define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */\r
-#define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */\r
-#define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */\r
-#define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */\r
-#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */\r
-#define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */\r
-#define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */\r
-#define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */\r
-#define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */\r
-#define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */\r
-#define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */\r
-#define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */\r
-#define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */\r
-#define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */\r
-#define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */\r
-#define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */\r
-#define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */\r
-#define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */\r
-#define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */\r
-#else\r
-#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */\r
-#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */\r
-#endif /* RCC_PLLP_DIV_2_31_SUPPORT */\r
-/**\r
- * @}\r
- */\r
-#endif /* RCC_PLLP_SUPPORT */\r
-\r
-/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider\r
- * @{\r
- */\r
-#define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */\r
-#define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */\r
-#define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */\r
-#define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider\r
- * @{\r
- */\r
-#define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */\r
-#define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */\r
-#define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */\r
-#define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source\r
- * @{\r
- */\r
-#define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */\r
-#define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */\r
-#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */\r
-#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_PLL_Clock_Output PLL Clock Output\r
- * @{\r
- */\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-#define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */\r
-#elif defined(RCC_PLLSAI1_SUPPORT)\r
-#define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-#define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */\r
-#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */\r
-/**\r
- * @}\r
- */\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-\r
-/** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output\r
- * @{\r
- */\r
-#define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */\r
-#define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */\r
-#define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */\r
-/**\r
- * @}\r
- */\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
-/** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output\r
- * @{\r
- */\r
-#define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */\r
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\r
-#define RCC_PLLSAI2_DSICLK RCC_PLLSAI2CFGR_PLLSAI2QEN /*!< PLLDSICLK selection from PLLSAI2 */\r
-#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */\r
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
-#define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */\r
-#else\r
-#define RCC_PLLSAI2_LTDCCLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLLTDCCLK selection from PLLSAI2 */\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-/** @defgroup RCC_MSI_Clock_Range MSI Clock Range\r
- * @{\r
- */\r
-#define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */\r
-#define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */\r
-#define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */\r
-#define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */\r
-#define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */\r
-#define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */\r
-#define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */\r
-#define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */\r
-#define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */\r
-#define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */\r
-#define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */\r
-#define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_System_Clock_Type System Clock Type\r
- * @{\r
- */\r
-#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */\r
-#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */\r
-#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */\r
-#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_System_Clock_Source System Clock Source\r
- * @{\r
- */\r
-#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */\r
-#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */\r
-#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */\r
-#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status\r
- * @{\r
- */\r
-#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */\r
-#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */\r
-#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */\r
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB_Clock_Source AHB Clock Source\r
- * @{\r
- */\r
-#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */\r
-#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */\r
-#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */\r
-#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */\r
-#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */\r
-#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */\r
-#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */\r
-#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */\r
-#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source\r
- * @{\r
- */\r
-#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */\r
-#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */\r
-#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */\r
-#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */\r
-#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_RTC_Clock_Source RTC Clock Source\r
- * @{\r
- */\r
-#define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */\r
-#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */\r
-#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */\r
-#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_MCO_Index MCO Index\r
- * @{\r
- */\r
-#define RCC_MCO1 0x00000000U\r
-#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source\r
- * @{\r
- */\r
-#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */\r
-#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */\r
-#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */\r
-#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */\r
-#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */\r
-#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */\r
-#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */\r
-#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */\r
-#endif /* RCC_HSI48_SUPPORT */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler\r
- * @{\r
- */\r
-#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */\r
-#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */\r
-#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */\r
-#define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */\r
-#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Interrupt Interrupts\r
- * @{\r
- */\r
-#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */\r
-#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */\r
-#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */\r
-#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */\r
-#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */\r
-#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-#define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-#define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-#define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */\r
-#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */\r
-#endif /* RCC_HSI48_SUPPORT */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Flag Flags\r
- * Elements values convention: XXXYYYYYb\r
- * - YYYYY : Flag position in the register\r
- * - XXX : Register index\r
- * - 001: CR register\r
- * - 010: BDCR register\r
- * - 011: CSR register\r
- * - 100: CRRCR register\r
- * @{\r
- */\r
-/* Flags in the CR register */\r
-#define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */\r
-#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */\r
-#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */\r
-#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-#define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-#define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-/* Flags in the BDCR register */\r
-#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */\r
-#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */\r
-\r
-/* Flags in the CSR register */\r
-#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */\r
-#define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */\r
-#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */\r
-#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */\r
-#define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */\r
-#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */\r
-#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */\r
-#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */\r
-#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */\r
-\r
-#if defined(RCC_HSI48_SUPPORT)\r
-/* Flags in the CRRCR register */\r
-#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */\r
-#endif /* RCC_HSI48_SUPPORT */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_LSEDrive_Config LSE Drive Config\r
- * @{\r
- */\r
-#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */\r
-#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */\r
-#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */\r
-#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock\r
- * @{\r
- */\r
-#define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */\r
-#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-\r
-/** @defgroup RCC_Exported_Macros RCC Exported Macros\r
- * @{\r
- */\r
-\r
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable\r
- * @brief Enable or disable the AHB1 peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before\r
- * using it.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_DMA1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#define __HAL_RCC_DMA2_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#define __HAL_RCC_CRC_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#define __HAL_RCC_TSC_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* GFXMMU */\r
-\r
-\r
-#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)\r
-\r
-#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)\r
-\r
-#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)\r
-\r
-#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN)\r
-#endif /* GFXMMU */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable\r
- * @brief Enable or disable the AHB2 peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before\r
- * using it.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* GPIOI */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(OCTOSPIM)\r
-#define __HAL_RCC_OSPIM_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* OCTOSPIM */\r
-\r
-#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)\r
-#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */\r
-\r
-\r
-#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)\r
-\r
-#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)\r
-\r
-#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN)\r
-#endif /* GPIOI */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)\r
-\r
-#if defined(OCTOSPIM)\r
-#define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN)\r
-#endif /* OCTOSPIM */\r
-\r
-#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)\r
-#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN)\r
-#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable\r
- * @brief Enable or disable the AHB3 peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before\r
- * using it.\r
- * @{\r
- */\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* FMC_BANK1 */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(OCTOSPI1)\r
-#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* OCTOSPI1 */\r
-\r
-#if defined(OCTOSPI2)\r
-#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* OCTOSPI2 */\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)\r
-#endif /* FMC_BANK1 */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(OCTOSPI1)\r
-#define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN)\r
-#endif /* OCTOSPI1 */\r
-\r
-#if defined(OCTOSPI2)\r
-#define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN)\r
-#endif /* OCTOSPI2 */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable\r
- * @brief Enable or disable the APB1 peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before\r
- * using it.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_TIM2_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* LCD */\r
-\r
-#if defined(RCC_APB1ENR1_RTCAPBEN)\r
-#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* RCC_APB1ENR1_RTCAPBEN */\r
-\r
-#define __HAL_RCC_WWDG_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-\r
-#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);\r
-#endif /* LCD */\r
-\r
-#if defined(RCC_APB1ENR1_RTCAPBEN)\r
-#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);\r
-#endif /* RCC_APB1ENR1_RTCAPBEN */\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN);\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)\r
-\r
-#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)\r
-\r
-#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable\r
- * @brief Enable or disable the APB2 peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before\r
- * using it.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)\r
-#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */\r
-\r
-#define __HAL_RCC_TIM1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#define __HAL_RCC_SPI1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-\r
-#define __HAL_RCC_TIM15_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#define __HAL_RCC_TIM16_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_CLK_ENABLE() do { \\r
- __IO uint32_t tmpreg; \\r
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \\r
- /* Delay after an RCC peripheral clock enabling */ \\r
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \\r
- UNUSED(tmpreg); \\r
- } while(0)\r
-#endif /* DSI */\r
-\r
-\r
-#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)\r
-#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)\r
-#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */\r
-\r
-#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)\r
-\r
-#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)\r
-\r
-#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)\r
-\r
-#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN)\r
-#endif /* DSI */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status\r
- * @brief Check whether the AHB1 peripheral clock is enabled or not.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before\r
- * using it.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U)\r
-\r
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)\r
-\r
-#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)\r
-\r
-#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U)\r
-#endif /* GFXMMU */\r
-\r
-\r
-#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U)\r
-\r
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)\r
-\r
-#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)\r
-\r
-#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U)\r
-#endif /* GFXMMU */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status\r
- * @brief Check whether the AHB2 peripheral clock is enabled or not.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before\r
- * using it.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)\r
-\r
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)\r
-\r
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U)\r
-#endif /* GPIOI */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != 0U)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != 0U)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)\r
-\r
-\r
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)\r
-\r
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)\r
-\r
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U)\r
-#endif /* GPIOI */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == 0U)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == 0U)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status\r
- * @brief Check whether the AHB3 peripheral clock is enabled or not.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before\r
- * using it.\r
- * @{\r
- */\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)\r
-#endif /* FMC_BANK1 */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)\r
-#endif /* FMC_BANK1 */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U)\r
-#endif /* QUADSPI */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status\r
- * @brief Check whether the APB1 peripheral clock is enabled or not.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before\r
- * using it.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != 0U)\r
-#endif /* LCD */\r
-\r
-#if defined(RCC_APB1ENR1_RTCAPBEN)\r
-#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U)\r
-#endif /* RCC_APB1ENR1_RTCAPBEN */\r
-\r
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != 0U)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != 0U)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != 0U)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != 0U)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != 0U)\r
-\r
-#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)\r
-\r
-#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != 0U)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U)\r
-\r
-\r
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == 0U)\r
-#endif /* LCD */\r
-\r
-#if defined(RCC_APB1ENR1_RTCAPBEN)\r
-#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U)\r
-#endif /* RCC_APB1ENR1_RTCAPBEN */\r
-\r
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U)\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == 0U)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == 0U)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == 0U)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == 0U)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == 0U)\r
-\r
-#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U)\r
-\r
-#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == 0U)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status\r
- * @brief Check whether the APB2 peripheral clock is enabled or not.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before\r
- * using it.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)\r
-\r
-#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != 0U)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)\r
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != 0U)\r
-#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */\r
-\r
-#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)\r
-\r
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)\r
-\r
-#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)\r
-\r
-#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != 0U)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != 0U)\r
-#endif /* DSI */\r
-\r
-\r
-#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)\r
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == 0U)\r
-#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */\r
-\r
-#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)\r
-\r
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)\r
-\r
-#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)\r
-\r
-#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == 0U)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == 0U)\r
-#endif /* DSI */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset\r
- * @brief Force or release AHB1 peripheral reset.\r
- * @{\r
- */\r
-#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)\r
-\r
-#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)\r
-\r
-#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)\r
-\r
-#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)\r
-\r
-#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST)\r
-#endif /* GFXMMU */\r
-\r
-\r
-#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)\r
-\r
-#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)\r
-\r
-#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)\r
-\r
-#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)\r
-\r
-#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST)\r
-#endif /* GFXMMU */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset\r
- * @brief Force or release AHB2 peripheral reset.\r
- * @{\r
- */\r
-#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)\r
-\r
-#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)\r
-\r
-#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)\r
-\r
-#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)\r
-#endif /* GPIOI */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)\r
-\r
-#if defined(OCTOSPIM)\r
-#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST)\r
-#endif /* OCTOSPIM */\r
-\r
-#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST)\r
-#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST)\r
-#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */\r
-\r
-\r
-#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)\r
-\r
-#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)\r
-\r
-#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)\r
-\r
-#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)\r
-#endif /* GPIOI */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)\r
-\r
-#if defined(OCTOSPIM)\r
-#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST)\r
-#endif /* OCTOSPIM */\r
-\r
-#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST)\r
-#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST)\r
-#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset\r
- * @brief Force or release AHB3 peripheral reset.\r
- * @{\r
- */\r
-#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)\r
-#endif /* FMC_BANK1 */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(OCTOSPI1)\r
-#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST)\r
-#endif /* OCTOSPI1 */\r
-\r
-#if defined(OCTOSPI2)\r
-#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST)\r
-#endif /* OCTOSPI2 */\r
-\r
-#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)\r
-#endif /* FMC_BANK1 */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(OCTOSPI1)\r
-#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST)\r
-#endif /* OCTOSPI1 */\r
-\r
-#if defined(OCTOSPI2)\r
-#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST)\r
-#endif /* OCTOSPI2 */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset\r
- * @brief Force or release APB1 peripheral reset.\r
- * @{\r
- */\r
-#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)\r
-\r
-#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)\r
-#endif /* LCD */\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)\r
-\r
-#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)\r
-\r
-#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)\r
-\r
-\r
-#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)\r
-\r
-#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)\r
-#endif /* LCD */\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)\r
-\r
-#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)\r
-\r
-#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset\r
- * @brief Force or release APB2 peripheral reset.\r
- * @{\r
- */\r
-#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)\r
-\r
-#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)\r
-#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)\r
-#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */\r
-\r
-#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)\r
-\r
-#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)\r
-\r
-#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)\r
-\r
-#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST)\r
-#endif /* DSI */\r
-\r
-\r
-#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)\r
-\r
-#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)\r
-#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)\r
-#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */\r
-\r
-#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)\r
-\r
-#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)\r
-\r
-#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)\r
-\r
-#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST)\r
-#endif /* DSI */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable\r
- * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\r
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
- * power consumption.\r
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)\r
-\r
-#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)\r
-\r
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)\r
-\r
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)\r
-\r
-#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN)\r
-#endif /* GFXMMU */\r
-\r
-\r
-#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)\r
-\r
-#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)\r
-\r
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)\r
-\r
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)\r
-\r
-#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN)\r
-#endif /* GFXMMU */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable\r
- * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\r
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
- * power consumption.\r
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)\r
-\r
-#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)\r
-\r
-#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)\r
-#endif /* GPIOI */\r
-\r
-#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)\r
-\r
-#if defined(SRAM3)\r
-#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN)\r
-#endif /* SRAM3 */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)\r
-\r
-#if defined(OCTOSPIM)\r
-#define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN)\r
-#endif /* OCTOSPIM */\r
-\r
-#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)\r
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN)\r
-#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */\r
-\r
-\r
-#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)\r
-\r
-#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)\r
-\r
-#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)\r
-#endif /* GPIOI */\r
-\r
-#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)\r
-\r
-#if defined(SRAM3)\r
-#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN)\r
-#endif /* SRAM3 */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)\r
-\r
-#if defined(OCTOSPIM)\r
-#define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN)\r
-#endif /* OCTOSPIM */\r
-\r
-#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)\r
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN)\r
-#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable\r
- * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.\r
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
- * power consumption.\r
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
- * @{\r
- */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(OCTOSPI1)\r
-#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN)\r
-#endif /* OCTOSPI1 */\r
-\r
-#if defined(OCTOSPI2)\r
-#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN)\r
-#endif /* OCTOSPI2 */\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)\r
-#endif /* FMC_BANK1 */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(OCTOSPI1)\r
-#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN)\r
-#endif /* OCTOSPI1 */\r
-\r
-#if defined(OCTOSPI2)\r
-#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN)\r
-#endif /* OCTOSPI2 */\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)\r
-#endif /* FMC_BANK1 */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable\r
- * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
- * power consumption.\r
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)\r
-#endif /* LCD */\r
-\r
-#if defined(RCC_APB1SMENR1_RTCAPBSMEN)\r
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)\r
-#endif /* RCC_APB1SMENR1_RTCAPBSMEN */\r
-\r
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)\r
-\r
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)\r
-\r
-#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)\r
-\r
-\r
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)\r
-#endif /* LCD */\r
-\r
-#if defined(RCC_APB1SMENR1_RTCAPBSMEN)\r
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)\r
-#endif /* RCC_APB1SMENR1_RTCAPBSMEN */\r
-\r
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)\r
-\r
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)\r
-\r
-#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable\r
- * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
- * power consumption.\r
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)\r
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)\r
-#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */\r
-\r
-#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)\r
-\r
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)\r
-\r
-#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)\r
-\r
-#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN)\r
-#endif /* DSI */\r
-\r
-\r
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)\r
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)\r
-#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */\r
-\r
-#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)\r
-\r
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)\r
-\r
-#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)\r
-\r
-#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN)\r
-#endif /* DSI */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status\r
- * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.\r
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
- * power consumption.\r
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U)\r
-\r
-#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U)\r
-\r
-#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U)\r
-\r
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U)\r
-\r
-#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != 0U)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != 0U)\r
-#endif /* GFXMMU */\r
-\r
-\r
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U)\r
-\r
-#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U)\r
-\r
-#if defined(DMAMUX1)\r
-#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U)\r
-#endif /* DMAMUX1 */\r
-\r
-#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U)\r
-\r
-#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U)\r
-\r
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U)\r
-\r
-#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == 0U)\r
-\r
-#if defined(DMA2D)\r
-#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == 0U)\r
-#endif /* DMA2D */\r
-\r
-#if defined(GFXMMU)\r
-#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == 0U)\r
-#endif /* GFXMMU */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status\r
- * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.\r
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
- * power consumption.\r
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U)\r
-\r
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U)\r
-\r
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != 0U)\r
-#endif /* GPIOI */\r
-\r
-#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U)\r
-\r
-#if defined(SRAM3)\r
-#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != 0U)\r
-#endif /* SRAM3 */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != 0U)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != 0U)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != 0U)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U)\r
-\r
-#if defined(OCTOSPIM)\r
-#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != 0U)\r
-#endif /* OCTOSPIM */\r
-\r
-#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)\r
-#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != 0U)\r
-#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */\r
-\r
-\r
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U)\r
-\r
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U)\r
-\r
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U)\r
-\r
-#if defined(GPIOD)\r
-#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U)\r
-#endif /* GPIOD */\r
-\r
-#if defined(GPIOE)\r
-#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U)\r
-#endif /* GPIOE */\r
-\r
-#if defined(GPIOF)\r
-#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U)\r
-#endif /* GPIOF */\r
-\r
-#if defined(GPIOG)\r
-#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U)\r
-#endif /* GPIOG */\r
-\r
-#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == 0U)\r
-\r
-#if defined(GPIOI)\r
-#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == 0U)\r
-#endif /* GPIOI */\r
-\r
-#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U)\r
-\r
-#if defined(SRAM3)\r
-#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == 0U)\r
-#endif /* SRAM3 */\r
-\r
-#if defined(USB_OTG_FS)\r
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == 0U)\r
-#endif /* USB_OTG_FS */\r
-\r
-#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == 0U)\r
-\r
-#if defined(DCMI)\r
-#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == 0U)\r
-#endif /* DCMI */\r
-\r
-#if defined(AES)\r
-#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U)\r
-#endif /* AES */\r
-\r
-#if defined(HASH)\r
-#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == 0U)\r
-#endif /* HASH */\r
-\r
-#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U)\r
-\r
-#if defined(OCTOSPIM)\r
-#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == 0U)\r
-#endif /* OCTOSPIM */\r
-\r
-#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)\r
-#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == 0U)\r
-#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status\r
- * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.\r
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
- * power consumption.\r
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
- * @{\r
- */\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(OCTOSPI1)\r
-#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != 0U)\r
-#endif /* OCTOSPI1 */\r
-\r
-#if defined(OCTOSPI2)\r
-#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != 0U)\r
-#endif /* OCTOSPI2 */\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U)\r
-#endif /* FMC_BANK1 */\r
-\r
-\r
-#if defined(QUADSPI)\r
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U)\r
-#endif /* QUADSPI */\r
-\r
-#if defined(OCTOSPI1)\r
-#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == 0U)\r
-#endif /* OCTOSPI1 */\r
-\r
-#if defined(OCTOSPI2)\r
-#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == 0U)\r
-#endif /* OCTOSPI2 */\r
-\r
-#if defined(FMC_BANK1)\r
-#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U)\r
-#endif /* FMC_BANK1 */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status\r
- * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.\r
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
- * power consumption.\r
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != 0U)\r
-#endif /* LCD */\r
-\r
-#if defined(RCC_APB1SMENR1_RTCAPBSMEN)\r
-#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U)\r
-#endif /* RCC_APB1SMENR1_RTCAPBSMEN */\r
-\r
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U)\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != 0U)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != 0U)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != 0U)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != 0U)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != 0U)\r
-\r
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U)\r
-\r
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != 0U)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U)\r
-\r
-\r
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U)\r
-\r
-#if defined(TIM3)\r
-#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U)\r
-#endif /* TIM3 */\r
-\r
-#if defined(TIM4)\r
-#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)\r
-#endif /* TIM4 */\r
-\r
-#if defined(TIM5)\r
-#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U)\r
-#endif /* TIM5 */\r
-\r
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U)\r
-\r
-#if defined(TIM7)\r
-#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U)\r
-#endif /* TIM7 */\r
-\r
-#if defined(LCD)\r
-#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == 0U)\r
-#endif /* LCD */\r
-\r
-#if defined(RCC_APB1SMENR1_RTCAPBSMEN)\r
-#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U)\r
-#endif /* RCC_APB1SMENR1_RTCAPBSMEN */\r
-\r
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U)\r
-\r
-#if defined(SPI2)\r
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U)\r
-#endif /* SPI2 */\r
-\r
-#if defined(SPI3)\r
-#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U)\r
-#endif /* SPI3 */\r
-\r
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U)\r
-\r
-#if defined(USART3)\r
-#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U)\r
-#endif /* USART3 */\r
-\r
-#if defined(UART4)\r
-#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U)\r
-#endif /* UART4 */\r
-\r
-#if defined(UART5)\r
-#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U)\r
-#endif /* UART5 */\r
-\r
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U)\r
-\r
-#if defined(I2C2)\r
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U)\r
-#endif /* I2C2 */\r
-\r
-#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U)\r
-\r
-#if defined(I2C4)\r
-#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U)\r
-#endif /* I2C4 */\r
-\r
-#if defined(CRS)\r
-#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)\r
-#endif /* CRS */\r
-\r
-#if defined(CAN1)\r
-#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == 0U)\r
-#endif /* CAN1 */\r
-\r
-#if defined(CAN2)\r
-#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == 0U)\r
-#endif /* CAN2 */\r
-\r
-#if defined(USB)\r
-#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == 0U)\r
-#endif /* USB */\r
-\r
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U)\r
-\r
-#if defined(DAC1)\r
-#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == 0U)\r
-#endif /* DAC1 */\r
-\r
-#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == 0U)\r
-\r
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U)\r
-\r
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U)\r
-\r
-#if defined(SWPMI1)\r
-#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == 0U)\r
-#endif /* SWPMI1 */\r
-\r
-#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == 0U)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status\r
- * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.\r
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
- * power consumption.\r
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
- * @{\r
- */\r
-\r
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)\r
-#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != 0U)\r
-#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */\r
-\r
-#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U)\r
-\r
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)\r
-\r
-#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U)\r
-\r
-#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != 0U)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != 0U)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != 0U)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != 0U)\r
-#endif /* DSI */\r
-\r
-\r
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)\r
-\r
-#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)\r
-#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == 0U)\r
-#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */\r
-\r
-#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U)\r
-\r
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U)\r
-\r
-#if defined(TIM8)\r
-#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U)\r
-#endif /* TIM8 */\r
-\r
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U)\r
-\r
-#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U)\r
-\r
-#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U)\r
-\r
-#if defined(TIM17)\r
-#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U)\r
-#endif /* TIM17 */\r
-\r
-#if defined(SAI1)\r
-#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U)\r
-#endif /* SAI1 */\r
-\r
-#if defined(SAI2)\r
-#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == 0U)\r
-#endif /* SAI2 */\r
-\r
-#if defined(DFSDM1_Filter0)\r
-#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == 0U)\r
-#endif /* DFSDM1_Filter0 */\r
-\r
-#if defined(LTDC)\r
-#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == 0U)\r
-#endif /* LTDC */\r
-\r
-#if defined(DSI)\r
-#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == 0U)\r
-#endif /* DSI */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset\r
- * @{\r
- */\r
-\r
-/** @brief Macros to force or release the Backup domain reset.\r
- * @note This function resets the RTC peripheral (including the backup registers)\r
- * and the RTC clock source selection in RCC_CSR register.\r
- * @note The BKPSRAM is not affected by this reset.\r
- * @retval None\r
- */\r
-#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)\r
-\r
-#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration\r
- * @{\r
- */\r
-\r
-/** @brief Macros to enable or disable the RTC clock.\r
- * @note As the RTC is in the Backup domain and write access is denied to\r
- * this domain after reset, you have to enable write access using\r
- * HAL_PWR_EnableBkUpAccess() function before to configure the RTC\r
- * (to be done once after reset).\r
- * @note These macros must be used after the RTC clock source was selected.\r
- * @retval None\r
- */\r
-#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)\r
-\r
-#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).\r
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.\r
- * It is used (enabled by hardware) as system clock source after startup\r
- * from Reset, wakeup from STOP and STANDBY mode, or in case of failure\r
- * of the HSE used directly or indirectly as system clock (if the Clock\r
- * Security System CSS is enabled).\r
- * @note HSI can not be stopped if it is used as system clock source. In this case,\r
- * you have to select another source of the system clock then stop the HSI.\r
- * @note After enabling the HSI, the application software should wait on HSIRDY\r
- * flag to be set indicating that HSI clock is stable and can be used as\r
- * system clock source.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
- * clock cycles.\r
- * @retval None\r
- */\r
-#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)\r
-\r
-#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)\r
-\r
-/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.\r
- * @note The calibration is used to compensate for the variations in voltage\r
- * and temperature that influence the frequency of the internal HSI RC.\r
- * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value\r
- * (default is RCC_HSICALIBRATION_DEFAULT).\r
- * This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices).\r
- * @retval None\r
- */\r
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \\r
- MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)\r
-\r
-/**\r
- * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)\r
- * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.\r
- * @note The enable of this function has not effect on the HSION bit.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)\r
-\r
-#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)\r
-\r
-/**\r
- * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)\r
- * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.\r
- * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication\r
- * speed because of the HSI startup time.\r
- * @note The enable of this function has not effect on the HSION bit.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)\r
-\r
-#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)\r
-\r
-/**\r
- * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).\r
- * @note The MSI is stopped by hardware when entering STOP and STANDBY modes.\r
- * It is used (enabled by hardware) as system clock source after\r
- * startup from Reset, wakeup from STOP and STANDBY mode, or in case\r
- * of failure of the HSE used directly or indirectly as system clock\r
- * (if the Clock Security System CSS is enabled).\r
- * @note MSI can not be stopped if it is used as system clock source.\r
- * In this case, you have to select another source of the system\r
- * clock then stop the MSI.\r
- * @note After enabling the MSI, the application software should wait on\r
- * MSIRDY flag to be set indicating that MSI clock is stable and can\r
- * be used as system clock source.\r
- * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator\r
- * clock cycles.\r
- * @retval None\r
- */\r
-#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)\r
-\r
-#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)\r
-\r
-/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.\r
- * @note The calibration is used to compensate for the variations in voltage\r
- * and temperature that influence the frequency of the internal MSI RC.\r
- * Refer to the Application Note AN3300 for more details on how to\r
- * calibrate the MSI.\r
- * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value\r
- * (default is RCC_MSICALIBRATION_DEFAULT).\r
- * This parameter must be a number between 0 and 255.\r
- * @retval None\r
- */\r
-#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \\r
- MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos)\r
-\r
-/**\r
- * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode\r
- * @note After restart from Reset , the MSI clock is around 4 MHz.\r
- * After stop the startup clock can be MSI (at any of its possible\r
- * frequencies, the one that was used before entering stop mode) or HSI.\r
- * After Standby its frequency can be selected between 4 possible values\r
- * (1, 2, 4 or 8 MHz).\r
- * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready\r
- * (MSIRDY=1).\r
- * @note The MSI clock range after reset can be modified on the fly.\r
- * @param __MSIRANGEVALUE__ specifies the MSI clock range.\r
- * This parameter must be one of the following values:\r
- * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz\r
- * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz\r
- * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz\r
- * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz\r
- * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz\r
- * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz\r
- * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)\r
- * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz\r
- * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz\r
- * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz\r
- * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz\r
- * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz\r
- * @retval None\r
- */\r
-#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \\r
- do { \\r
- SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \\r
- MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \\r
- } while(0)\r
-\r
-/**\r
- * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode\r
- * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).\r
- * @param __MSIRANGEVALUE__ specifies the MSI clock range.\r
- * This parameter must be one of the following values:\r
- * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz\r
- * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz\r
- * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)\r
- * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz\r
- * @retval None\r
- */\r
-#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \\r
- MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)\r
-\r
-/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode\r
- * @retval MSI clock range.\r
- * This parameter must be one of the following values:\r
- * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz\r
- * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz\r
- * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz\r
- * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz\r
- * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz\r
- * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz\r
- * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)\r
- * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz\r
- * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz\r
- * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz\r
- * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz\r
- * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz\r
- */\r
-#define __HAL_RCC_GET_MSI_RANGE() \\r
- ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \\r
- READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \\r
- (READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U))\r
-\r
-/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).\r
- * @note After enabling the LSI, the application software should wait on\r
- * LSIRDY flag to be set indicating that LSI clock is stable and can\r
- * be used to clock the IWDG and/or the RTC.\r
- * @note LSI can not be disabled if the IWDG is running.\r
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
- * clock cycles.\r
- * @retval None\r
- */\r
-#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)\r
-\r
-#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)\r
-\r
-/**\r
- * @brief Macro to configure the External High Speed oscillator (HSE).\r
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r
- * supported by this macro. User should request a transition to HSE Off\r
- * first and then HSE On or HSE Bypass.\r
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r
- * software should wait on HSERDY flag to be set indicating that HSE clock\r
- * is stable and can be used to clock the PLL and/or system clock.\r
- * @note HSE state can not be changed if it is used directly or through the\r
- * PLL as system clock. In this case, you have to select another source\r
- * of the system clock then change the HSE state (ex. disable it).\r
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.\r
- * @note This function reset the CSSON bit, so if the clock security system(CSS)\r
- * was previously enabled you have to enable it again after calling this\r
- * function.\r
- * @param __STATE__ specifies the new state of the HSE.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after\r
- * 6 HSE oscillator clock cycles.\r
- * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.\r
- * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock.\r
- * @retval None\r
- */\r
-#define __HAL_RCC_HSE_CONFIG(__STATE__) \\r
- do { \\r
- if((__STATE__) == RCC_HSE_ON) \\r
- { \\r
- SET_BIT(RCC->CR, RCC_CR_HSEON); \\r
- } \\r
- else if((__STATE__) == RCC_HSE_BYPASS) \\r
- { \\r
- SET_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
- SET_BIT(RCC->CR, RCC_CR_HSEON); \\r
- } \\r
- else \\r
- { \\r
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \\r
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
- } \\r
- } while(0)\r
-\r
-/**\r
- * @brief Macro to configure the External Low Speed oscillator (LSE).\r
- * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\r
- * supported by this macro. User should request a transition to LSE Off\r
- * first and then LSE On or LSE Bypass.\r
- * @note As the LSE is in the Backup domain and write access is denied to\r
- * this domain after reset, you have to enable write access using\r
- * HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r
- * (to be done once after reset).\r
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application\r
- * software should wait on LSERDY flag to be set indicating that LSE clock\r
- * is stable and can be used to clock the RTC.\r
- * @param __STATE__ specifies the new state of the LSE.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after\r
- * 6 LSE oscillator clock cycles.\r
- * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.\r
- * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.\r
- * @retval None\r
- */\r
-#define __HAL_RCC_LSE_CONFIG(__STATE__) \\r
- do { \\r
- if((__STATE__) == RCC_LSE_ON) \\r
- { \\r
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
- } \\r
- else if((__STATE__) == RCC_LSE_BYPASS) \\r
- { \\r
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
- } \\r
- else \\r
- { \\r
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
- } \\r
- } while(0)\r
-\r
-#if defined(RCC_HSI48_SUPPORT)\r
-\r
-/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).\r
- * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.\r
- * @note After enabling the HSI48, the application software should wait on HSI48RDY\r
- * flag to be set indicating that HSI48 clock is stable.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)\r
-\r
-#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)\r
-\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-/** @brief Macros to configure the RTC clock (RTCCLK).\r
- * @note As the RTC clock configuration bits are in the Backup domain and write\r
- * access is denied to this domain after reset, you have to enable write\r
- * access using the Power Backup Access macro before to configure\r
- * the RTC clock source (to be done once after reset).\r
- * @note Once the RTC clock is configured it cannot be changed unless the\r
- * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by\r
- * a Power On Reset (POR).\r
- *\r
- * @param __RTC_CLKSOURCE__ specifies the RTC clock source.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.\r
- * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.\r
- * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.\r
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected\r
- *\r
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to\r
- * work in STOP and STANDBY modes, and can be used as wakeup source.\r
- * However, when the HSE clock is used as RTC clock source, the RTC\r
- * cannot be used in STOP and STANDBY modes.\r
- * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as\r
- * RTC clock source).\r
- * @retval None\r
- */\r
-#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \\r
- MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))\r
-\r
-\r
-/** @brief Macro to get the RTC clock source.\r
- * @retval The returned value can be one of the following:\r
- * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.\r
- * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.\r
- * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.\r
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected\r
- */\r
-#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))\r
-\r
-/** @brief Macros to enable or disable the main PLL.\r
- * @note After enabling the main PLL, the application software should wait on\r
- * PLLRDY flag to be set indicating that PLL clock is stable and can\r
- * be used as system clock source.\r
- * @note The main PLL can not be disabled if it is used as system clock source\r
- * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.\r
- * @retval None\r
- */\r
-#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)\r
-\r
-#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)\r
-\r
-/** @brief Macro to configure the PLL clock source.\r
- * @note This function must be used only when the main PLL is disabled.\r
- * @param __PLLSOURCE__ specifies the PLL entry clock source.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry\r
- * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry\r
- * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry\r
- * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry\r
- * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).\r
- * @retval None\r
- *\r
- */\r
-#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \\r
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))\r
-\r
-/** @brief Macro to configure the PLL source division factor M.\r
- * @note This function must be used only when the main PLL is disabled.\r
- * @param __PLLM__ specifies the division factor for PLL VCO input clock\r
- * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.\r
- * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices.\r
- * @note You have to set the PLLM parameter correctly to ensure that the VCO input\r
- * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency\r
- * of 16 MHz to limit PLL jitter.\r
- * @retval None\r
- *\r
- */\r
-#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \\r
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)\r
-\r
-/**\r
- * @brief Macro to configure the main PLL clock source, multiplication and division factors.\r
- * @note This function must be used only when the main PLL is disabled.\r
- *\r
- * @param __PLLSOURCE__ specifies the PLL entry clock source.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry\r
- * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry\r
- * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry\r
- * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry\r
- * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).\r
- *\r
- * @param __PLLM__ specifies the division factor for PLL VCO input clock.\r
- * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.\r
- * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices.\r
- * @note You have to set the PLLM parameter correctly to ensure that the VCO input\r
- * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency\r
- * of 16 MHz to limit PLL jitter.\r
- *\r
- * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock.\r
- * This parameter must be a number between 8 and 86.\r
- * @note You have to set the PLLN parameter correctly to ensure that the VCO\r
- * output frequency is between 64 and 344 MHz.\r
- *\r
- * @param __PLLP__ specifies the division factor for SAI clock when SAI available on device.\r
- * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x\r
- * else (2 to 31).\r
- *\r
- * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks.\r
- * This parameter must be in the range (2, 4, 6 or 8).\r
- * @note If the USB OTG FS is used in your application, you have to set the\r
- * PLLQ parameter correctly to have 48 MHz clock for the USB. However,\r
- * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work\r
- * correctly.\r
- * @param __PLLR__ specifies the division factor for the main system clock.\r
- * @note You have to set the PLLR parameter correctly to not exceed 80MHZ.\r
- * This parameter must be in the range (2, 4, 6 or 8).\r
- * @retval None\r
- */\r
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
-\r
-#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \\r
- MODIFY_REG(RCC->PLLCFGR, \\r
- (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \\r
- RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLPDIV), \\r
- ((__PLLSOURCE__) | \\r
- (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \\r
- ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \\r
- ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \\r
- ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \\r
- ((uint32_t)(__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))\r
-\r
-#elif defined(RCC_PLLP_SUPPORT)\r
-\r
-#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \\r
- MODIFY_REG(RCC->PLLCFGR, \\r
- (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \\r
- RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP), \\r
- ((__PLLSOURCE__) | \\r
- (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \\r
- ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \\r
- ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \\r
- ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \\r
- (((__PLLP__) >> 4U) << RCC_PLLCFGR_PLLP_Pos)))\r
-\r
-#else\r
-\r
-#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLQ__,__PLLR__ ) \\r
- MODIFY_REG(RCC->PLLCFGR, \\r
- (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \\r
- RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \\r
- ((__PLLSOURCE__) | \\r
- (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \\r
- ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \\r
- ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \\r
- ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))\r
-\r
-#endif /* RCC_PLLP_DIV_2_31_SUPPORT */\r
-\r
-/** @brief Macro to get the oscillator used as PLL clock source.\r
- * @retval The oscillator used as PLL clock source. The returned value can be one\r
- * of the following:\r
- * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.\r
- * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.\r
- * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.\r
- * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.\r
- */\r
-#define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))\r
-\r
-/**\r
- * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)\r
- * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime\r
- * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot\r
- * be stopped if used as System Clock.\r
- * @param __PLLCLOCKOUT__ specifies the PLL clock to be output.\r
- * This parameter can be one or a combination of the following values:\r
- * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve\r
- * high-quality audio performance on SAI interface in case.\r
- * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),\r
- * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).\r
- * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)\r
- * @retval None\r
- */\r
-#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))\r
-\r
-#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))\r
-\r
-/**\r
- * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)\r
- * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve\r
- * high-quality audio performance on SAI interface in case.\r
- * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),\r
- * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).\r
- * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)\r
- * @retval SET / RESET\r
- */\r
-#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))\r
-\r
-/**\r
- * @brief Macro to configure the system clock source.\r
- * @param __SYSCLKSOURCE__ specifies the system clock source.\r
- * This parameter can be one of the following values:\r
- * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.\r
- * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.\r
- * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.\r
- * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.\r
- * @retval None\r
- */\r
-#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))\r
-\r
-/** @brief Macro to get the clock source used as system clock.\r
- * @retval The clock source used as system clock. The returned value can be one\r
- * of the following:\r
- * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.\r
- * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.\r
- * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.\r
- * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.\r
- */\r
-#define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))\r
-\r
-/**\r
- * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.\r
- * @note As the LSE is in the Backup domain and write access is denied to\r
- * this domain after reset, you have to enable write access using\r
- * HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r
- * (to be done once after reset).\r
- * @param __LSEDRIVE__ specifies the new state of the LSE drive capability.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.\r
- * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.\r
- * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.\r
- * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.\r
- * @retval None\r
- */\r
-#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \\r
- MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))\r
-\r
-/**\r
- * @brief Macro to configure the wake up from stop clock.\r
- * @param __STOPWUCLK__ specifies the clock source used after wake up from stop.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source\r
- * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source\r
- * @retval None\r
- */\r
-#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))\r
-\r
-\r
-/** @brief Macro to configure the MCO clock.\r
- * @param __MCOCLKSOURCE__ specifies the MCO clock source.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled\r
- * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee\r
- * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source\r
- @if STM32L443xx\r
- * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48\r
- @endif\r
- @if STM32L4A6xx\r
- * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48\r
- @endif\r
- * @param __MCODIV__ specifies the MCO clock prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1\r
- * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2\r
- * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4\r
- * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8\r
- * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16\r
- */\r
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\r
- MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))\r
-\r
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management\r
- * @brief macros to manage the specified RCC Flags and interrupts.\r
- * @{\r
- */\r
-\r
-/** @brief Enable RCC interrupt(s).\r
- * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt\r
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt\r
- * @arg @ref RCC_IT_MSIRDY HSI ready interrupt\r
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt\r
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt\r
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt\r
- * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1\r
- * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2\r
- * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt\r
- @if STM32L443xx\r
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48\r
- @endif\r
- @if STM32L4A6xx\r
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48\r
- @endif\r
- * @retval None\r
- */\r
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))\r
-\r
-/** @brief Disable RCC interrupt(s).\r
- * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt\r
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt\r
- * @arg @ref RCC_IT_MSIRDY HSI ready interrupt\r
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt\r
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt\r
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt\r
- * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1\r
- * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2\r
- * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt\r
- @if STM32L443xx\r
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48\r
- @endif\r
- @if STM32L4A6xx\r
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48\r
- @endif\r
- * @retval None\r
- */\r
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))\r
-\r
-/** @brief Clear the RCC's interrupt pending bits.\r
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt\r
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt\r
- * @arg @ref RCC_IT_MSIRDY MSI ready interrupt\r
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt\r
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt\r
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt\r
- * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1\r
- * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2\r
- * @arg @ref RCC_IT_CSS HSE Clock security system interrupt\r
- * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt\r
- @if STM32L443xx\r
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48\r
- @endif\r
- @if STM32L4A6xx\r
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48\r
- @endif\r
- * @retval None\r
- */\r
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__))\r
-\r
-/** @brief Check whether the RCC interrupt has occurred or not.\r
- * @param __INTERRUPT__ specifies the RCC interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt\r
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt\r
- * @arg @ref RCC_IT_MSIRDY MSI ready interrupt\r
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt\r
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt\r
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt\r
- * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1\r
- * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2\r
- * @arg @ref RCC_IT_CSS HSE Clock security system interrupt\r
- * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt\r
- @if STM32L443xx\r
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48\r
- @endif\r
- @if STM32L4A6xx\r
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48\r
- @endif\r
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r
- */\r
-#define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__))\r
-\r
-/** @brief Set RMVF bit to clear the reset flags.\r
- * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,\r
- * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.\r
- * @retval None\r
- */\r
-#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)\r
-\r
-/** @brief Check whether the selected RCC flag is set or not.\r
- * @param __FLAG__ specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready\r
- * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready\r
- * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready\r
- * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready\r
- * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready for devices with PLLSAI1\r
- * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2\r
- @if STM32L443xx\r
- * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48\r
- @endif\r
- @if STM32L4A6xx\r
- * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48\r
- @endif\r
- * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready\r
- * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection\r
- * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready\r
- * @arg @ref RCC_FLAG_BORRST BOR reset\r
- * @arg @ref RCC_FLAG_OBLRST OBLRST reset\r
- * @arg @ref RCC_FLAG_PINRST Pin reset\r
- * @arg @ref RCC_FLAG_FWRST FIREWALL reset\r
- * @arg @ref RCC_FLAG_SFTRST Software reset\r
- * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset\r
- * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset\r
- * @arg @ref RCC_FLAG_LPWRRST Low Power reset\r
- * @retval The new state of __FLAG__ (TRUE or FALSE).\r
- */\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \\r
- ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \\r
- ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \\r
- ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \\r
- (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U)\r
-#else\r
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \\r
- ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \\r
- ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \\r
- (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U)\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private constants ---------------------------------------------------------*/\r
-/** @defgroup RCC_Private_Constants RCC Private Constants\r
- * @{\r
- */\r
-/* Defines used for Flags */\r
-#define CR_REG_INDEX 1U\r
-#define BDCR_REG_INDEX 2U\r
-#define CSR_REG_INDEX 3U\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define CRRCR_REG_INDEX 4U\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-#define RCC_FLAG_MASK 0x1FU\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @addtogroup RCC_Private_Macros\r
- * @{\r
- */\r
-\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \\r
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \\r
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \\r
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \\r
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \\r
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \\r
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))\r
-#else\r
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \\r
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \\r
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \\r
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \\r
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \\r
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \\r
- ((__HSE__) == RCC_HSE_BYPASS))\r
-\r
-#if defined(RCC_BDCR_LSESYSDIS)\r
-#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \\r
- ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS))\r
-#else\r
-#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \\r
- ((__LSE__) == RCC_LSE_BYPASS))\r
-#endif /* RCC_BDCR_LSESYSDIS */\r
-\r
-#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))\r
-\r
-#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))\r
-\r
-#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))\r
-\r
-#if defined(RCC_CSR_LSIPREDIV)\r
-#define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128))\r
-#endif /* RCC_CSR_LSIPREDIV */\r
-\r
-#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))\r
-\r
-#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U)\r
-\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \\r
- ((__PLL__) == RCC_PLL_ON))\r
-\r
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \\r
- ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \\r
- ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \\r
- ((__SOURCE__) == RCC_PLLSOURCE_HSE))\r
-\r
-#if defined(RCC_PLLM_DIV_1_16_SUPPORT)\r
-#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))\r
-#else\r
-#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))\r
-#endif /*RCC_PLLM_DIV_1_16_SUPPORT */\r
-\r
-#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))\r
-\r
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
-#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))\r
-#else\r
-#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))\r
-#endif /*RCC_PLLP_DIV_2_31_SUPPORT */\r
-\r
-#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \\r
- ((__VALUE__) == 6U) || ((__VALUE__) == 8U))\r
-\r
-#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \\r
- ((__VALUE__) == 6U) || ((__VALUE__) == 8U))\r
-\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-#define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \\r
- (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \\r
- (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \\r
- (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U))\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)\r
-#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \\r
- (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \\r
- (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U))\r
-#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \\r
- (((__VALUE__) & RCC_PLLSAI2_DSICLK) == RCC_PLLSAI2_DSICLK) || \\r
- (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \\r
- (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U))\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
-#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \\r
- ((__RANGE__) == RCC_MSIRANGE_1) || \\r
- ((__RANGE__) == RCC_MSIRANGE_2) || \\r
- ((__RANGE__) == RCC_MSIRANGE_3) || \\r
- ((__RANGE__) == RCC_MSIRANGE_4) || \\r
- ((__RANGE__) == RCC_MSIRANGE_5) || \\r
- ((__RANGE__) == RCC_MSIRANGE_6) || \\r
- ((__RANGE__) == RCC_MSIRANGE_7) || \\r
- ((__RANGE__) == RCC_MSIRANGE_8) || \\r
- ((__RANGE__) == RCC_MSIRANGE_9) || \\r
- ((__RANGE__) == RCC_MSIRANGE_10) || \\r
- ((__RANGE__) == RCC_MSIRANGE_11))\r
-\r
-#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \\r
- ((__RANGE__) == RCC_MSIRANGE_5) || \\r
- ((__RANGE__) == RCC_MSIRANGE_6) || \\r
- ((__RANGE__) == RCC_MSIRANGE_7))\r
-\r
-#define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U))\r
-\r
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \\r
- ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \\r
- ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \\r
- ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))\r
-\r
-#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \\r
- ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \\r
- ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \\r
- ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \\r
- ((__HCLK__) == RCC_SYSCLK_DIV512))\r
-\r
-#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \\r
- ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \\r
- ((__PCLK__) == RCC_HCLK_DIV16))\r
-\r
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \\r
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \\r
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \\r
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))\r
-\r
-#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)\r
-\r
-#if defined(RCC_HSI48_SUPPORT)\r
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \\r
- ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \\r
- ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \\r
- ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \\r
- ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \\r
- ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \\r
- ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \\r
- ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \\r
- ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))\r
-#else\r
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \\r
- ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \\r
- ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \\r
- ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \\r
- ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \\r
- ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \\r
- ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \\r
- ((__SOURCE__) == RCC_MCO1SOURCE_LSE))\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
-#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \\r
- ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \\r
- ((__DIV__) == RCC_MCODIV_16))\r
-\r
-#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \\r
- ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \\r
- ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \\r
- ((__DRIVE__) == RCC_LSEDRIVE_HIGH))\r
-\r
-#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \\r
- ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))\r
-/**\r
- * @}\r
- */\r
-\r
-/* Include RCC HAL Extended module */\r
-#include "stm32l4xx_hal_rcc_ex.h"\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @addtogroup RCC_Exported_Functions\r
- * @{\r
- */\r
-\r
-\r
-/** @addtogroup RCC_Exported_Functions_Group1\r
- * @{\r
- */\r
-\r
-/* Initialization and de-initialization functions ******************************/\r
-HAL_StatusTypeDef HAL_RCC_DeInit(void);\r
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup RCC_Exported_Functions_Group2\r
- * @{\r
- */\r
-\r
-/* Peripheral Control functions ************************************************/\r
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);\r
-void HAL_RCC_EnableCSS(void);\r
-uint32_t HAL_RCC_GetSysClockFreq(void);\r
-uint32_t HAL_RCC_GetHCLKFreq(void);\r
-uint32_t HAL_RCC_GetPCLK1Freq(void);\r
-uint32_t HAL_RCC_GetPCLK2Freq(void);\r
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);\r
-/* CSS NMI IRQ handler */\r
-void HAL_RCC_NMI_IRQHandler(void);\r
-/* User Callbacks in non blocking mode (IT mode) */\r
-void HAL_RCC_CSSCallback(void);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32L4xx_HAL_RCC_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
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