+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l4xx_hal_rcc.c\r
- * @author MCD Application Team\r
- * @brief RCC HAL module driver.\r
- * This file provides firmware functions to manage the following\r
- * functionalities of the Reset and Clock Control (RCC) peripheral:\r
- * + Initialization and de-initialization functions\r
- * + Peripheral Control functions\r
- *\r
- @verbatim\r
- ==============================================================================\r
- ##### RCC specific features #####\r
- ==============================================================================\r
- [..]\r
- After reset the device is running from Multiple Speed Internal oscillator\r
- (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache\r
- and I-Cache are disabled, and all peripherals are off except internal\r
- SRAM, Flash and JTAG.\r
-\r
- (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses:\r
- all peripherals mapped on these busses are running at MSI speed.\r
- (+) The clock for all peripherals is switched off, except the SRAM and FLASH.\r
- (+) All GPIOs are in analog mode, except the JTAG pins which\r
- are assigned to be used for debug purpose.\r
-\r
- [..]\r
- Once the device started from reset, the user application has to:\r
- (+) Configure the clock source to be used to drive the System clock\r
- (if the application needs higher frequency/performance)\r
- (+) Configure the System clock frequency and Flash settings\r
- (+) Configure the AHB and APB busses prescalers\r
- (+) Enable the clock for the peripheral(s) to be used\r
- (+) Configure the clock source(s) for peripherals which clocks are not\r
- derived from the System clock (SAIx, RTC, ADC, USB OTG FS/SDMMC1/RNG)\r
-\r
- @endverbatim\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
- * All rights reserved.</center></h2>\r
- *\r
- * This software component is licensed by ST under BSD 3-Clause license,\r
- * the "License"; You may not use this file except in compliance with the\r
- * License. You may obtain a copy of the License at:\r
- * opensource.org/licenses/BSD-3-Clause\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup RCC RCC\r
- * @brief RCC HAL module driver\r
- * @{\r
- */\r
-\r
-#ifdef HAL_RCC_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/** @defgroup RCC_Private_Constants RCC Private Constants\r
- * @{\r
- */\r
-#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT\r
-#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */\r
-#define MSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */\r
-#if defined(RCC_CSR_LSIPREDIV)\r
-#define LSI_TIMEOUT_VALUE 17U /* 17 ms (16 ms starting time + 1) */\r
-#else\r
-#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */\r
-#endif /* RCC_CSR_LSIPREDIV */\r
-#define HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */\r
-#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */\r
-#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/** @defgroup RCC_Private_Macros RCC Private Macros\r
- * @{\r
- */\r
-#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()\r
-#define MCO1_GPIO_PORT GPIOA\r
-#define MCO1_PIN GPIO_PIN_8\r
-\r
-#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \\r
- (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__)))\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @defgroup RCC_Private_Functions RCC Private Functions\r
- * @{\r
- */\r
-static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange);\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-static uint32_t RCC_GetSysClockFreqFromPLLSource(void);\r
-#endif\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup RCC_Exported_Functions RCC Exported Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions\r
- * @brief Initialization and Configuration functions\r
- *\r
- @verbatim\r
- ===============================================================================\r
- ##### Initialization and de-initialization functions #####\r
- ===============================================================================\r
- [..]\r
- This section provides functions allowing to configure the internal and external oscillators\r
- (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1\r
- and APB2).\r
-\r
- [..] Internal/external clock and PLL configuration\r
- (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through\r
- the PLL as System clock source.\r
-\r
- (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.\r
- It can be used to generate the clock for the USB OTG FS (48 MHz).\r
- The number of flash wait states is automatically adjusted when MSI range is updated with\r
- HAL_RCC_OscConfig() and the MSI is used as System clock source.\r
-\r
- (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC\r
- clock source.\r
-\r
- (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or\r
- through the PLL as System clock source. Can be used also optionally as RTC clock source.\r
-\r
- (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.\r
-\r
- (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:\r
- (++) The first output is used to generate the high speed system clock (up to 80MHz).\r
- (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),\r
- the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).\r
- (++) The third output is used to generate an accurate clock to achieve\r
- high-quality audio performance on SAI interface.\r
-\r
- (+) PLLSAI1 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:\r
- (++) The first output is used to generate SAR ADC1 clock.\r
- (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),\r
- the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).\r
- (++) The Third output is used to generate an accurate clock to achieve\r
- high-quality audio performance on SAI interface.\r
-\r
- (+) PLLSAI2 (clocked by HSI, HSE or MSI) providing up to two independent output clocks:\r
- (++) The first output is used to generate SAR ADC2 clock.\r
- (++) The second output is used to generate an accurate clock to achieve\r
- high-quality audio performance on SAI interface.\r
-\r
- (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs\r
- (HSE used directly or through PLL as System clock source), the System clock\r
- is automatically switched to HSI and an interrupt is generated if enabled.\r
- The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)\r
- exception vector.\r
-\r
- (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or\r
- main PLL clock (through a configurable prescaler) on PA8 pin.\r
-\r
- [..] System, AHB and APB busses clocks configuration\r
- (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,\r
- HSE and main PLL.\r
- The AHB clock (HCLK) is derived from System clock through configurable\r
- prescaler and used to clock the CPU, memory and peripherals mapped\r
- on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived\r
- from AHB clock through configurable prescalers and used to clock\r
- the peripherals mapped on these busses. You can use\r
- "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.\r
-\r
- -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:\r
-\r
- (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLSAI1) or (PLLSAI2) or\r
- from an external clock mapped on the SAI_CKIN pin.\r
- You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock.\r
- (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock\r
- divided by 2 to 31.\r
- You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function\r
- to configure this clock.\r
- (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz\r
- to work correctly, while the SDMMC1 and RNG peripherals require a frequency\r
- equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1\r
- through PLLQ divider. You have to enable the peripheral clock and use\r
- HAL_RCCEx_PeriphCLKConfig() function to configure this clock.\r
- (+@) IWDG clock which is always the LSI clock.\r
-\r
-\r
- (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz.\r
- The clock source frequency should be adapted depending on the device voltage range\r
- as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.\r
-\r
- @endverbatim\r
-\r
- Table 1. HCLK clock frequency for STM32L4Rx/STM32L4Sx devices\r
- +--------------------------------------------------------+\r
- | Latency | HCLK clock frequency (MHz) |\r
- | |--------------------------------------|\r
- | | voltage range 1 | voltage range 2 |\r
- | | 1.2 V | 1.0 V |\r
- |-----------------|-------------------|------------------|\r
- |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 8 |\r
- |-----------------|-------------------|------------------|\r
- |1WS(2 CPU cycles)| 20 < HCLK <= 40 | 8 < HCLK <= 16 |\r
- |-----------------|-------------------|------------------|\r
- |2WS(3 CPU cycles)| 40 < HCLK <= 60 | 16 < HCLK <= 26 |\r
- |-----------------|-------------------|------------------|\r
- |3WS(4 CPU cycles)| 60 < HCLK <= 80 | 16 < HCLK <= 26 |\r
- |-----------------|-------------------|------------------|\r
- |4WS(5 CPU cycles)| 80 < HCLK <= 100 | 16 < HCLK <= 26 |\r
- |-----------------|-------------------|------------------|\r
- |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 |\r
- +--------------------------------------------------------+\r
-\r
- Table 2. HCLK clock frequency for other STM32L4 devices\r
- +-------------------------------------------------------+\r
- | Latency | HCLK clock frequency (MHz) |\r
- | |-------------------------------------|\r
- | | voltage range 1 | voltage range 2 |\r
- | | 1.2 V | 1.0 V |\r
- |-----------------|------------------|------------------|\r
- |0WS(1 CPU cycles)| 0 < HCLK <= 16 | 0 < HCLK <= 6 |\r
- |-----------------|------------------|------------------|\r
- |1WS(2 CPU cycles)| 16 < HCLK <= 32 | 6 < HCLK <= 12 |\r
- |-----------------|------------------|------------------|\r
- |2WS(3 CPU cycles)| 32 < HCLK <= 48 | 12 < HCLK <= 18 |\r
- |-----------------|------------------|------------------|\r
- |3WS(4 CPU cycles)| 48 < HCLK <= 64 | 18 < HCLK <= 26 |\r
- |-----------------|------------------|------------------|\r
- |4WS(5 CPU cycles)| 64 < HCLK <= 80 | 18 < HCLK <= 26 |\r
- +-------------------------------------------------------+\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Reset the RCC clock configuration to the default reset state.\r
- * @note The default reset state of the clock configuration is given below:\r
- * - MSI ON and used as system clock source\r
- * - HSE, HSI, PLL, PLLSAI1 and PLLSAI2 OFF\r
- * - AHB, APB1 and APB2 prescalers set to 1.\r
- * - CSS, MCO1 OFF\r
- * - All interrupts disabled\r
- * - All interrupt and reset flags cleared\r
- * @note This function does not modify the configuration of the\r
- * - Peripheral clock sources\r
- * - LSI, LSE and RTC clocks (Backup domain)\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_RCC_DeInit(void)\r
-{\r
- uint32_t tickstart;\r
-\r
- /* Reset to default System clock */\r
- /* Set MSION bit */\r
- SET_BIT(RCC->CR, RCC_CR_MSION);\r
-\r
- /* Insure MSIRDY bit is set before writing default MSIRANGE value */\r
- /* Get start tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till MSI is ready */\r
- while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
-\r
- /* Set MSIRANGE default value */\r
- MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6);\r
-\r
- /* Reset CFGR register (MSI is selected as system clock source) */\r
- CLEAR_REG(RCC->CFGR);\r
-\r
- /* Update the SystemCoreClock global variable for MSI as system clock source */\r
- SystemCoreClock = MSI_VALUE;\r
-\r
- /* Configure the source of time base considering new system clock settings */\r
- if(HAL_InitTick(uwTickPrio) != HAL_OK)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Insure MSI selected as system clock source */\r
- /* Get start tick */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till system clock source is ready */\r
- while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI)\r
- {\r
- if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
-\r
- /* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON, PLLSAIxON bits */\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON);\r
-\r
-#elif defined(RCC_PLLSAI1_SUPPORT)\r
-\r
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON);\r
-\r
-#else\r
-\r
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON);\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
- /* Insure PLLRDY, PLLSAI1RDY and PLLSAI2RDY (if present) are reset */\r
- /* Get start tick */\r
- tickstart = HAL_GetTick();\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
- while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U)\r
-\r
-#elif defined(RCC_PLLSAI1_SUPPORT)\r
-\r
- while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U)\r
-\r
-#else\r
-\r
- while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)\r
-\r
-#endif\r
- {\r
- if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
-\r
- /* Reset PLLCFGR register */\r
- CLEAR_REG(RCC->PLLCFGR);\r
- SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4 );\r
-\r
-#if defined(RCC_PLLSAI1_SUPPORT)\r
-\r
- /* Reset PLLSAI1CFGR register */\r
- CLEAR_REG(RCC->PLLSAI1CFGR);\r
- SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N_4 );\r
-\r
-#endif /* RCC_PLLSAI1_SUPPORT */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
-\r
- /* Reset PLLSAI2CFGR register */\r
- CLEAR_REG(RCC->PLLSAI2CFGR);\r
- SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N_4 );\r
-\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
- /* Reset HSEBYP bit */\r
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);\r
-\r
- /* Disable all interrupts */\r
- CLEAR_REG(RCC->CIER);\r
-\r
- /* Clear all interrupt flags */\r
- WRITE_REG(RCC->CICR, 0xFFFFFFFFU);\r
-\r
- /* Clear all reset flags */\r
- SET_BIT(RCC->CSR, RCC_CSR_RMVF);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initialize the RCC Oscillators according to the specified parameters in the\r
- * RCC_OscInitTypeDef.\r
- * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that\r
- * contains the configuration information for the RCC Oscillators.\r
- * @note The PLL is not disabled when used as system clock.\r
- * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\r
- * supported by this macro. User should request a transition to LSE Off\r
- * first and then LSE On or LSE Bypass.\r
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r
- * supported by this macro. User should request a transition to HSE Off\r
- * first and then HSE On or HSE Bypass.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)\r
-{\r
- uint32_t tickstart;\r
- HAL_StatusTypeDef status;\r
- uint32_t sysclk_source, pll_config;\r
-\r
- /* Check Null pointer */\r
- if(RCC_OscInitStruct == NULL)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));\r
-\r
- sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();\r
- pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();\r
-\r
- /*----------------------------- MSI Configuration --------------------------*/\r
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));\r
- assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));\r
- assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));\r
-\r
- /* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */\r
- if((sysclk_source == RCC_CFGR_SWS_MSI) ||\r
- ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))\r
- {\r
- if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Otherwise, just the calibration and MSI range change are allowed */\r
- else\r
- {\r
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY)\r
- must be correctly programmed according to the frequency of the CPU clock\r
- (HCLK) and the supply voltage of the device. */\r
- if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())\r
- {\r
- /* First increase number of wait states update if necessary */\r
- if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Selects the Multiple Speed oscillator (MSI) clock range .*/\r
- __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);\r
- /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/\r
- __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);\r
- }\r
- else\r
- {\r
- /* Else, keep current flash latency while decreasing applies */\r
- /* Selects the Multiple Speed oscillator (MSI) clock range .*/\r
- __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);\r
- /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/\r
- __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);\r
-\r
- /* Decrease number of wait states update if necessary */\r
- if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)\r
- {\r
- return HAL_ERROR;\r
- }\r
- }\r
-\r
- /* Update the SystemCoreClock global variable */\r
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);\r
-\r
- /* Configure the source of time base considering new system clocks settings*/\r
- status = HAL_InitTick(uwTickPrio);\r
- if(status != HAL_OK)\r
- {\r
- return status;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Check the MSI State */\r
- if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)\r
- {\r
- /* Enable the Internal High Speed oscillator (MSI). */\r
- __HAL_RCC_MSI_ENABLE();\r
-\r
- /* Get timeout */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till MSI is ready */\r
- while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- /* Selects the Multiple Speed oscillator (MSI) clock range .*/\r
- __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);\r
- /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/\r
- __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);\r
-\r
- }\r
- else\r
- {\r
- /* Disable the Internal High Speed oscillator (MSI). */\r
- __HAL_RCC_MSI_DISABLE();\r
-\r
- /* Get timeout */\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till MSI is ready */\r
- while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- }\r
- }\r
- /*------------------------------- HSE Configuration ------------------------*/\r
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));\r
-\r
- /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */\r
- if((sysclk_source == RCC_CFGR_SWS_HSE) ||\r
- ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))\r
- {\r
- if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))\r
- {\r
- return HAL_ERROR;\r
- }\r
- }\r
- else\r
- {\r
- /* Set the new HSE configuration ---------------------------------------*/\r
- __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);\r
-\r
- /* Check the HSE State */\r
- if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)\r
- {\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till HSE is ready */\r
- while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till HSE is disabled */\r
- while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- }\r
- }\r
- /*----------------------------- HSI Configuration --------------------------*/\r
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));\r
- assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));\r
-\r
- /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */\r
- if((sysclk_source == RCC_CFGR_SWS_HSI) ||\r
- ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))\r
- {\r
- /* When HSI is used as system clock it will not be disabled */\r
- if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))\r
- {\r
- return HAL_ERROR;\r
- }\r
- /* Otherwise, just the calibration is allowed */\r
- else\r
- {\r
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
- }\r
- }\r
- else\r
- {\r
- /* Check the HSI State */\r
- if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)\r
- {\r
- /* Enable the Internal High Speed oscillator (HSI). */\r
- __HAL_RCC_HSI_ENABLE();\r
-\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till HSI is ready */\r
- while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
-\r
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
- }\r
- else\r
- {\r
- /* Disable the Internal High Speed oscillator (HSI). */\r
- __HAL_RCC_HSI_DISABLE();\r
-\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till HSI is disabled */\r
- while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- }\r
- }\r
- /*------------------------------ LSI Configuration -------------------------*/\r
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));\r
-\r
- /* Check the LSI State */\r
- if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)\r
- {\r
-#if defined(RCC_CSR_LSIPREDIV)\r
- uint32_t csr_temp = RCC->CSR;\r
-\r
- /* Check LSI division factor */\r
- assert_param(IS_RCC_LSIDIV(RCC_OscInitStruct->LSIDiv));\r
-\r
- if (RCC_OscInitStruct->LSIDiv != (csr_temp & RCC_CSR_LSIPREDIV))\r
- {\r
- if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \\r
- ((csr_temp & RCC_CSR_LSION) != RCC_CSR_LSION))\r
- {\r
- /* If LSIRDY is set while LSION is not enabled,\r
- LSIPREDIV can't be updated */\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Turn off LSI before changing RCC_CSR_LSIPREDIV */\r
- if ((csr_temp & RCC_CSR_LSION) == RCC_CSR_LSION)\r
- {\r
- __HAL_RCC_LSI_DISABLE();\r
-\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till LSI is disabled */\r
- while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
-\r
- /* Set LSI division factor */\r
- MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);\r
- }\r
-#endif /* RCC_CSR_LSIPREDIV */\r
-\r
- /* Enable the Internal Low Speed oscillator (LSI). */\r
- __HAL_RCC_LSI_ENABLE();\r
-\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till LSI is ready */\r
- while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Disable the Internal Low Speed oscillator (LSI). */\r
- __HAL_RCC_LSI_DISABLE();\r
-\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till LSI is disabled */\r
- while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- }\r
- /*------------------------------ LSE Configuration -------------------------*/\r
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)\r
- {\r
- FlagStatus pwrclkchanged = RESET;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));\r
-\r
- /* Update LSE configuration in Backup Domain control register */\r
- /* Requires to enable write access to Backup Domain of necessary */\r
- if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))\r
- {\r
- __HAL_RCC_PWR_CLK_ENABLE();\r
- pwrclkchanged = SET;\r
- }\r
-\r
- if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))\r
- {\r
- /* Enable write access to Backup domain */\r
- SET_BIT(PWR->CR1, PWR_CR1_DBP);\r
-\r
- /* Wait for Backup domain Write protection disable */\r
- tickstart = HAL_GetTick();\r
-\r
- while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))\r
- {\r
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
-\r
- /* Set the new LSE configuration -----------------------------------------*/\r
-#if defined(RCC_BDCR_LSESYSDIS)\r
- if((RCC_OscInitStruct->LSEState & RCC_BDCR_LSEON) != 0U)\r
- {\r
- /* Set LSESYSDIS bit according to LSE propagation option (enabled or disabled) */\r
- MODIFY_REG(RCC->BDCR, RCC_BDCR_LSESYSDIS, (RCC_OscInitStruct->LSEState & RCC_BDCR_LSESYSDIS));\r
-\r
- if((RCC_OscInitStruct->LSEState & RCC_BDCR_LSEBYP) != 0U)\r
- {\r
- /* LSE oscillator bypass enable */\r
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);\r
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);\r
- }\r
- else\r
- {\r
- /* LSE oscillator enable */\r
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);\r
- }\r
- }\r
- else\r
- {\r
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);\r
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);\r
- }\r
-#else\r
- __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);\r
-#endif /* RCC_BDCR_LSESYSDIS */\r
-\r
- /* Check the LSE State */\r
- if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)\r
- {\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till LSE is ready */\r
- while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till LSE is disabled */\r
- while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
-\r
-#if defined(RCC_BDCR_LSESYSDIS)\r
- /* By default, stop disabling LSE propagation */\r
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);\r
-#endif /* RCC_BDCR_LSESYSDIS */\r
- }\r
-\r
- /* Restore clock configuration if changed */\r
- if(pwrclkchanged == SET)\r
- {\r
- __HAL_RCC_PWR_CLK_DISABLE();\r
- }\r
- }\r
-#if defined(RCC_HSI48_SUPPORT)\r
- /*------------------------------ HSI48 Configuration -----------------------*/\r
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));\r
-\r
- /* Check the LSI State */\r
- if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)\r
- {\r
- /* Enable the Internal Low Speed oscillator (HSI48). */\r
- __HAL_RCC_HSI48_ENABLE();\r
-\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till HSI48 is ready */\r
- while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Disable the Internal Low Speed oscillator (HSI48). */\r
- __HAL_RCC_HSI48_DISABLE();\r
-\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till HSI48 is disabled */\r
- while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- }\r
-#endif /* RCC_HSI48_SUPPORT */\r
- /*-------------------------------- PLL Configuration -----------------------*/\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));\r
-\r
- if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)\r
- {\r
- /* Check if the PLL is used as system clock or not */\r
- if(sysclk_source != RCC_CFGR_SWS_PLL)\r
- {\r
- if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)\r
- {\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));\r
- assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));\r
- assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));\r
-#if defined(RCC_PLLP_SUPPORT)\r
- assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));\r
-#endif /* RCC_PLLP_SUPPORT */\r
- assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));\r
- assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));\r
-\r
- /* Disable the main PLL. */\r
- __HAL_RCC_PLL_DISABLE();\r
-\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till PLL is ready */\r
- while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
-\r
- /* Configure the main PLL clock source, multiplication and division factors. */\r
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,\r
- RCC_OscInitStruct->PLL.PLLM,\r
- RCC_OscInitStruct->PLL.PLLN,\r
-#if defined(RCC_PLLP_SUPPORT)\r
- RCC_OscInitStruct->PLL.PLLP,\r
-#endif\r
- RCC_OscInitStruct->PLL.PLLQ,\r
- RCC_OscInitStruct->PLL.PLLR);\r
-\r
- /* Enable the main PLL. */\r
- __HAL_RCC_PLL_ENABLE();\r
-\r
- /* Enable PLL System Clock output. */\r
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);\r
-\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till PLL is ready */\r
- while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Disable the main PLL. */\r
- __HAL_RCC_PLL_DISABLE();\r
-\r
- /* Disable all PLL outputs to save power if no PLLs on */\r
-#if defined(RCC_PLLSAI1_SUPPORT) && defined(RCC_CR_PLLSAI2RDY)\r
- if(READ_BIT(RCC->CR, (RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY)) == 0U)\r
- {\r
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);\r
- }\r
-#elif defined(RCC_PLLSAI1_SUPPORT)\r
- if(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)\r
- {\r
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);\r
- }\r
-#else\r
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);\r
-#endif /* RCC_PLLSAI1_SUPPORT && RCC_CR_PLLSAI2RDY */\r
-\r
-#if defined(RCC_PLLSAI2_SUPPORT)\r
- __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);\r
-#elif defined(RCC_PLLSAI1_SUPPORT)\r
- __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK);\r
-#else\r
- __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK);\r
-#endif /* RCC_PLLSAI2_SUPPORT */\r
-\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Wait till PLL is disabled */\r
- while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)\r
- {\r
- if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Check if there is a request to disable the PLL used as System clock source */\r
- if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)\r
- {\r
- return HAL_ERROR;\r
- }\r
- else\r
- {\r
- pll_config = RCC->PLLCFGR;\r
- /* Do not return HAL_ERROR if request repeats the current configuration */\r
- if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||\r
- (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||\r
- (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||\r
-#if defined(RCC_PLLP_SUPPORT)\r
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
- (READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||\r
-#else\r
- (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||\r
-#endif\r
-#endif\r
- (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||\r
- (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))\r
- {\r
- return HAL_ERROR;\r
- }\r
- }\r
- }\r
- }\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initialize the CPU, AHB and APB busses clocks according to the specified\r
- * parameters in the RCC_ClkInitStruct.\r
- * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that\r
- * contains the configuration information for the RCC peripheral.\r
- * @param FLatency FLASH Latency\r
- * This parameter can be one of the following values:\r
- * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle\r
- * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle\r
- * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles\r
- * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles\r
- * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles\r
- @if STM32L4S9xx\r
- * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles\r
- * @arg FLASH_LATENCY_6 FLASH 6 Latency cycles\r
- * @arg FLASH_LATENCY_7 FLASH 7 Latency cycles\r
- * @arg FLASH_LATENCY_8 FLASH 8 Latency cycles\r
- * @arg FLASH_LATENCY_9 FLASH 9 Latency cycles\r
- * @arg FLASH_LATENCY_10 FLASH 10 Latency cycles\r
- * @arg FLASH_LATENCY_11 FLASH 11 Latency cycles\r
- * @arg FLASH_LATENCY_12 FLASH 12 Latency cycles\r
- * @arg FLASH_LATENCY_13 FLASH 13 Latency cycles\r
- * @arg FLASH_LATENCY_14 FLASH 14 Latency cycles\r
- * @arg FLASH_LATENCY_15 FLASH 15 Latency cycles\r
- @endif\r
- *\r
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency\r
- * and updated by HAL_RCC_GetHCLKFreq() function called within this function\r
- *\r
- * @note The MSI is used by default as system clock source after\r
- * startup from Reset, wake-up from STANDBY mode. After restart from Reset,\r
- * the MSI frequency is set to its default value 4 MHz.\r
- *\r
- * @note The HSI can be selected as system clock source after\r
- * from STOP modes or in case of failure of the HSE used directly or indirectly\r
- * as system clock (if the Clock Security System CSS is enabled).\r
- *\r
- * @note A switch from one clock source to another occurs only if the target\r
- * clock source is ready (clock stable after startup delay or PLL locked).\r
- * If a clock source which is not yet ready is selected, the switch will\r
- * occur when the clock source is ready.\r
- *\r
- * @note You can use HAL_RCC_GetClockConfig() function to know which clock is\r
- * currently used as system clock source.\r
- *\r
- * @note Depending on the device voltage range, the software has to set correctly\r
- * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency\r
- * (for more details refer to section above "Initialization/de-initialization functions")\r
- * @retval None\r
- */\r
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)\r
-{\r
- uint32_t tickstart;\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
- uint32_t hpre = RCC_SYSCLK_DIV1;\r
-#endif\r
- HAL_StatusTypeDef status;\r
-\r
- /* Check Null pointer */\r
- if(RCC_ClkInitStruct == NULL)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));\r
- assert_param(IS_FLASH_LATENCY(FLatency));\r
-\r
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY)\r
- must be correctly programmed according to the frequency of the CPU clock\r
- (HCLK) and the supply voltage of the device. */\r
-\r
- /* Increasing the number of wait states because of higher CPU frequency */\r
- if(FLatency > __HAL_FLASH_GET_LATENCY())\r
- {\r
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
- __HAL_FLASH_SET_LATENCY(FLatency);\r
-\r
- /* Check that the new number of wait states is taken into account to access the Flash\r
- memory by reading the FLASH_ACR register */\r
- if(__HAL_FLASH_GET_LATENCY() != FLatency)\r
- {\r
- return HAL_ERROR;\r
- }\r
- }\r
-\r
- /*------------------------- SYSCLK Configuration ---------------------------*/\r
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)\r
- {\r
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));\r
-\r
- /* PLL is selected as System Clock Source */\r
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r
- {\r
- /* Check the PLL ready flag */\r
- if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)\r
- {\r
- return HAL_ERROR;\r
- }\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
- /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */\r
- /* Compute target PLL output frequency */\r
- if(RCC_GetSysClockFreqFromPLLSource() > 80000000U)\r
- {\r
- if(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)\r
- {\r
- /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);\r
- hpre = RCC_SYSCLK_DIV2;\r
- }\r
- else if((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))\r
- {\r
- /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);\r
- hpre = RCC_SYSCLK_DIV2;\r
- }\r
- else\r
- {\r
- /* nothing to do */\r
- }\r
- }\r
-#endif\r
- }\r
- else\r
- {\r
- /* HSE is selected as System Clock Source */\r
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r
- {\r
- /* Check the HSE ready flag */\r
- if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)\r
- {\r
- return HAL_ERROR;\r
- }\r
- }\r
- /* MSI is selected as System Clock Source */\r
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)\r
- {\r
- /* Check the MSI ready flag */\r
- if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)\r
- {\r
- return HAL_ERROR;\r
- }\r
- }\r
- /* HSI is selected as System Clock Source */\r
- else\r
- {\r
- /* Check the HSI ready flag */\r
- if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)\r
- {\r
- return HAL_ERROR;\r
- }\r
- }\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
- /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */\r
- if(HAL_RCC_GetSysClockFreq() > 80000000U)\r
- {\r
- /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);\r
- hpre = RCC_SYSCLK_DIV2;\r
- }\r
-#endif\r
-\r
- }\r
-\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);\r
-\r
- /* Get Start Tick*/\r
- tickstart = HAL_GetTick();\r
-\r
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))\r
- {\r
- if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)\r
- {\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
-\r
- /*-------------------------- HCLK Configuration --------------------------*/\r
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)\r
- {\r
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);\r
- }\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
- else\r
- {\r
- /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */\r
- if(hpre == RCC_SYSCLK_DIV2)\r
- {\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);\r
- }\r
- }\r
-#endif\r
-\r
- /* Decreasing the number of wait states because of lower CPU frequency */\r
- if(FLatency < __HAL_FLASH_GET_LATENCY())\r
- {\r
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
- __HAL_FLASH_SET_LATENCY(FLatency);\r
-\r
- /* Check that the new number of wait states is taken into account to access the Flash\r
- memory by reading the FLASH_ACR register */\r
- if(__HAL_FLASH_GET_LATENCY() != FLatency)\r
- {\r
- return HAL_ERROR;\r
- }\r
- }\r
-\r
- /*-------------------------- PCLK1 Configuration ---------------------------*/\r
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\r
- {\r
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);\r
- }\r
-\r
- /*-------------------------- PCLK2 Configuration ---------------------------*/\r
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\r
- {\r
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));\r
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));\r
- }\r
-\r
- /* Update the SystemCoreClock global variable */\r
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);\r
-\r
- /* Configure the source of time base considering new system clocks settings*/\r
- status = HAL_InitTick(uwTickPrio);\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions\r
- * @brief RCC clocks control functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Peripheral Control functions #####\r
- ===============================================================================\r
- [..]\r
- This subsection provides a set of functions allowing to:\r
-\r
- (+) Ouput clock to MCO pin.\r
- (+) Retrieve current clock frequencies.\r
- (+) Enable the Clock Security System.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Select the clock source to output on MCO pin(PA8).\r
- * @note PA8 should be configured in alternate function mode.\r
- * @param RCC_MCOx specifies the output direction for the clock source.\r
- * For STM32L4xx family this parameter can have only one value:\r
- * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).\r
- * @param RCC_MCOSource specifies the clock source to output.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO\r
- * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee\r
- * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source\r
- * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source\r
- @if STM32L443xx\r
- * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48\r
- @endif\r
- * @param RCC_MCODiv specifies the MCO prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg @ref RCC_MCODIV_1 no division applied to MCO clock\r
- * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock\r
- * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock\r
- * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock\r
- * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock\r
- * @retval None\r
- */\r
-void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)\r
-{\r
- GPIO_InitTypeDef GPIO_InitStruct;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RCC_MCO(RCC_MCOx));\r
- assert_param(IS_RCC_MCODIV(RCC_MCODiv));\r
- assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));\r
-\r
- /* Prevent unused argument(s) compilation warning if no assert_param check */\r
- UNUSED(RCC_MCOx);\r
-\r
- /* MCO Clock Enable */\r
- __MCO1_CLK_ENABLE();\r
-\r
- /* Configue the MCO1 pin in alternate function mode */\r
- GPIO_InitStruct.Pin = MCO1_PIN;\r
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\r
- GPIO_InitStruct.Pull = GPIO_NOPULL;\r
- GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\r
- HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);\r
-\r
- /* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */\r
- MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv ));\r
-}\r
-\r
-/**\r
- * @brief Return the SYSCLK frequency.\r
- *\r
- * @note The system frequency computed by this function is not the real\r
- * frequency in the chip. It is calculated based on the predefined\r
- * constant and the selected clock source:\r
- * @note If SYSCLK source is MSI, function returns values based on MSI\r
- * Value as defined by the MSI range.\r
- * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)\r
- * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)\r
- * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),\r
- * HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.\r
- * @note (*) HSI_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value\r
- * 16 MHz) but the real value may vary depending on the variations\r
- * in voltage and temperature.\r
- * @note (**) HSE_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value\r
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
- * frequency of the crystal used. Otherwise, this function may\r
- * have wrong result.\r
- *\r
- * @note The result of this function could be not correct when using fractional\r
- * value for HSE crystal.\r
- *\r
- * @note This function can be used by the user application to compute the\r
- * baudrate for the communication peripherals or configure other parameters.\r
- *\r
- * @note Each time SYSCLK changes, this function must be called to update the\r
- * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.\r
- *\r
- *\r
- * @retval SYSCLK frequency\r
- */\r
-uint32_t HAL_RCC_GetSysClockFreq(void)\r
-{\r
- uint32_t msirange = 0U, sysclockfreq = 0U;\r
- uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */\r
- uint32_t sysclk_source, pll_oscsource;\r
-\r
- sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();\r
- pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();\r
-\r
- if((sysclk_source == RCC_CFGR_SWS_MSI) ||\r
- ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))\r
- {\r
- /* MSI or PLL with MSI source used as system clock source */\r
-\r
- /* Get SYSCLK source */\r
- if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)\r
- { /* MSISRANGE from RCC_CSR applies */\r
- msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;\r
- }\r
- else\r
- { /* MSIRANGE from RCC_CR applies */\r
- msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;\r
- }\r
- /*MSI frequency range in HZ*/\r
- msirange = MSIRangeTable[msirange];\r
-\r
- if(sysclk_source == RCC_CFGR_SWS_MSI)\r
- {\r
- /* MSI used as system clock source */\r
- sysclockfreq = msirange;\r
- }\r
- }\r
- else if(sysclk_source == RCC_CFGR_SWS_HSI)\r
- {\r
- /* HSI used as system clock source */\r
- sysclockfreq = HSI_VALUE;\r
- }\r
- else if(sysclk_source == RCC_CFGR_SWS_HSE)\r
- {\r
- /* HSE used as system clock source */\r
- sysclockfreq = HSE_VALUE;\r
- }\r
- else\r
- {\r
- /* unexpected case: sysclockfreq at 0 */\r
- }\r
-\r
- if(sysclk_source == RCC_CFGR_SWS_PLL)\r
- {\r
- /* PLL used as system clock source */\r
-\r
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM\r
- SYSCLK = PLL_VCO / PLLR\r
- */\r
- pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);\r
-\r
- switch (pllsource)\r
- {\r
- case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */\r
- pllvco = HSI_VALUE;\r
- break;\r
-\r
- case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */\r
- pllvco = HSE_VALUE;\r
- break;\r
-\r
- case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */\r
- default:\r
- pllvco = msirange;\r
- break;\r
- }\r
- pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;\r
- pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;\r
- pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;\r
- sysclockfreq = pllvco / pllr;\r
- }\r
-\r
- return sysclockfreq;\r
-}\r
-\r
-/**\r
- * @brief Return the HCLK frequency.\r
- * @note Each time HCLK changes, this function must be called to update the\r
- * right HCLK value. Otherwise, any configuration based on this function will be incorrect.\r
- *\r
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.\r
- * @retval HCLK frequency in Hz\r
- */\r
-uint32_t HAL_RCC_GetHCLKFreq(void)\r
-{\r
- return SystemCoreClock;\r
-}\r
-\r
-/**\r
- * @brief Return the PCLK1 frequency.\r
- * @note Each time PCLK1 changes, this function must be called to update the\r
- * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.\r
- * @retval PCLK1 frequency in Hz\r
- */\r
-uint32_t HAL_RCC_GetPCLK1Freq(void)\r
-{\r
- /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/\r
- return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));\r
-}\r
-\r
-/**\r
- * @brief Return the PCLK2 frequency.\r
- * @note Each time PCLK2 changes, this function must be called to update the\r
- * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.\r
- * @retval PCLK2 frequency in Hz\r
- */\r
-uint32_t HAL_RCC_GetPCLK2Freq(void)\r
-{\r
- /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/\r
- return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));\r
-}\r
-\r
-/**\r
- * @brief Configure the RCC_OscInitStruct according to the internal\r
- * RCC configuration registers.\r
- * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that\r
- * will be configured.\r
- * @retval None\r
- */\r
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)\r
-{\r
- /* Check the parameters */\r
- assert_param(RCC_OscInitStruct != (void *)NULL);\r
-\r
- /* Set all possible values for the Oscillator type parameter ---------------*/\r
-#if defined(RCC_HSI48_SUPPORT)\r
- RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \\r
- RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;\r
-#else\r
- RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \\r
- RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
- /* Get the HSE configuration -----------------------------------------------*/\r
- if(READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP)\r
- {\r
- RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;\r
- }\r
- else if(READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON)\r
- {\r
- RCC_OscInitStruct->HSEState = RCC_HSE_ON;\r
- }\r
- else\r
- {\r
- RCC_OscInitStruct->HSEState = RCC_HSE_OFF;\r
- }\r
-\r
- /* Get the MSI configuration -----------------------------------------------*/\r
- if(READ_BIT(RCC->CR, RCC_CR_MSION) == RCC_CR_MSION)\r
- {\r
- RCC_OscInitStruct->MSIState = RCC_MSI_ON;\r
- }\r
- else\r
- {\r
- RCC_OscInitStruct->MSIState = RCC_MSI_OFF;\r
- }\r
-\r
- RCC_OscInitStruct->MSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos;\r
- RCC_OscInitStruct->MSIClockRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE);\r
-\r
- /* Get the HSI configuration -----------------------------------------------*/\r
- if(READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION)\r
- {\r
- RCC_OscInitStruct->HSIState = RCC_HSI_ON;\r
- }\r
- else\r
- {\r
- RCC_OscInitStruct->HSIState = RCC_HSI_OFF;\r
- }\r
-\r
- RCC_OscInitStruct->HSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos;\r
-\r
- /* Get the LSE configuration -----------------------------------------------*/\r
- if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)\r
- {\r
-#if defined(RCC_BDCR_LSESYSDIS)\r
- if((RCC->BDCR & RCC_BDCR_LSESYSDIS) == RCC_BDCR_LSESYSDIS)\r
- {\r
- RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_RTC_ONLY;\r
- }\r
- else\r
-#endif /* RCC_BDCR_LSESYSDIS */\r
- {\r
- RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;\r
- }\r
- }\r
- else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON)\r
- {\r
-#if defined(RCC_BDCR_LSESYSDIS)\r
- if((RCC->BDCR & RCC_BDCR_LSESYSDIS) == RCC_BDCR_LSESYSDIS)\r
- {\r
- RCC_OscInitStruct->LSEState = RCC_LSE_ON_RTC_ONLY;\r
- }\r
- else\r
-#endif /* RCC_BDCR_LSESYSDIS */\r
- {\r
- RCC_OscInitStruct->LSEState = RCC_LSE_ON;\r
- }\r
- }\r
- else\r
- {\r
- RCC_OscInitStruct->LSEState = RCC_LSE_OFF;\r
- }\r
-\r
- /* Get the LSI configuration -----------------------------------------------*/\r
- if(READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION)\r
- {\r
- RCC_OscInitStruct->LSIState = RCC_LSI_ON;\r
- }\r
- else\r
- {\r
- RCC_OscInitStruct->LSIState = RCC_LSI_OFF;\r
- }\r
-#if defined(RCC_CSR_LSIPREDIV)\r
-\r
- /* Get the LSI configuration -----------------------------------------------*/\r
- if((RCC->CSR & RCC_CSR_LSIPREDIV) == RCC_CSR_LSIPREDIV)\r
- {\r
- RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV128;\r
- }\r
- else\r
- {\r
- RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV1;\r
- }\r
-#endif /* RCC_CSR_LSIPREDIV */\r
-\r
-#if defined(RCC_HSI48_SUPPORT)\r
- /* Get the HSI48 configuration ---------------------------------------------*/\r
- if(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)\r
- {\r
- RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;\r
- }\r
- else\r
- {\r
- RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;\r
- }\r
-#else\r
- RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;\r
-#endif /* RCC_HSI48_SUPPORT */\r
-\r
- /* Get the PLL configuration -----------------------------------------------*/\r
- if(READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON)\r
- {\r
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;\r
- }\r
- else\r
- {\r
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;\r
- }\r
- RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);\r
- RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;\r
- RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;\r
- RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);\r
- RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U);\r
-#if defined(RCC_PLLP_SUPPORT)\r
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\r
- RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;\r
-#else\r
- if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)\r
- {\r
- RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV17;\r
- }\r
- else\r
- {\r
- RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV7;\r
- }\r
-#endif /* RCC_PLLP_DIV_2_31_SUPPORT */\r
-#endif /* RCC_PLLP_SUPPORT */\r
-}\r
-\r
-/**\r
- * @brief Configure the RCC_ClkInitStruct according to the internal\r
- * RCC configuration registers.\r
- * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that\r
- * will be configured.\r
- * @param pFLatency Pointer on the Flash Latency.\r
- * @retval None\r
- */\r
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)\r
-{\r
- /* Check the parameters */\r
- assert_param(RCC_ClkInitStruct != (void *)NULL);\r
- assert_param(pFLatency != (void *)NULL);\r
-\r
- /* Set all possible values for the Clock type parameter --------------------*/\r
- RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;\r
-\r
- /* Get the SYSCLK configuration --------------------------------------------*/\r
- RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW);\r
-\r
- /* Get the HCLK configuration ----------------------------------------------*/\r
- RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE);\r
-\r
- /* Get the APB1 configuration ----------------------------------------------*/\r
- RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1);\r
-\r
- /* Get the APB2 configuration ----------------------------------------------*/\r
- RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U);\r
-\r
- /* Get the Flash Wait State (Latency) configuration ------------------------*/\r
- *pFLatency = __HAL_FLASH_GET_LATENCY();\r
-}\r
-\r
-/**\r
- * @brief Enable the Clock Security System.\r
- * @note If a failure is detected on the HSE oscillator clock, this oscillator\r
- * is automatically disabled and an interrupt is generated to inform the\r
- * software about the failure (Clock Security System Interrupt, CSSI),\r
- * allowing the MCU to perform rescue operations. The CSSI is linked to\r
- * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.\r
- * @note The Clock Security System can only be cleared by reset.\r
- * @retval None\r
- */\r
-void HAL_RCC_EnableCSS(void)\r
-{\r
- SET_BIT(RCC->CR, RCC_CR_CSSON) ;\r
-}\r
-\r
-/**\r
- * @brief Handle the RCC Clock Security System interrupt request.\r
- * @note This API should be called under the NMI_Handler().\r
- * @retval None\r
- */\r
-void HAL_RCC_NMI_IRQHandler(void)\r
-{\r
- /* Check RCC CSSF interrupt flag */\r
- if(__HAL_RCC_GET_IT(RCC_IT_CSS))\r
- {\r
- /* RCC Clock Security System interrupt user callback */\r
- HAL_RCC_CSSCallback();\r
-\r
- /* Clear RCC CSS pending bit */\r
- __HAL_RCC_CLEAR_IT(RCC_IT_CSS);\r
- }\r
-}\r
-\r
-/**\r
- * @brief RCC Clock Security System interrupt callback.\r
- * @retval none\r
- */\r
-__weak void HAL_RCC_CSSCallback(void)\r
-{\r
- /* NOTE : This function should not be modified, when the callback is needed,\r
- the HAL_RCC_CSSCallback should be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @addtogroup RCC_Private_Functions\r
- * @{\r
- */\r
-/**\r
- * @brief Update number of Flash wait states in line with MSI range and current\r
- voltage range.\r
- * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11\r
- * @retval HAL status\r
- */\r
-static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)\r
-{\r
- uint32_t vos;\r
- uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */\r
-\r
- if(__HAL_RCC_PWR_IS_CLK_ENABLED())\r
- {\r
- vos = HAL_PWREx_GetVoltageRange();\r
- }\r
- else\r
- {\r
- __HAL_RCC_PWR_CLK_ENABLE();\r
- vos = HAL_PWREx_GetVoltageRange();\r
- __HAL_RCC_PWR_CLK_DISABLE();\r
- }\r
-\r
- if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)\r
- {\r
- if(msirange > RCC_MSIRANGE_8)\r
- {\r
- /* MSI > 16Mhz */\r
- if(msirange > RCC_MSIRANGE_10)\r
- {\r
- /* MSI 48Mhz */\r
- latency = FLASH_LATENCY_2; /* 2WS */\r
- }\r
- else\r
- {\r
- /* MSI 24Mhz or 32Mhz */\r
- latency = FLASH_LATENCY_1; /* 1WS */\r
- }\r
- }\r
- /* else MSI <= 16Mhz default FLASH_LATENCY_0 0WS */\r
- }\r
- else\r
- {\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
- if(msirange >= RCC_MSIRANGE_8)\r
- {\r
- /* MSI >= 16Mhz */\r
- latency = FLASH_LATENCY_2; /* 2WS */\r
- }\r
- else\r
- {\r
- if(msirange == RCC_MSIRANGE_7)\r
- {\r
- /* MSI 8Mhz */\r
- latency = FLASH_LATENCY_1; /* 1WS */\r
- }\r
- /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */\r
- }\r
-#else\r
- if(msirange > RCC_MSIRANGE_8)\r
- {\r
- /* MSI > 16Mhz */\r
- latency = FLASH_LATENCY_3; /* 3WS */\r
- }\r
- else\r
- {\r
- if(msirange == RCC_MSIRANGE_8)\r
- {\r
- /* MSI 16Mhz */\r
- latency = FLASH_LATENCY_2; /* 2WS */\r
- }\r
- else if(msirange == RCC_MSIRANGE_7)\r
- {\r
- /* MSI 8Mhz */\r
- latency = FLASH_LATENCY_1; /* 1WS */\r
- }\r
- /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */\r
- }\r
-#endif\r
- }\r
-\r
- __HAL_FLASH_SET_LATENCY(latency);\r
-\r
- /* Check that the new number of wait states is taken into account to access the Flash\r
- memory by reading the FLASH_ACR register */\r
- if(__HAL_FLASH_GET_LATENCY() != latency)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- return HAL_OK;\r
-}\r
-\r
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
-/**\r
- * @brief Compute SYSCLK frequency based on PLL SYSCLK source.\r
- * @retval SYSCLK frequency\r
- */\r
-static uint32_t RCC_GetSysClockFreqFromPLLSource(void)\r
-{\r
- uint32_t msirange = 0U;\r
- uint32_t pllvco, pllsource, pllr, pllm, sysclockfreq; /* no init needed */\r
-\r
- if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI)\r
- {\r
- /* Get MSI range source */\r
- if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)\r
- { /* MSISRANGE from RCC_CSR applies */\r
- msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;\r
- }\r
- else\r
- { /* MSIRANGE from RCC_CR applies */\r
- msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;\r
- }\r
- /*MSI frequency range in HZ*/\r
- msirange = MSIRangeTable[msirange];\r
- }\r
-\r
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM\r
- SYSCLK = PLL_VCO / PLLR\r
- */\r
- pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);\r
-\r
- switch (pllsource)\r
- {\r
- case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */\r
- pllvco = HSI_VALUE;\r
- break;\r
-\r
- case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */\r
- pllvco = HSE_VALUE;\r
- break;\r
-\r
- case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */\r
- default:\r
- pllvco = msirange;\r
- break;\r
- }\r
- pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;\r
- pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;\r
- pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;\r
- sysclockfreq = pllvco / pllr;\r
-\r
- return sysclockfreq;\r
-}\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* HAL_RCC_MODULE_ENABLED */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / blobdiff