--- /dev/null
+/****************************************************************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only\r
+* intended for use with Renesas products. No other uses are authorized. This\r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+****************************************************************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* File Name : GNU_LINKER_ATCM.ld\r
+* Device(s) : RZ/T1 (R7S910018)\r
+* Tool-Chain : GNUARM-NONEv14.02-EABI\r
+* H/W Platform : RSK+RZT1 CPU Board\r
+* Description : Linker file for projects that require to load and run from RAM (ATCM)\r
+***********************************************************************************************************************/\r
+/***********************************************************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 21.05.2015 1.00\r
+***********************************************************************************************************************/\r
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")\r
+OUTPUT_ARCH(arm)\r
+ENTRY(start)\r
+\r
+/* Base Address RAM Memory Table 1 Mbyte on-chip RAM */\r
+MEMORY\r
+{\r
+ /* Internal RAM address range H'2000_0000 to H'2001_FFFF is configured as data retention RAM */\r
+ /* Write access to this address range has to be enabled by writing to registers SYSCR1 and SYSCR2 */\r
+ ATCM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 /* (512KB) H'00000000 to H'0007FFFF */\r
+ BTCM (rwx) : ORIGIN = 0x00800000, LENGTH = 0x00800000 /* (32KB) H'00800000 to H'00807FFF */\r
+ BUFFER_RAM (rwx) : ORIGIN = 0x20200000, LENGTH = 0x00100000 /* (1024KB) H'08000000 to H'0FFFFFFF */\r
+ DATA_RAM0 (rwx) : ORIGIN = 0x24000000, LENGTH = 0x00080000 /* (512KB) H'22000000 to H'2207FFFF */\r
+ DATA_RAM1 (rwx) : ORIGIN = 0x22000000, LENGTH = 0x00080000 /* (512KB) H'24000000 to H'2407FFFF */\r
+\r
+ SPIBSC (rw) : ORIGIN = 0x30000000, LENGTH = 0x04000000 /* attached to H'30000000 to H'33FFFFFF */\r
+ CS0 (rw) : ORIGIN = 0x40000000, LENGTH = 0x04000000 /* attached to H'40000000 to H'43FFFFFF */\r
+ CS1 (rw) : ORIGIN = 0x44000000, LENGTH = 0x04000000 /* attached to H'44000000 to H'47FFFFFF */\r
+ CS2 (rw) : ORIGIN = 0x48000000, LENGTH = 0x04000000 /* attached to H'40000000 to H'4CFFFFFF */\r
+ CS3 (rw) : ORIGIN = 0x4C000000, LENGTH = 0x04000000 /* attached to H'4C000000 to H'4FFFFFFF */\r
+ CS4 (rw) : ORIGIN = 0x50000000, LENGTH = 0x04000000 /* attached to H'50000000 to H'53FFFFFF */\r
+ CS5 (rw) : ORIGIN = 0x54000000, LENGTH = 0x04000000 /* attached to H'54000000 to H'57FFFFFF */\r
+\r
+ /* Mapped memory type */\r
+ SPI_ROM (rw) : ORIGIN = 0x30000000, LENGTH = 0x04000000\r
+ CS0_ROM (rw) : ORIGIN = 0x40000000, LENGTH = 0x04000000\r
+ CS1_ROM (rw) : ORIGIN = 0x44000000, LENGTH = 0x04000000\r
+ SDRAM0_EXT (rw) : ORIGIN = 0x48000000, LENGTH = 0x04000000\r
+ SDRAM1_EXT (rw) : ORIGIN = 0x4C000000, LENGTH = 0x04000000\r
+}\r
+\r
+SYS_STACK_SIZE = 0x200; /* Application stack size */\r
+SVC_STACK_SIZE = 0x200; /* SVC mode stack */\r
+IRQ_STACK_SIZE = 0x200; /* IRQ mode stack */\r
+FIQ_STACK_SIZE = 0x200; /* FRQ mode stack */\r
+UND_STACK_SIZE = 0x200; /* SVC mode stack */\r
+ABT_STACK_SIZE = 0x200; /* ABT mode stack */\r
+HEAP_STACK_SIZE = 0x1000; /* Heap stack size */\r
+\r
+ATCM_BASE = 0x00000000; /* User application located here */\r
+BTCM_BASE = 0x00800000; /* BTCM base address */\r
+\r
+USER_EXEC_BASE = 0x00000000; /* Application loads and runs from here */\r
+\r
+USER_RAM = 0x20000000; /* Application's RAM base */\r
+\r
+STACK_BASE = 0x00807800; /* Stacks located in BTCM */\r
+\r
+SDRAM0_BASE = 0x48000000; /* SDRAM1 is attached to CS2 space */\r
+SDRAM1_BASE = 0x4C000000; /* SDRAM1 is attached to CS3 space */\r
+\r
+SECTIONS\r
+{\r
+ .reset USER_EXEC_BASE :\r
+ {\r
+ reset_start = .;\r
+ execute = .;\r
+ _intvec_start = .;\r
+ *start.o (.text);\r
+ . = ALIGN(0x4);\r
+ _intvec_end = .;\r
+ end_reset = .;\r
+ } > ATCM\r
+\r
+ .text :\r
+ {\r
+ text_start = .;\r
+ *(.text)\r
+ *(.text.startup)\r
+ text_end = .;\r
+ } > ATCM\r
+\r
+ .rodata :\r
+ {\r
+ _rodata_start = .;\r
+ *(.rodata)\r
+ *(.rodata.*)\r
+ . = ALIGN(0x8);\r
+ _start_data_ROM = .;\r
+ *(.data)\r
+ *(.data.*)\r
+ _end_data_ROM = .;\r
+ *(.got.plt)\r
+ *(.got)\r
+ . = ALIGN(0x8);\r
+ _rodata_end = .;\r
+ PROVIDE(end = .);\r
+ } > ATCM\r
+\r
+ _ram_data_size = (_end_data_ROM - _start_data_ROM);\r
+\r
+ .data USER_RAM :\r
+ {\r
+ _data_start = .;\r
+ _start_data_RAM = .;\r
+ . += _ram_data_size;\r
+ _data_end = .;\r
+ }\r
+\r
+ .bss _data_end :\r
+ {\r
+ _bss = .;\r
+ PROVIDE(__bss_start__ = .);\r
+ *(.bss)\r
+ *(.bss.**)\r
+ *(COMMON)\r
+ . = ALIGN(0x4);\r
+ PROVIDE(__bss_end__ = .);\r
+ _ebss = .;\r
+ _end = .;\r
+ PROVIDE(end = .);\r
+ }\r
+\r
+ .heap :\r
+ {\r
+ heap_start = .;\r
+ . = ALIGN(0x8);\r
+ *(.heap_stack)\r
+ . += HEAP_STACK_SIZE;\r
+ heap_end = .;\r
+ } > ATCM\r
+\r
+ .sys_stack STACK_BASE :\r
+ {\r
+ sys_stack_start = .;\r
+ . = ALIGN(0x8);\r
+ *(.sys_stack)\r
+ . += SYS_STACK_SIZE;\r
+ sys_stack_end = .;\r
+ } > BTCM\r
+\r
+ .svc_stack sys_stack_end :\r
+ {\r
+ svc_stack_start = .;\r
+ . = ALIGN(0x8);\r
+ *(.svc_stack)\r
+ . += SVC_STACK_SIZE;\r
+ svc_stack_end = .;\r
+ } > BTCM\r
+\r
+ .irq_stack svc_stack_end :\r
+ {\r
+ irq_stack_start = .;\r
+ . = ALIGN(0x8);\r
+ *(.irq_stack)\r
+ . += IRQ_STACK_SIZE;\r
+ irq_stack_end = .;\r
+ } > BTCM\r
+\r
+ .fiq_stack irq_stack_end :\r
+ {\r
+ fiq_stack_start = .;\r
+ . = ALIGN(0x8);\r
+ *(.fiq_stack)\r
+ . += FIQ_STACK_SIZE;\r
+ fiq_stack_end = .;\r
+ } > BTCM\r
+\r
+ .und_stack fiq_stack_end :\r
+ {\r
+ und_stack_start = .;\r
+ . = ALIGN(0x8);\r
+ *(.und_stack)\r
+ . += UND_STACK_SIZE;\r
+ und_stack_end = .;\r
+ } > BTCM\r
+\r
+ .abt_stack und_stack_end :\r
+ {\r
+ abt_stack_start = .;\r
+ . = ALIGN(0x8);\r
+ *(.abt_stack)\r
+ . += ABT_STACK_SIZE;\r
+ abt_stack_end = .;\r
+ } > BTCM\r
+\r
+ /* NOLOAD directs linker NOT to fill VRAMx_SECTION with 0. */\r
+ /* Usage of NOLOAD increases speed of linker and download to target */\r
+ .sdram0_section SDRAM0_BASE (NOLOAD) : {} > SDRAM0_EXT\r
+ .sdram1_section SDRAM1_BASE (NOLOAD) : {} > SDRAM1_EXT\r
+}
\ No newline at end of file
projects / freertos / blobdiff