+++ /dev/null
-;*******************************************************************************\r
-; DISCLAIMER\r
-; This software is supplied by Renesas Electronics Corporation and is only\r
-; intended for use with Renesas products. No other uses are authorized. This\r
-; software is owned by Renesas Electronics Corporation and is protected under\r
-; all applicable laws, including copyright laws.\r
-; THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
-; THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
-; LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
-; AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
-; TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
-; ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
-; FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
-; ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
-; BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-; Renesas reserves the right, without notice, to make changes to this software\r
-; and to discontinue the availability of this software. By using this software,\r
-; you agree to the additional terms and conditions found by accessing the\r
-; following link:\r
-; http://www.renesas.com/disclaimer\r
-;\r
-; Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.\r
-;******************************************************************************\r
-;*******************************************************************************\r
-; System Name : RZ/T1 Init program\r
-; File Name : loader_init.asm\r
-; Version : 0.1\r
-; Device : R7S9100xx\r
-; Abstract : Loader program 1\r
-; Tool-Chain : IAR Embedded Workbench Ver.7.20\r
-; OS : not use\r
-; H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)\r
-; Description : Description interrupt service routine of RZ/T1\r
-; Limitation : none\r
-;******************************************************************************\r
-;*******************************************************************************\r
-; History : DD.MM.YYYY Version Description\r
-; : First Release\r
-;******************************************************************************\r
-\r
- SECTION IRQ_STACK:DATA:NOROOT(3)\r
- SECTION FIQ_STACK:DATA:NOROOT(3)\r
- SECTION SVC_STACK:DATA:NOROOT(3)\r
- SECTION ABT_STACK:DATA:NOROOT(3)\r
- SECTION UND_STACK:DATA:NOROOT(3)\r
- SECTION CSTACK:DATA:NOROOT(3)\r
- \r
- SECTION LDR_DATA_RBLOCK:DATA:ROOT(2)\r
- SECTION LDR_DATA_WBLOCK:DATA:ROOT(2)\r
-\r
- SECTION M3_PRG_RBLOCK:DATA:ROOT(2)\r
- SECTION M3_PRG_WBLOCK:DATA:ROOT(2)\r
-\r
-; This program is allocated to section "d_ldr_prg" \r
- SECTION d_ldr_prg:CODE:ROOT(2)\r
- \r
- ARM\r
- \r
- PUBLIC loader_init1\r
- PUBLIC set_low_vec\r
- PUBLIC cache_init\r
- PUBLIC mpu_init\r
- IMPORT loader_init2\r
-\r
- \r
-;***********************************************************************\r
-; Function Name : loader_init1\r
-; Description : Initialize sysytem by loader program\r
-; Arguments : none\r
-; Return Value : none\r
-;***********************************************************************\r
-loader_init1:\r
- \r
-stack_init:\r
- ; Stack setting \r
- cps #17 ; FIQ mode\r
- ldr sp, =SFE(FIQ_STACK)\r
- cps #18 ; IRQ mode\r
- ldr sp, =SFE(IRQ_STACK)\r
- cps #23 ; Abort mode\r
- ldr sp, =SFE(ABT_STACK)\r
- cps #27 ; Undef mode\r
- ldr sp, =SFE(UND_STACK)\r
- cps #31 ; System mode\r
- ldr sp, =SFE(CSTACK)\r
- cps #19 ; SVC mode\r
- ldr sp, =SFE(SVC_STACK)\r
- \r
-vfp_init: \r
- ; Initialize VFP setting\r
- mrc p15, #0, r0, c1, c0, #2 ; Enables cp10 and cp11 accessing\r
- orr r0, r0, #0xF00000\r
- mcr p15, #0, r0, c1, c0, #2\r
- isb ; Ensuring Context-changing\r
- \r
- mov r0, #0x40000000 ; Enables VFP operation\r
- vmsr fpexc, r0\r
- \r
-data_init: \r
- ; Initialize variables has initialized value of loader_init2.\r
- ; Variables has no initialized value already be initialized to zero \r
- ; in boot sequence(Clear ATCM and BTCM).\r
- ldr r0, =SFB(LDR_DATA_RBLOCK)\r
- ldr r1, =SFB(LDR_DATA_WBLOCK)\r
- ldr r2, =SIZEOF(LDR_DATA_WBLOCK)\r
- cmp r2, #0\r
-#ifdef DUAL_CORE\r
- beq m3_init\r
-#else\r
- beq jump_loader_init2\r
-#endif\r
- \r
-copy_to_LDR_DATA:\r
- ldrb r3, [r0], #1\r
- strb r3, [r1], #1\r
- subs r2, r2, #1\r
- bne copy_to_LDR_DATA \r
- dsb ; Ensuring data-changing\r
-\r
-#ifdef DUAL_CORE\r
-\r
-m3_init:\r
- ; Initialize image for Cortex-M3 core\r
- ldr r0, =SFB(M3_PRG_RBLOCK)\r
- ldr r1, =SFB(M3_PRG_WBLOCK)\r
- ldr r2, =SIZEOF(M3_PRG_WBLOCK)\r
- cmp r2, #0\r
- beq jump_loader_init2\r
- \r
-copy_to_M3_PRG:\r
- ldrb r3, [r0], #1\r
- strb r3, [r1], #1\r
- subs r2, r2, #1\r
- bne copy_to_M3_PRG \r
- dsb ; Ensuring data-changing\r
-\r
-#endif\r
-\r
- ; Jump to loader_init2\r
-jump_loader_init2:\r
- ldr r0, =loader_init2\r
- bx r0\r
-\r
-;***********************************************************************\r
-; Function Name : cache_init\r
-; Description : Initialize I1, D1 cache and MPU settings\r
-; Arguments : none\r
-; Return Value : none\r
-;***********************************************************************\r
-\r
-;*******************************************************************************\r
-; Macro definitions\r
-;*******************************************************************************\r
-\r
-SCTLR_BR: dcd 0x00020000\r
-SCTLR_M: dcd 0x00000001\r
-SCTLR_I_C: dcd 0x00001004\r
- \r
-DRBAR_REGION_0: dcd 0x04000000 ; Base address = 0400_0000h\r
-DRACR_REGION_0: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share\r
-DRSR_REGION_0: dcd 0x00000025 ; Size 512KB, MPU enable\r
-\r
-DRBAR_REGION_1: dcd 0x10000000 ; Base address = 1000_0000h \r
-DRACR_REGION_1: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share\r
-DRSR_REGION_1: dcd 0x00000033 ; Size 64MB, MPU enable \r
-\r
-DRBAR_REGION_2: dcd 0x20000000 ; Base address = 2000_0000h \r
-DRACR_REGION_2: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share\r
-DRSR_REGION_2: dcd 0x00000025 ; Size 512KB, MPU enable\r
-\r
-DRBAR_REGION_3: dcd 0x22000000 ; Base address = 2200_0000h \r
-DRACR_REGION_3: dcd 0x00000307 ; R/W(full), Normal, Write-back no allocate, share\r
-DRSR_REGION_3: dcd 0x00000033 ; Size 64MB, MPU enable \r
-\r
-DRBAR_REGION_4: dcd 0x30000000 ; Base address = 3000_0000h \r
-DRACR_REGION_4: dcd 0x0000030F ; R/W(full), Normal, Write-back write allocate, share \r
-DRSR_REGION_4: dcd 0x00000033 ; Size 64MB, MPU enable \r
-\r
-DRBAR_REGION_5: dcd 0x40000000 ; Base address = 4000_0000h \r
-DRACR_REGION_5: dcd 0x0000030F ; R/W(full), Normal, Write-back write allocate, share \r
-DRSR_REGION_5: dcd 0x00000035 ; Size 128MB, MPU enable \r
- \r
-DRBAR_REGION_6: dcd 0x48000000 ; Base address = 4800_0000h \r
-DRACR_REGION_6: dcd 0x0000030F ; R/W(full), Normal, Write-back write allocate, share \r
-DRSR_REGION_6: dcd 0x00000035 ; Size 128MB, MPU enable \r
-\r
-DRBAR_REGION_7: dcd 0x50000000 ; Base address = 5000_0000h \r
-DRACR_REGION_7: dcd 0x00001305 ; R/W(full), XN, Device, share \r
-DRSR_REGION_7: dcd 0x00000035 ; Size 128MB, MPU enable \r
-\r
-DRBAR_REGION_8: dcd 0x60000000 ; Base address = 6000_0000h\r
-DRACR_REGION_8: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share \r
-DRSR_REGION_8: dcd 0x00000035 ; Size 128MB, MPU enable \r
-\r
-DRBAR_REGION_9: dcd 0x68000000 ; Base address = 6800_0000h \r
-DRACR_REGION_9: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share \r
-DRSR_REGION_9: dcd 0x00000035 ; Size 128MB, MPU enable \r
- \r
-DRBAR_REGION_10: dcd 0x70000000 ; Base address = 7000_0000h \r
-DRACR_REGION_10: dcd 0x00001305 ; R/W(full), XN, Device, share \r
-DRSR_REGION_10: dcd 0x00000035 ; Size 128MB, MPU enable \r
-\r
-DRBAR_REGION_11: dcd 0x80000000 ; Base address = 8000_0000h \r
-DRACR_REGION_11: dcd 0x00001305 ; R/W(full), XN, Device, share \r
-DRSR_REGION_11: dcd 0x0000003D ; Size 2GB, MPU enable \r
-\r
-cache_init:\r
- push {lr}\r
-\r
-cache_invalidate:\r
- ; Invalidate the I1, D1 cache \r
- mov r0, #0\r
- mcr p15, #0, r0, c7, c5, #0 ; Invalidate all Instruction Caches (Write-value is Ignored)\r
- isb ; Ensuring Context-changing\r
- mcr p15, #0, r0, c15, c5, #0 ; Invalidate all Data Caches (Write-value is Ignored)\r
- isb ; Ensuring Context-changing\r
- \r
- ; Adopt default memory map as background map.\r
- ldr r0, SCTLR_BR ; Set SCTLR.BR bit to 1\r
- mrc p15, 0, r1, c1, c0, 0 \r
- orr r1, r1, r0\r
- dsb\r
- mcr p15, 0, r1, c1, c0, 0 \r
- isb ; Ensuring Context-changing\r
- \r
- ; Initialize MPU settings (region 0 to 11)\r
- ; Define region 0\r
- mov r0, #0\r
- ldr r1, DRBAR_REGION_0\r
- ldr r2, DRACR_REGION_0\r
- ldr r3, DRSR_REGION_0\r
- bl mpu_init\r
-\r
- ; Define region 1\r
- mov r0, #1\r
- ldr r1, DRBAR_REGION_1\r
- ldr r2, DRACR_REGION_1\r
- ldr r3, DRSR_REGION_1\r
- bl mpu_init\r
-\r
- ; Define region 2\r
- mov r0, #2\r
- ldr r1, DRBAR_REGION_2\r
- ldr r2, DRACR_REGION_2\r
- ldr r3, DRSR_REGION_2\r
- bl mpu_init\r
-\r
- ; Define region 3\r
- mov r0, #3\r
- ldr r1, DRBAR_REGION_3\r
- ldr r2, DRACR_REGION_3\r
- ldr r3, DRSR_REGION_3\r
- bl mpu_init\r
-\r
- ; Define region 4\r
- mov r0, #4\r
- ldr r1, DRBAR_REGION_4\r
- ldr r2, DRACR_REGION_4\r
- ldr r3, DRSR_REGION_4\r
- bl mpu_init\r
-\r
- ; Define region 5\r
- mov r0, #5\r
- ldr r1, DRBAR_REGION_5\r
- ldr r2, DRACR_REGION_5\r
- ldr r3, DRSR_REGION_5\r
- bl mpu_init\r
-\r
- ; Define region 6\r
- mov r0, #6\r
- ldr r1, DRBAR_REGION_6\r
- ldr r2, DRACR_REGION_6\r
- ldr r3, DRSR_REGION_6\r
- bl mpu_init\r
-\r
- ; Define region 7\r
- mov r0, #7\r
- ldr r1, DRBAR_REGION_7\r
- ldr r2, DRACR_REGION_7\r
- ldr r3, DRSR_REGION_7\r
- bl mpu_init\r
-\r
- ; Define region 8\r
- mov r0, #8\r
- ldr r1, DRBAR_REGION_8\r
- ldr r2, DRACR_REGION_8\r
- ldr r3, DRSR_REGION_8\r
- bl mpu_init\r
-\r
- ; Define region 9\r
- mov r0, #9\r
- ldr r1, DRBAR_REGION_9\r
- ldr r2, DRACR_REGION_9\r
- ldr r3, DRSR_REGION_9\r
- bl mpu_init\r
-\r
- ; Define region 10\r
- mov r0, #10\r
- ldr r1, DRBAR_REGION_10\r
- ldr r2, DRACR_REGION_10\r
- ldr r3, DRSR_REGION_10\r
- bl mpu_init\r
-\r
- ; Define region 11\r
- mov r0, #11\r
- ldr r1, DRBAR_REGION_11\r
- ldr r2, DRACR_REGION_11\r
- ldr r3, DRSR_REGION_11\r
- bl mpu_init\r
- \r
- ; Enables MPU operation\r
- ldr r0, SCTLR_M ; Set SCTLR.M bit to 1\r
- mrc p15, 0, r1, c1, c0, 0 \r
- orr r1, r1, r0\r
- dsb\r
- mcr p15, 0, r1, c1, c0, 0 \r
- isb ; Ensuring Context-changing\r
- \r
- ; Enables I1,D1 cache operation\r
- ldr r0, SCTLR_I_C ; Set SCTLR.I and C bit to 1\r
- mrc p15, 0, r1, c1, c0, 0 \r
- orr r1, r1, r0\r
- dsb\r
- mcr p15, 0, r1, c1, c0, 0 \r
- isb ; Ensuring Context-changing\r
-\r
- pop {pc}\r
- bx lr\r
-\r
-;***********************************************************************\r
-; Function Name : mpu_init\r
-; Description : Initialize MPU settings\r
-; Arguments : none\r
-; Return Value : none\r
-;***********************************************************************\r
-mpu_init:\r
- ; RGNR(MPU Memory Region Number Register)\r
- mcr p15, #0, r0, c6, c2, #0\r
- isb ; Ensuring Context-changing\r
- \r
- ; DRBAR(Data Region Base Address Register)\r
- mcr p15, #0, r1, c6, c1, #0\r
- isb ; Ensuring Context-changing\r
-\r
- ; DRACR(Data Region Access Control Register)\r
- mcr p15, #0, r2, c6, c1, #4\r
- isb ; Ensuring Context-changing\r
-\r
- ; DRSR(Data Region Size and Enable Register)\r
- mcr p15, #0, r3, c6, c1, #2\r
- isb ; Ensuring Context-changing\r
- \r
- bx lr\r
-\r
-\r
-;***********************************************************************\r
-; Function Name : set_low_vec\r
-; Description : Initialize sysytem by loader program\r
-; Arguments : none\r
-; Return Value : none\r
-;***********************************************************************\r
-set_low_vec:\r
- mrc p15, 0, r0, c1, c0, 0 ; Set SCTLR.V bit to 1 (low-vector)\r
- and r0, r0, #0xFFFFDFFF\r
- mcr p15, 0, r0, c1, c0, 0\r
- isb ; Ensuring Context-changing\r
- \r
- bx lr \r
-\r
- END \r
-; End of File \r
projects / freertos / blobdiff