]> git.sur5r.net Git - freertos/blobdiff - FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/IntQueueTimer.c
Baseline new GCC and Renesas compiler projects for RX71M and RX113 before adding...
[freertos] / FreeRTOS / Demo / CORTEX_R4F_RZ_T_GCC_IAR_ARM / src / Full_Demo / IntQueueTimer.c
index 4c443ca5e532bba6baaf0b521e6cf74e26d1cf8f..5aee68febc5d451a64f8011a4741868c9275c79a 100644 (file)
 #include "r_cg_cmt.h"\r
 #include "r_reset.h"\r
 \r
-#define tmrCMT_1_CHANNEL_0_HZ  ( 2000UL )\r
+#define tmrCMT_1_CHANNEL_0_HZ  ( 4000UL )\r
 #define tmrCMT_1_CHANNEL_1_HZ  ( 2011UL )\r
 \r
-/* Handlers for the two timers used.  See the documentation page\r
-for this port on http://www.FreeRTOS.org for more information on writing\r
-interrupt handlers. */\r
+/*\r
+ * Handlers for the two timers used.  See the documentation page\r
+ * for this port on TBD for more information on writing\r
+ * interrupt handlers.\r
+ */\r
 void vCMT_1_Channel_0_ISR( void );\r
 void vCMT_1_Channel_1_ISR( void );\r
 \r
+/*\r
+ * Entry point for the handlers.  These set the pxISRFunction variable to point\r
+ * to the C handler for each timer, then branch to the FreeRTOS IRQ handler.\r
+ */\r
+#ifdef __GNUC__\r
+       static void vCMT_1_Channel_0_ISR_Entry( void ) __attribute__((naked));\r
+       static void vCMT_1_Channel_1_ISR_Entry( void ) __attribute__((naked));\r
+#endif /* __GNUC__ */\r
+#ifdef __ICCARM__\r
+       /* IAR requires the entry point to be in an assembly file.  The functions\r
+       are     implemented in $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm. */\r
+       extern void vCMT_1_Channel_0_ISR_Entry( void );\r
+       extern void vCMT_1_Channel_1_ISR_Entry( void );\r
+#endif /* __ICCARM__ */\r
 /*-----------------------------------------------------------*/\r
 \r
 void vInitialiseTimerForIntQueueTest( void )\r
 {\r
 uint32_t ulCompareMatchValue;\r
 const uint32_t ulPeripheralClockDivider = 6UL, ulCMTClockDivider = 8UL;\r
-extern void FreeRTOS_IRQ_Handler( void );\r
 \r
        /* Disable CMI2 and CMI3 interrupts. */\r
        VIC.IEC0.LONG = ( 1UL << 23UL ) | ( 1UL << 24UL );\r
@@ -140,16 +155,15 @@ extern void FreeRTOS_IRQ_Handler( void );
        VIC.PLS0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL );\r
 \r
        /* Set CMI2 and CMI3 priority levels so they nest. */\r
-       VIC.PRL23.LONG = _CMT_PRIORITY_LEVEL10;\r
+       VIC.PRL23.LONG = _CMT_PRIORITY_LEVEL2;\r
        VIC.PRL24.LONG = _CMT_PRIORITY_LEVEL9;\r
 \r
        /* Set CMI2 and CMI3 interrupt address. */\r
-#warning Int 1 timer handler addresses not set.\r
-       VIC.VAD23.LONG = ( uint32_t ) NULL;\r
-       VIC.VAD24.LONG = ( uint32_t ) NULL;\r
+       VIC.VAD23.LONG = ( uint32_t ) vCMT_1_Channel_0_ISR_Entry;\r
+       VIC.VAD24.LONG = ( uint32_t ) vCMT_1_Channel_1_ISR_Entry;\r
 \r
     /* Enable CMI2 and CMI3 interrupts in ICU. */\r
-    VIC.IEN0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL );\r
+       VIC.IEN0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL );\r
 \r
     /* Start CMT1 channel 0 and 1 count. */\r
     CMT.CMSTR1.BIT.STR2 = 1U;\r
@@ -159,8 +173,8 @@ extern void FreeRTOS_IRQ_Handler( void );
 \r
 void vCMT_1_Channel_0_ISR( void )\r
 {\r
-       /* Re-enabled interrupts. */\r
-       taskENABLE_INTERRUPTS();\r
+       /* Clear the interrupt. */\r
+       VIC.PIC0.LONG = ( 1UL << 23UL );\r
 \r
        /* Call the handler that is part of the common code - this is where the\r
        non-portable code ends and the actual test is performed. */\r
@@ -170,8 +184,8 @@ void vCMT_1_Channel_0_ISR( void )
 \r
 void vCMT_1_Channel_1_ISR( void )\r
 {\r
-       /* Re-enabled interrupts. */\r
-       portENABLE_INTERRUPTS();\r
+       /* Clear the interrupt. */\r
+       VIC.PIC0.LONG = ( 1UL << 24UL );\r
 \r
        /* Call the handler that is part of the common code - this is where the\r
        non-portable code ends and the actual test is performed. */\r
@@ -179,6 +193,48 @@ void vCMT_1_Channel_1_ISR( void )
 }\r
 /*-----------------------------------------------------------*/\r
 \r
+/*\r
+ * The RZ/T vectors directly to a peripheral specific interrupt handler, rather\r
+ * than using the Cortex-R IRQ vector.  Therefore each interrupt handler\r
+ * installed by the application must follow the examples below, which save a\r
+ * pointer to a standard C function in the pxISRFunction variable, before\r
+ * branching to the FreeRTOS IRQ handler.  The FreeRTOS IRQ handler then manages\r
+ * interrupt entry (including interrupt nesting), before calling the C function\r
+ * saved in the pxISRFunction variable.  NOTE:  The entry points are naked\r
+ * functions - do not add C code to these functions.\r
+ */\r
+#ifdef __GNUC__\r
+       /* The IAR equivalent is implemented in\r
+       $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */\r
+       static void vCMT_1_Channel_0_ISR_Entry( void )\r
+       {\r
+               __asm volatile (                                                                                                                \\r
+                                                       "PUSH   {r0-r1}                                                         \t\n"   \\r
+                                                       "LDR    r0, =pxISRFunction                                      \t\n"   \\r
+                                                       "LDR    r1, =vCMT_1_Channel_0_ISR                       \t\n"   \\r
+                                                       "STR    r1, [r0]                                                        \t\n"   \\r
+                                                       "POP    {r0-r1}                                                         \t\n"   \\r
+                                                       "B              FreeRTOS_IRQ_Handler                                    "\r
+                                               );\r
+       }\r
+#endif /* __GNUC__ */\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __GNUC__\r
+       /* The IAR equivalent is implemented in\r
+       $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */\r
+       static void vCMT_1_Channel_1_ISR_Entry( void )\r
+       {\r
+               __asm volatile (                                                                                                                \\r
+                                                       "PUSH   {r0-r1}                                                         \t\n"   \\r
+                                                       "LDR    r0, =pxISRFunction                                      \t\n"   \\r
+                                                       "LDR    r1, =vCMT_1_Channel_1_ISR                       \t\n"   \\r
+                                                       "STR    r1, [r0]                                                        \t\n"   \\r
+                                                       "POP    {r0-r1}                                                         \t\n"   \\r
+                                                       "B              FreeRTOS_IRQ_Handler                                    "\r
+                                               );\r
+       }\r
+#endif /* __GNUC__ */\r
 \r
 \r
 \r