Initial RZ/T port and demo - work in progress, currently only the tick interrupt...

[freertos] / FreeRTOS / Demo / CORTEX_R4F_RZ_T_GCC_IAR_ARM / src / cg_src / r_cg_interrupthandlers.h

diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_interrupthandlers.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_interrupthandlers.h
new file mode 100644 (file)
index 0000000..625caf0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_interrupthandlers.h
@@ -0,0 +1,83 @@
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name    : r_cg_interrupthandlers.h\r
+* Version      : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]\r
+* Device(s)    : R7S910018CBG\r
+* Tool-Chain   : GCCARM\r
+* Description  : This file declares interrupt handlers.\r
+* Creation Date: 22/04/2015\r
+***********************************************************************************************************************/\r
+#ifndef INTERRUPT_HANDLERS_H\r
+#define INTERRUPT_HANDLERS_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+/* FIQ exception handler */\r
+void r_fiq_handler(void) __attribute__((interrupt ("FIQ")));\r
+\r
+/* ICU IRQ12 */\r
+void r_icu_irq12_interrupt(void) __attribute__((interrupt ("IRQ")));\r
+\r
+/* ADC Unit0 S12ADI0 */\r
+void r_s12ad_s12adi0_interrupt(void) __attribute__((interrupt ("IRQ")));\r
+\r
+/* RSPI1 SPTI1 */\r
+void r_rspi1_transmit_interrupt(void) __attribute__((interrupt ("IRQ")));\r
+\r
+/* RSPI1 SPEI1 */\r
+void r_rspi1_error_interrupt(void) __attribute__((interrupt ("IRQ")));\r
+\r
+/* RSPI1 SPII1 */\r
+void r_rspi1_idle_interrupt(void) __attribute__((interrupt ("IRQ")));\r
+\r
+/* SCIFA TXIF2 */\r
+void r_scifa2_txif2_interrupt(void) __attribute__((interrupt ("IRQ")));\r
+\r
+/* SCIFA DRIF2 */\r
+void r_scifa2_drif2_interrupt(void) __attribute__((interrupt ("IRQ")));\r
+\r
+/* SCIFA RXIF2 */\r
+void r_scifa2_rxif2_interrupt(void) __attribute__((interrupt ("IRQ")));\r
+\r
+/* SCIFA BRIF2 */\r
+void r_scifa2_brif2_interrupt(void) __attribute__((interrupt ("IRQ")));\r
+\r
+/* CMT CMI4 */\r
+void r_cmt_cmi4_interrupt(void) __attribute__((interrupt ("IRQ")));\r
+\r
+/* CMT CMI5 */\r
+void r_cmt_cmi5_interrupt(void) __attribute__((interrupt ("IRQ")));\r
+\r
+\r
+#endif
\ No newline at end of file