Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to...

[freertos] / FreeRTOS / Demo / CORTEX_R5_UltraScale_MPSoC / RTOSDemo_R5 / src / Full_Demo / main_full.c

diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c
index fb6114afc1129867b01c9aef3f5b6d3e7bb6d00e..bcd6d1ada43dcabf1d5cc2a1100d134f66326618 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c
@@ -496,6 +496,23 @@ void vFullDemoTickHook( void )
 \r
        /* Call the code that 'gives' a task notification from an ISR. */\r
        xNotifyTaskFromISR();\r
+\r
+       /* Test flop alignment in interrupts - calling printf from an interrupt\r
+       is BAD! */\r
+       #if( configASSERT_DEFINED == 1 )\r
+       {\r
+       char cBuf[ 20 ];\r
+       UBaseType_t uxSavedInterruptStatus;\r
+\r
+               uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
+               {\r
+                       sprintf( cBuf, "%1.3f", 1.234 );\r
+               }\r
+               portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+\r
+               configASSERT( strcmp( cBuf, "1.234" ) == 0 );\r
+       }\r
+       #endif /* configASSERT_DEFINED */\r
 }\r
 \r
 \r