Update Zynq, MPSoc Cortex-A53 and MPSoc Cortex-R5 demo projects to build with the...

[freertos] / FreeRTOS / Demo / CORTEX_R5_UltraScale_MPSoC / RTOSDemo_R5_bsp / psu_cortexr5_0 / include / xparameters.h

diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h
index efc88f158b6ed294e1b0a83e64aa4fc580c385a8..38c98f94048f72e6ced03ab83855c3c06a719549 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h
@@ -1,35 +1,34 @@
+#ifndef XPARAMETERS_H   /* prevent circular inclusions */\r
+#define XPARAMETERS_H   /* by using protection macros */\r
+\r
 /* Definition for CPU ID */\r
-#define XPAR_CPU_ID 0\r
+#define XPAR_CPU_ID 0U\r
 \r
 /* Definitions for peripheral PSU_CORTEXR5_0 */\r
-#define XPAR_PSU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499994995\r
+#define XPAR_PSU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499950000\r
 \r
 \r
 /******************************************************************/\r
 \r
 /* Canonical definitions for peripheral PSU_CORTEXR5_0 */\r
-#define XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499994995\r
+#define XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499950000\r
 \r
 \r
 /******************************************************************/\r
 \r
  /* Definition for PSS REF CLK FREQUENCY */\r
-#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33333000U\r
+#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33330000U\r
 \r
 #include "xparameters_ps.h"\r
 \r
-/******************************************************************/\r
-\r
-/*\r
- * Definitions of PSU_TTC_3 counter 0 base address and frequency used\r
- * by sleep and usleep APIs\r
- */\r
-\r
-#define SLEEP_TIMER_BASEADDR 0xFF140000\r
-#define SLEEP_TIMER_FREQUENCY 100000000\r
+#define XPS_BOARD_ZCU102\r
 \r
 /******************************************************************/\r
 \r
+ /*Definitions for peripheral PSU_R5_DDR_1 */\r
+#define XPAR_PSU_R5_DDR_1_S_AXI_BASEADDR 0x0\r
+#define XPAR_PSU_R5_DDR_1_S_AXI_HIGHADDR 0x7fffffff\r
+\r
 \r
 /* Number of Fabric Resets */\r
 #define XPAR_NUM_FABRIC_RESETS 1\r
@@ -37,192 +36,225 @@
 #define STDIN_BASEADDRESS 0xFF000000\r
 #define STDOUT_BASEADDRESS 0xFF000000\r
 \r
+/******************************************************************/\r
+\r
+/* Platform specific definitions */\r
+#define PLATFORM_ZYNQMP\r
+ \r
+/* Definitions for debug logic configuration in lockstep mode */\r
+#define LOCKSTEP_MODE_DEBUG 0U\r
+ \r
+/* Definitions for sleep timer configuration */\r
+#define SLEEP_TIMER_BASEADDR XPAR_PSU_TTC_9_BASEADDR\r
+#define SLEEP_TIMER_FREQUENCY XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ\r
+#define XSLEEP_TTC_INSTANCE 3\r
+#define XSLEEP_TIMER_IS_DEFAULT_TIMER\r
+ \r
+ \r
+/******************************************************************/\r
+/* Definitions for driver AVBUF */\r
+#define XPAR_XAVBUF_NUM_INSTANCES 1\r
+\r
+/* Definitions for peripheral PSU_DP */\r
+#define XPAR_PSU_DP_DEVICE_ID 0\r
+#define XPAR_PSU_DP_BASEADDR 0xFD4A0000\r
+#define XPAR_PSU_DP_HIGHADDR 0xFD4AFFFF\r
+\r
+\r
+/******************************************************************/\r
+\r
+/* Canonical definitions for peripheral PSU_DP */\r
+#define XPAR_XAVBUF_0_DEVICE_ID XPAR_PSU_DP_DEVICE_ID\r
+#define XPAR_XAVBUF_0_BASEADDR 0xFD4A0000\r
+#define XPAR_XAVBUF_0_HIGHADDR 0xFD4AFFFF\r
+\r
+\r
 /******************************************************************/\r
 \r
 /* Definitions for driver AXIPMON */\r
-#define XPAR_XAXIPMON_NUM_INSTANCES 4\r
+#define XPAR_XAXIPMON_NUM_INSTANCES 4U\r
 \r
 /* Definitions for peripheral PSU_APM_0 */\r
-#define XPAR_PSU_APM_0_DEVICE_ID 0\r
-#define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000\r
-#define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFF\r
-#define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32\r
-#define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32\r
-#define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1\r
-#define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6\r
-#define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10\r
-#define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1\r
-#define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0\r
-#define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32\r
-#define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56\r
-#define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1\r
-#define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1\r
-#define XPAR_PSU_APM_0_ENABLE_ADVANCED 1\r
-#define XPAR_PSU_APM_0_ENABLE_PROFILE 0\r
-#define XPAR_PSU_APM_0_ENABLE_TRACE 0\r
-#define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000\r
-#define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000\r
-#define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 1\r
+#define XPAR_PSU_APM_0_DEVICE_ID 0U\r
+#define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000U\r
+#define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFFU\r
+#define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32U\r
+#define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32U\r
+#define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1U\r
+#define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6U\r
+#define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10U\r
+#define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1U\r
+#define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0U\r
+#define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32U\r
+#define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56U\r
+#define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1U\r
+#define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1U\r
+#define XPAR_PSU_APM_0_ENABLE_ADVANCED 1U\r
+#define XPAR_PSU_APM_0_ENABLE_PROFILE 0U\r
+#define XPAR_PSU_APM_0_ENABLE_TRACE 0U\r
+#define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000U\r
+#define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000U\r
+#define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 1U\r
 \r
 \r
 /* Definitions for peripheral PSU_APM_1 */\r
-#define XPAR_PSU_APM_1_DEVICE_ID 1\r
-#define XPAR_PSU_APM_1_BASEADDR 0xFFA00000\r
-#define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFF\r
-#define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32\r
-#define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32\r
-#define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1\r
-#define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1\r
-#define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3\r
-#define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1\r
-#define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0\r
-#define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32\r
-#define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56\r
-#define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1\r
-#define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1\r
-#define XPAR_PSU_APM_1_ENABLE_ADVANCED 1\r
-#define XPAR_PSU_APM_1_ENABLE_PROFILE 0\r
-#define XPAR_PSU_APM_1_ENABLE_TRACE 0\r
-#define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000\r
-#define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000\r
-#define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 1\r
+#define XPAR_PSU_APM_1_DEVICE_ID 1U\r
+#define XPAR_PSU_APM_1_BASEADDR 0xFFA00000U\r
+#define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFFU\r
+#define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32U\r
+#define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32U\r
+#define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1U\r
+#define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1U\r
+#define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3U\r
+#define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1U\r
+#define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0U\r
+#define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32U\r
+#define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56U\r
+#define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1U\r
+#define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1U\r
+#define XPAR_PSU_APM_1_ENABLE_ADVANCED 1U\r
+#define XPAR_PSU_APM_1_ENABLE_PROFILE 0U\r
+#define XPAR_PSU_APM_1_ENABLE_TRACE 0U\r
+#define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000U\r
+#define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000U\r
+#define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 1U\r
 \r
 \r
 /* Definitions for peripheral PSU_APM_2 */\r
-#define XPAR_PSU_APM_2_DEVICE_ID 2\r
-#define XPAR_PSU_APM_2_BASEADDR 0xFFA10000\r
-#define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFF\r
-#define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32\r
-#define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32\r
-#define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1\r
-#define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1\r
-#define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3\r
-#define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1\r
-#define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0\r
-#define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32\r
-#define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56\r
-#define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1\r
-#define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1\r
-#define XPAR_PSU_APM_2_ENABLE_ADVANCED 1\r
-#define XPAR_PSU_APM_2_ENABLE_PROFILE 0\r
-#define XPAR_PSU_APM_2_ENABLE_TRACE 0\r
-#define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000\r
-#define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000\r
-#define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 1\r
+#define XPAR_PSU_APM_2_DEVICE_ID 2U\r
+#define XPAR_PSU_APM_2_BASEADDR 0xFFA10000U\r
+#define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFFU\r
+#define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32U\r
+#define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32U\r
+#define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1U\r
+#define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1U\r
+#define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3U\r
+#define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1U\r
+#define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0U\r
+#define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32U\r
+#define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56U\r
+#define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1U\r
+#define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1U\r
+#define XPAR_PSU_APM_2_ENABLE_ADVANCED 1U\r
+#define XPAR_PSU_APM_2_ENABLE_PROFILE 0U\r
+#define XPAR_PSU_APM_2_ENABLE_TRACE 0U\r
+#define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000U\r
+#define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000U\r
+#define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 1U\r
 \r
 \r
 /* Definitions for peripheral PSU_APM_5 */\r
-#define XPAR_PSU_APM_5_DEVICE_ID 3\r
-#define XPAR_PSU_APM_5_BASEADDR 0xFD490000\r
-#define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFF\r
-#define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32\r
-#define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32\r
-#define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1\r
-#define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1\r
-#define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3\r
-#define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1\r
-#define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0\r
-#define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32\r
-#define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56\r
-#define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1\r
-#define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1\r
-#define XPAR_PSU_APM_5_ENABLE_ADVANCED 1\r
-#define XPAR_PSU_APM_5_ENABLE_PROFILE 0\r
-#define XPAR_PSU_APM_5_ENABLE_TRACE 0\r
-#define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000\r
-#define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000\r
-#define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 1\r
+#define XPAR_PSU_APM_5_DEVICE_ID 3U\r
+#define XPAR_PSU_APM_5_BASEADDR 0xFD490000U\r
+#define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFFU\r
+#define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32U\r
+#define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32U\r
+#define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1U\r
+#define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1U\r
+#define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3U\r
+#define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1U\r
+#define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0U\r
+#define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32U\r
+#define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56U\r
+#define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1U\r
+#define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1U\r
+#define XPAR_PSU_APM_5_ENABLE_ADVANCED 1U\r
+#define XPAR_PSU_APM_5_ENABLE_PROFILE 0U\r
+#define XPAR_PSU_APM_5_ENABLE_TRACE 0U\r
+#define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000U\r
+#define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000U\r
+#define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 1U\r
 \r
 \r
 /******************************************************************/\r
 \r
 /* Canonical definitions for peripheral PSU_APM_0 */\r
 #define XPAR_AXIPMON_0_DEVICE_ID XPAR_PSU_APM_0_DEVICE_ID\r
-#define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000\r
-#define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFF\r
-#define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32\r
-#define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32\r
-#define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1\r
-#define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6\r
-#define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10\r
-#define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1\r
-#define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0\r
-#define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32\r
-#define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56\r
-#define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1\r
-#define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1\r
-#define XPAR_AXIPMON_0_ENABLE_ADVANCED 1\r
-#define XPAR_AXIPMON_0_ENABLE_PROFILE 0\r
-#define XPAR_AXIPMON_0_ENABLE_TRACE 0\r
-#define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000\r
-#define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000\r
-#define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 1\r
+#define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000U\r
+#define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFFU\r
+#define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32U\r
+#define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32U\r
+#define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1U\r
+#define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6U\r
+#define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10U\r
+#define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1U\r
+#define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0U\r
+#define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32U\r
+#define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56U\r
+#define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1U\r
+#define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1U\r
+#define XPAR_AXIPMON_0_ENABLE_ADVANCED 1U\r
+#define XPAR_AXIPMON_0_ENABLE_PROFILE 0U\r
+#define XPAR_AXIPMON_0_ENABLE_TRACE 0U\r
+#define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000U\r
+#define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000U\r
+#define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 1U\r
 \r
 /* Canonical definitions for peripheral PSU_APM_1 */\r
 #define XPAR_AXIPMON_1_DEVICE_ID XPAR_PSU_APM_1_DEVICE_ID\r
-#define XPAR_AXIPMON_1_BASEADDR 0xFFA00000\r
-#define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFF\r
-#define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32\r
-#define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32\r
-#define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1\r
-#define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1\r
-#define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3\r
-#define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1\r
-#define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0\r
-#define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32\r
-#define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56\r
-#define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1\r
-#define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1\r
-#define XPAR_AXIPMON_1_ENABLE_ADVANCED 1\r
-#define XPAR_AXIPMON_1_ENABLE_PROFILE 0\r
-#define XPAR_AXIPMON_1_ENABLE_TRACE 0\r
-#define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000\r
-#define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000\r
-#define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 1\r
+#define XPAR_AXIPMON_1_BASEADDR 0xFFA00000U\r
+#define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFFU\r
+#define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32U\r
+#define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32U\r
+#define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1U\r
+#define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1U\r
+#define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3U\r
+#define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1U\r
+#define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0U\r
+#define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32U\r
+#define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56U\r
+#define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1U\r
+#define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1U\r
+#define XPAR_AXIPMON_1_ENABLE_ADVANCED 1U\r
+#define XPAR_AXIPMON_1_ENABLE_PROFILE 0U\r
+#define XPAR_AXIPMON_1_ENABLE_TRACE 0U\r
+#define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000U\r
+#define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000U\r
+#define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 1U\r
 \r
 /* Canonical definitions for peripheral PSU_APM_2 */\r
 #define XPAR_AXIPMON_2_DEVICE_ID XPAR_PSU_APM_2_DEVICE_ID\r
-#define XPAR_AXIPMON_2_BASEADDR 0xFFA10000\r
-#define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFF\r
-#define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32\r
-#define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32\r
-#define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1\r
-#define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1\r
-#define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3\r
-#define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1\r
-#define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0\r
-#define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32\r
-#define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56\r
-#define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1\r
-#define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1\r
-#define XPAR_AXIPMON_2_ENABLE_ADVANCED 1\r
-#define XPAR_AXIPMON_2_ENABLE_PROFILE 0\r
-#define XPAR_AXIPMON_2_ENABLE_TRACE 0\r
-#define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000\r
-#define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000\r
-#define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 1\r
+#define XPAR_AXIPMON_2_BASEADDR 0xFFA10000U\r
+#define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFFU\r
+#define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32U\r
+#define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32U\r
+#define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1U\r
+#define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1U\r
+#define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3U\r
+#define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1U\r
+#define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0U\r
+#define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32U\r
+#define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56U\r
+#define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1U\r
+#define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1U\r
+#define XPAR_AXIPMON_2_ENABLE_ADVANCED 1U\r
+#define XPAR_AXIPMON_2_ENABLE_PROFILE 0U\r
+#define XPAR_AXIPMON_2_ENABLE_TRACE 0U\r
+#define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000U\r
+#define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000U\r
+#define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 1U\r
 \r
 /* Canonical definitions for peripheral PSU_APM_5 */\r
 #define XPAR_AXIPMON_3_DEVICE_ID XPAR_PSU_APM_5_DEVICE_ID\r
-#define XPAR_AXIPMON_3_BASEADDR 0xFD490000\r
-#define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFF\r
-#define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32\r
-#define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32\r
-#define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1\r
-#define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1\r
-#define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3\r
-#define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1\r
-#define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0\r
-#define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32\r
-#define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56\r
-#define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1\r
-#define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1\r
-#define XPAR_AXIPMON_3_ENABLE_ADVANCED 1\r
-#define XPAR_AXIPMON_3_ENABLE_PROFILE 0\r
-#define XPAR_AXIPMON_3_ENABLE_TRACE 0\r
-#define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000\r
-#define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000\r
-#define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 1\r
+#define XPAR_AXIPMON_3_BASEADDR 0xFD490000U\r
+#define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFFU\r
+#define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32U\r
+#define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32U\r
+#define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1U\r
+#define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1U\r
+#define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3U\r
+#define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1U\r
+#define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0U\r
+#define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32U\r
+#define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56U\r
+#define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1U\r
+#define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1U\r
+#define XPAR_AXIPMON_3_ENABLE_ADVANCED 1U\r
+#define XPAR_AXIPMON_3_ENABLE_PROFILE 0U\r
+#define XPAR_AXIPMON_3_ENABLE_TRACE 0U\r
+#define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000U\r
+#define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000U\r
+#define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 1U\r
 \r
 \r
 /******************************************************************/\r
@@ -234,7 +266,7 @@
 #define XPAR_PSU_CAN_1_DEVICE_ID 0\r
 #define XPAR_PSU_CAN_1_BASEADDR 0xFF070000\r
 #define XPAR_PSU_CAN_1_HIGHADDR 0xFF07FFFF\r
-#define XPAR_PSU_CAN_1_CAN_CLK_FREQ_HZ 99998999\r
+#define XPAR_PSU_CAN_1_CAN_CLK_FREQ_HZ 99990000\r
 \r
 \r
 /******************************************************************/\r
@@ -243,7 +275,7 @@
 #define XPAR_XCANPS_0_DEVICE_ID XPAR_PSU_CAN_1_DEVICE_ID\r
 #define XPAR_XCANPS_0_BASEADDR 0xFF070000\r
 #define XPAR_XCANPS_0_HIGHADDR 0xFF07FFFF\r
-#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 99998999\r
+#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 99990000\r
 \r
 \r
 /******************************************************************/\r
@@ -277,7 +309,7 @@
 #define XPAR_PSU_DDRC_0_BASEADDR 0xFD070000\r
 #define XPAR_PSU_DDRC_0_HIGHADDR 0xFD070FFF\r
 #define XPAR_PSU_DDRC_0_HAS_ECC 0\r
-#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 533328002\r
+#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 533280000\r
 \r
 \r
 /******************************************************************/\r
@@ -286,7 +318,26 @@
 #define XPAR_DDRCPSU_0_DEVICE_ID XPAR_PSU_DDRC_0_DEVICE_ID\r
 #define XPAR_DDRCPSU_0_BASEADDR 0xFD070000\r
 #define XPAR_DDRCPSU_0_HIGHADDR 0xFD070FFF\r
-#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 533328002\r
+#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 533280000\r
+\r
+\r
+/******************************************************************/\r
+\r
+/* Definitions for driver DPDMA */\r
+#define XPAR_XDPDMA_NUM_INSTANCES 1\r
+\r
+/* Definitions for peripheral PSU_DPDMA */\r
+#define XPAR_PSU_DPDMA_DEVICE_ID 0\r
+#define XPAR_PSU_DPDMA_BASEADDR 0xFD4C0000\r
+#define XPAR_PSU_DPDMA_HIGHADDR 0xFD4CFFFF\r
+\r
+\r
+/******************************************************************/\r
+\r
+/* Canonical definitions for peripheral PSU_DPDMA */\r
+#define XPAR_XDPDMA_0_DEVICE_ID XPAR_PSU_DPDMA_DEVICE_ID\r
+#define XPAR_XDPDMA_0_BASEADDR 0xFD4C0000\r
+#define XPAR_XDPDMA_0_HIGHADDR 0xFD4CFFFF\r
 \r
 \r
 /******************************************************************/\r
@@ -298,28 +349,31 @@
 #define XPAR_PSU_ETHERNET_3_DEVICE_ID 0\r
 #define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000\r
 #define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF\r
-#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749\r
+#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124987500\r
 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12\r
 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1\r
 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60\r
 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1\r
 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60\r
 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10\r
+#define XPAR_PSU_ETHERNET_3_ENET_TSU_CLK_FREQ_HZ 249975000\r
 \r
 \r
 /******************************************************************/\r
 \r
+#define XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT 0\r
 /* Canonical definitions for peripheral PSU_ETHERNET_3 */\r
 #define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID\r
 #define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000\r
 #define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF\r
-#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749\r
+#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124987500\r
 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12\r
 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1\r
 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60\r
 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1\r
 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60\r
 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10\r
+#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 249975000\r
 \r
 \r
 /******************************************************************/\r
@@ -375,19 +429,14 @@
 #define XPAR_PSU_CCI_REG_S_AXI_HIGHADDR 0xFD5EFFFF\r
 \r
 \r
-/* Definitions for peripheral PSU_CRF_APB */\r
-#define XPAR_PSU_CRF_APB_S_AXI_BASEADDR 0xFD1A0000\r
-#define XPAR_PSU_CRF_APB_S_AXI_HIGHADDR 0xFD2DFFFF\r
-\r
-\r
 /* Definitions for peripheral PSU_CRL_APB */\r
 #define XPAR_PSU_CRL_APB_S_AXI_BASEADDR 0xFF5E0000\r
 #define XPAR_PSU_CRL_APB_S_AXI_HIGHADDR 0xFF85FFFF\r
 \r
 \r
-/* Definitions for peripheral PSU_CSU_0 */\r
-#define XPAR_PSU_CSU_0_S_AXI_BASEADDR 0xFFCA0000\r
-#define XPAR_PSU_CSU_0_S_AXI_HIGHADDR 0xFFCAFFFF\r
+/* Definitions for peripheral PSU_CTRL_IPI */\r
+#define XPAR_PSU_CTRL_IPI_S_AXI_BASEADDR 0xFF380000\r
+#define XPAR_PSU_CTRL_IPI_S_AXI_HIGHADDR 0xFF3FFFFF\r
 \r
 \r
 /* Definitions for peripheral PSU_DDR_PHY */\r
@@ -430,16 +479,6 @@
 #define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF\r
 \r
 \r
-/* Definitions for peripheral PSU_DP */\r
-#define XPAR_PSU_DP_S_AXI_BASEADDR 0xFD4A0000\r
-#define XPAR_PSU_DP_S_AXI_HIGHADDR 0xFD4AFFFF\r
-\r
-\r
-/* Definitions for peripheral PSU_DPDMA */\r
-#define XPAR_PSU_DPDMA_S_AXI_BASEADDR 0xFD4C0000\r
-#define XPAR_PSU_DPDMA_S_AXI_HIGHADDR 0xFD4CFFFF\r
-\r
-\r
 /* Definitions for peripheral PSU_EFUSE */\r
 #define XPAR_PSU_EFUSE_S_AXI_BASEADDR 0xFFCC0000\r
 #define XPAR_PSU_EFUSE_S_AXI_HIGHADDR 0xFFCCFFFF\r
@@ -520,6 +559,11 @@
 #define XPAR_PSU_MBISTJTAG_S_AXI_HIGHADDR 0xFFCFFFFF\r
 \r
 \r
+/* Definitions for peripheral PSU_MESSAGE_BUFFERS */\r
+#define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_BASEADDR 0xFF990000\r
+#define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_HIGHADDR 0xFF99FFFF\r
+\r
+\r
 /* Definitions for peripheral PSU_OCM */\r
 #define XPAR_PSU_OCM_S_AXI_BASEADDR 0xFF960000\r
 #define XPAR_PSU_OCM_S_AXI_HIGHADDR 0xFF96FFFF\r
@@ -527,7 +571,7 @@
 \r
 /* Definitions for peripheral PSU_OCM_RAM_0 */\r
 #define XPAR_PSU_OCM_RAM_0_S_AXI_BASEADDR 0xFFFC0000\r
-#define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFEFFFF\r
+#define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFFFFFF\r
 \r
 \r
 /* Definitions for peripheral PSU_OCM_XMPU_CFG */\r
@@ -550,6 +594,16 @@
 #define XPAR_PSU_PCIE_DMA_S_AXI_HIGHADDR 0xFD0FFFFF\r
 \r
 \r
+/* Definitions for peripheral PSU_PCIE_HIGH1 */\r
+#define XPAR_PSU_PCIE_HIGH1_S_AXI_BASEADDR 0x600000000\r
+#define XPAR_PSU_PCIE_HIGH1_S_AXI_HIGHADDR 0x7FFFFFFFF\r
+\r
+\r
+/* Definitions for peripheral PSU_PCIE_HIGH2 */\r
+#define XPAR_PSU_PCIE_HIGH2_S_AXI_BASEADDR 0x8000000000\r
+#define XPAR_PSU_PCIE_HIGH2_S_AXI_HIGHADDR 0xBFFFFFFFFF\r
+\r
+\r
 /* Definitions for peripheral PSU_PCIE_LOW */\r
 #define XPAR_PSU_PCIE_LOW_S_AXI_BASEADDR 0xE0000000\r
 #define XPAR_PSU_PCIE_LOW_S_AXI_HIGHADDR 0xEFFFFFFF\r
@@ -560,11 +614,6 @@
 #define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF\r
 \r
 \r
-/* Definitions for peripheral PSU_PMU_IOMODULE */\r
-#define XPAR_PSU_PMU_IOMODULE_S_AXI_BASEADDR 0xFFD40000\r
-#define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF\r
-\r
-\r
 /* Definitions for peripheral PSU_QSPI_LINEAR_0 */\r
 #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000\r
 #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF\r
@@ -582,7 +631,7 @@
 \r
 /* Definitions for peripheral PSU_R5_DDR_0 */\r
 #define XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR 0x00100000\r
-#define XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR 0xFFFFFFFF\r
+#define XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR 0x7FFFFFFF\r
 \r
 \r
 /* Definitions for peripheral PSU_R5_TCM_RAM_0 */\r
@@ -625,6 +674,11 @@
 #define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF\r
 \r
 \r
+/* Definitions for peripheral PSU_USB_0 */\r
+#define XPAR_PSU_USB_0_S_AXI_BASEADDR 0xFF9D0000\r
+#define XPAR_PSU_USB_0_S_AXI_HIGHADDR 0xFF9DFFFF\r
+\r
+\r
 /******************************************************************/\r
 \r
 /* Definitions for driver GPIOPS */\r
@@ -653,14 +707,14 @@
 #define XPAR_PSU_I2C_0_DEVICE_ID 0\r
 #define XPAR_PSU_I2C_0_BASEADDR 0xFF020000\r
 #define XPAR_PSU_I2C_0_HIGHADDR 0xFF02FFFF\r
-#define XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ 99998999\r
+#define XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ 99990000\r
 \r
 \r
 /* Definitions for peripheral PSU_I2C_1 */\r
 #define XPAR_PSU_I2C_1_DEVICE_ID 1\r
 #define XPAR_PSU_I2C_1_BASEADDR 0xFF030000\r
 #define XPAR_PSU_I2C_1_HIGHADDR 0xFF03FFFF\r
-#define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 99998999\r
+#define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 99990000\r
 \r
 \r
 /******************************************************************/\r
@@ -669,32 +723,25 @@
 #define XPAR_XIICPS_0_DEVICE_ID XPAR_PSU_I2C_0_DEVICE_ID\r
 #define XPAR_XIICPS_0_BASEADDR 0xFF020000\r
 #define XPAR_XIICPS_0_HIGHADDR 0xFF02FFFF\r
-#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 99998999\r
+#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 99990000\r
 \r
 /* Canonical definitions for peripheral PSU_I2C_1 */\r
 #define XPAR_XIICPS_1_DEVICE_ID XPAR_PSU_I2C_1_DEVICE_ID\r
 #define XPAR_XIICPS_1_BASEADDR 0xFF030000\r
 #define XPAR_XIICPS_1_HIGHADDR 0xFF03FFFF\r
-#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 99998999\r
+#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 99990000\r
 \r
 \r
 /******************************************************************/\r
 \r
-#define  XPAR_XIPIPSU_NUM_INSTANCES  2\r
+#define  XPAR_XIPIPSU_NUM_INSTANCES  1U\r
 \r
 /* Parameter definitions for peripheral psu_ipi_1 */\r
-#define  XPAR_PSU_IPI_1_DEVICE_ID  0\r
-#define  XPAR_PSU_IPI_1_BASE_ADDRESS  0xFF310000\r
-#define  XPAR_PSU_IPI_1_BIT_MASK  0x00000100\r
-#define  XPAR_PSU_IPI_1_BUFFER_INDEX  0\r
-#define  XPAR_PSU_IPI_1_INT_ID  65\r
-\r
-/* Parameter definitions for peripheral psu_ipi_2 */\r
-#define  XPAR_PSU_IPI_2_DEVICE_ID  1\r
-#define  XPAR_PSU_IPI_2_BASE_ADDRESS  0xFF320000\r
-#define  XPAR_PSU_IPI_2_BIT_MASK  0x00000200\r
-#define  XPAR_PSU_IPI_2_BUFFER_INDEX  1\r
-#define  XPAR_PSU_IPI_2_INT_ID  66\r
+#define  XPAR_PSU_IPI_1_DEVICE_ID  0U\r
+#define  XPAR_PSU_IPI_1_BASE_ADDRESS  0xFF310000U\r
+#define  XPAR_PSU_IPI_1_BIT_MASK  0x00000100U\r
+#define  XPAR_PSU_IPI_1_BUFFER_INDEX  0U\r
+#define  XPAR_PSU_IPI_1_INT_ID  65U\r
 \r
 /* Canonical definitions for peripheral psu_ipi_1 */\r
 #define  XPAR_XIPIPSU_0_DEVICE_ID      XPAR_PSU_IPI_1_DEVICE_ID\r
@@ -703,89 +750,50 @@
 #define  XPAR_XIPIPSU_0_BUFFER_INDEX   XPAR_PSU_IPI_1_BUFFER_INDEX\r
 #define  XPAR_XIPIPSU_0_INT_ID XPAR_PSU_IPI_1_INT_ID\r
 \r
-/* Canonical definitions for peripheral psu_ipi_2 */\r
-#define  XPAR_XIPIPSU_1_DEVICE_ID      XPAR_PSU_IPI_2_DEVICE_ID\r
-#define  XPAR_XIPIPSU_1_BASE_ADDRESS   XPAR_PSU_IPI_2_BASE_ADDRESS\r
-#define  XPAR_XIPIPSU_1_BIT_MASK       XPAR_PSU_IPI_2_BIT_MASK\r
-#define  XPAR_XIPIPSU_1_BUFFER_INDEX   XPAR_PSU_IPI_2_BUFFER_INDEX\r
-#define  XPAR_XIPIPSU_1_INT_ID XPAR_PSU_IPI_2_INT_ID\r
-\r
-#define  XPAR_XIPIPSU_NUM_TARGETS  11\r
-\r
-#define  XPAR_PSU_IPI_0_BIT_MASK  0x00000001\r
-#define  XPAR_PSU_IPI_0_BUFFER_INDEX  2\r
-#define  XPAR_PSU_IPI_1_BIT_MASK  0x00000100\r
-#define  XPAR_PSU_IPI_1_BUFFER_INDEX  0\r
-#define  XPAR_PSU_IPI_2_BIT_MASK  0x00000200\r
-#define  XPAR_PSU_IPI_2_BUFFER_INDEX  1\r
-#define  XPAR_PSU_IPI_3_BIT_MASK  0x00010000\r
-#define  XPAR_PSU_IPI_3_BUFFER_INDEX  7\r
-#define  XPAR_PSU_IPI_4_BIT_MASK  0x00020000\r
-#define  XPAR_PSU_IPI_4_BUFFER_INDEX  7\r
-#define  XPAR_PSU_IPI_5_BIT_MASK  0x00040000\r
-#define  XPAR_PSU_IPI_5_BUFFER_INDEX  7\r
-#define  XPAR_PSU_IPI_6_BIT_MASK  0x00080000\r
-#define  XPAR_PSU_IPI_6_BUFFER_INDEX  7\r
-#define  XPAR_PSU_IPI_7_BIT_MASK  0x01000000\r
-#define  XPAR_PSU_IPI_7_BUFFER_INDEX  3\r
-#define  XPAR_PSU_IPI_8_BIT_MASK  0x02000000\r
-#define  XPAR_PSU_IPI_8_BUFFER_INDEX  4\r
-#define  XPAR_PSU_IPI_9_BIT_MASK  0x04000000\r
-#define  XPAR_PSU_IPI_9_BUFFER_INDEX  5\r
-#define  XPAR_PSU_IPI_10_BIT_MASK  0x08000000\r
-#define  XPAR_PSU_IPI_10_BUFFER_INDEX  6\r
+#define  XPAR_XIPIPSU_NUM_TARGETS  7U\r
+\r
+#define  XPAR_PSU_IPI_0_BIT_MASK  0x00000001U\r
+#define  XPAR_PSU_IPI_0_BUFFER_INDEX  2U\r
+#define  XPAR_PSU_IPI_1_BIT_MASK  0x00000100U\r
+#define  XPAR_PSU_IPI_1_BUFFER_INDEX  0U\r
+#define  XPAR_PSU_IPI_2_BIT_MASK  0x00000200U\r
+#define  XPAR_PSU_IPI_2_BUFFER_INDEX  1U\r
+#define  XPAR_PSU_IPI_3_BIT_MASK  0x00010000U\r
+#define  XPAR_PSU_IPI_3_BUFFER_INDEX  7U\r
+#define  XPAR_PSU_IPI_4_BIT_MASK  0x00020000U\r
+#define  XPAR_PSU_IPI_4_BUFFER_INDEX  7U\r
+#define  XPAR_PSU_IPI_5_BIT_MASK  0x00040000U\r
+#define  XPAR_PSU_IPI_5_BUFFER_INDEX  7U\r
+#define  XPAR_PSU_IPI_6_BIT_MASK  0x00080000U\r
+#define  XPAR_PSU_IPI_6_BUFFER_INDEX  7U\r
 /* Target List for referring to processor IPI Targets */\r
 \r
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX  0\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_INDEX  1\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_INDEX  2\r
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX  0U\r
 \r
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX  0\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_INDEX  1\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_INDEX  2\r
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX  0U\r
 \r
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX  0\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_INDEX  1\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_INDEX  2\r
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX  0U\r
 \r
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX  0\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_INDEX  1\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_INDEX  2\r
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX  0U\r
 \r
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX  1\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH1_INDEX  2\r
-\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX  1\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_INDEX  2\r
-\r
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX  1\r
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX  2\r
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK  XPAR_PSU_IPI_3_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX  3\r
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK  XPAR_PSU_IPI_4_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX  4\r
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_MASK  XPAR_PSU_IPI_5_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_INDEX  5\r
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_MASK  XPAR_PSU_IPI_6_BIT_MASK\r
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_INDEX  6\r
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX  1U\r
+\r
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK  XPAR_PSU_IPI_2_BIT_MASK\r
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX  2U\r
+\r
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK  XPAR_PSU_IPI_3_BIT_MASK\r
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX  3U\r
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK  XPAR_PSU_IPI_4_BIT_MASK\r
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX  4U\r
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK  XPAR_PSU_IPI_5_BIT_MASK\r
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX  5U\r
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK  XPAR_PSU_IPI_6_BIT_MASK\r
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX  6U\r
 \r
 /* Definitions for driver QSPIPSU */\r
 #define XPAR_XQSPIPSU_NUM_INSTANCES 1\r
@@ -794,22 +802,31 @@
 #define XPAR_PSU_QSPI_0_DEVICE_ID 0\r
 #define XPAR_PSU_QSPI_0_BASEADDR 0xFF0F0000\r
 #define XPAR_PSU_QSPI_0_HIGHADDR 0xFF0FFFFF\r
-#define XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ 124998749\r
+#define XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ 124987500\r
 #define XPAR_PSU_QSPI_0_QSPI_MODE 2\r
 #define XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH 2\r
 \r
 \r
 /******************************************************************/\r
 \r
+#define XPAR_PSU_QSPI_0_IS_CACHE_COHERENT 0\r
 /* Canonical definitions for peripheral PSU_QSPI_0 */\r
 #define XPAR_XQSPIPSU_0_DEVICE_ID XPAR_PSU_QSPI_0_DEVICE_ID\r
 #define XPAR_XQSPIPSU_0_BASEADDR 0xFF0F0000\r
 #define XPAR_XQSPIPSU_0_HIGHADDR 0xFF0FFFFF\r
-#define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 124998749\r
+#define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 124987500\r
 #define XPAR_XQSPIPSU_0_QSPI_MODE 2\r
 #define XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH 2\r
 \r
 \r
+/******************************************************************/\r
+\r
+/* Definitions for driver RESETPS */\r
+#define XPAR_XRESETPS_NUM_INSTANCES 1U\r
+/* Definitions for peripheral RESETPS */\r
+#define XPAR_XRESETPS_DEVICE_ID 0\r
+#define XPAR_XRESETPS_BASEADDR 0xFFFFFFFFU\r
+\r
 /******************************************************************/\r
 \r
 /* Definitions for driver RTCPSU */\r
@@ -832,22 +849,22 @@
 /******************************************************************/\r
 \r
 /* Definitions for driver SCUGIC */\r
-#define XPAR_XSCUGIC_NUM_INSTANCES 1\r
+#define XPAR_XSCUGIC_NUM_INSTANCES 1U\r
 \r
 /* Definitions for peripheral PSU_RCPU_GIC */\r
-#define XPAR_PSU_RCPU_GIC_DEVICE_ID 0\r
-#define XPAR_PSU_RCPU_GIC_BASEADDR 0xF9001000\r
-#define XPAR_PSU_RCPU_GIC_HIGHADDR 0xF9001FFF\r
-#define XPAR_PSU_RCPU_GIC_DIST_BASEADDR 0xF9000000\r
+#define XPAR_PSU_RCPU_GIC_DEVICE_ID 0U\r
+#define XPAR_PSU_RCPU_GIC_BASEADDR 0xF9001000U\r
+#define XPAR_PSU_RCPU_GIC_HIGHADDR 0xF9001FFFU\r
+#define XPAR_PSU_RCPU_GIC_DIST_BASEADDR 0xF9000000U\r
 \r
 \r
 /******************************************************************/\r
 \r
 /* Canonical definitions for peripheral PSU_RCPU_GIC */\r
-#define XPAR_SCUGIC_0_DEVICE_ID 0\r
-#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9001000\r
-#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9001FFF\r
-#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9000000\r
+#define XPAR_SCUGIC_0_DEVICE_ID 0U\r
+#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9001000U\r
+#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9001FFFU\r
+#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9000000U\r
 \r
 \r
 /******************************************************************/\r
@@ -859,24 +876,25 @@
 #define XPAR_PSU_SD_1_DEVICE_ID 0\r
 #define XPAR_PSU_SD_1_BASEADDR 0xFF170000\r
 #define XPAR_PSU_SD_1_HIGHADDR 0xFF17FFFF\r
-#define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 199998006\r
+#define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 187481250\r
 #define XPAR_PSU_SD_1_HAS_CD 1\r
 #define XPAR_PSU_SD_1_HAS_WP 1\r
-#define XPAR_PSU_SD_1_BUS_WIDTH 4\r
+#define XPAR_PSU_SD_1_BUS_WIDTH 8\r
 #define XPAR_PSU_SD_1_MIO_BANK 1\r
 #define XPAR_PSU_SD_1_HAS_EMIO 0\r
 \r
 \r
 /******************************************************************/\r
 \r
+#define XPAR_PSU_SD_1_IS_CACHE_COHERENT 0\r
 /* Canonical definitions for peripheral PSU_SD_1 */\r
 #define XPAR_XSDPS_0_DEVICE_ID XPAR_PSU_SD_1_DEVICE_ID\r
 #define XPAR_XSDPS_0_BASEADDR 0xFF170000\r
 #define XPAR_XSDPS_0_HIGHADDR 0xFF17FFFF\r
-#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 199998006\r
+#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 187481250\r
 #define XPAR_XSDPS_0_HAS_CD 1\r
 #define XPAR_XSDPS_0_HAS_WP 1\r
-#define XPAR_XSDPS_0_BUS_WIDTH 4\r
+#define XPAR_XSDPS_0_BUS_WIDTH 8\r
 #define XPAR_XSDPS_0_MIO_BANK 1\r
 #define XPAR_XSDPS_0_HAS_EMIO 0\r
 \r
@@ -894,6 +912,7 @@
 \r
 /******************************************************************/\r
 \r
+#define XPAR_PSU_AMS_REF_FREQMHZ 49.995\r
 /* Canonical definitions for peripheral PSU_AMS */\r
 #define XPAR_XSYSMONPSU_0_DEVICE_ID XPAR_PSU_AMS_DEVICE_ID\r
 #define XPAR_XSYSMONPSU_0_BASEADDR 0xFFA50000\r
@@ -903,133 +922,133 @@
 /******************************************************************/\r
 \r
 /* Definitions for driver TTCPS */\r
-#define XPAR_XTTCPS_NUM_INSTANCES 12\r
+#define XPAR_XTTCPS_NUM_INSTANCES 12U\r
 \r
 /* Definitions for peripheral PSU_TTC_0 */\r
-#define XPAR_PSU_TTC_0_DEVICE_ID 0\r
-#define XPAR_PSU_TTC_0_BASEADDR 0XFF110000\r
-#define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0\r
-#define XPAR_PSU_TTC_1_DEVICE_ID 1\r
-#define XPAR_PSU_TTC_1_BASEADDR 0XFF110004\r
-#define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0\r
-#define XPAR_PSU_TTC_2_DEVICE_ID 2\r
-#define XPAR_PSU_TTC_2_BASEADDR 0XFF110008\r
-#define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0\r
+#define XPAR_PSU_TTC_0_DEVICE_ID 0U\r
+#define XPAR_PSU_TTC_0_BASEADDR 0XFF110000U\r
+#define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0U\r
+#define XPAR_PSU_TTC_1_DEVICE_ID 1U\r
+#define XPAR_PSU_TTC_1_BASEADDR 0XFF110004U\r
+#define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0U\r
+#define XPAR_PSU_TTC_2_DEVICE_ID 2U\r
+#define XPAR_PSU_TTC_2_BASEADDR 0XFF110008U\r
+#define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0U\r
 \r
 \r
 /* Definitions for peripheral PSU_TTC_1 */\r
-#define XPAR_PSU_TTC_3_DEVICE_ID 3\r
-#define XPAR_PSU_TTC_3_BASEADDR 0XFF120000\r
-#define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0\r
-#define XPAR_PSU_TTC_4_DEVICE_ID 4\r
-#define XPAR_PSU_TTC_4_BASEADDR 0XFF120004\r
-#define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0\r
-#define XPAR_PSU_TTC_5_DEVICE_ID 5\r
-#define XPAR_PSU_TTC_5_BASEADDR 0XFF120008\r
-#define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0\r
+#define XPAR_PSU_TTC_3_DEVICE_ID 3U\r
+#define XPAR_PSU_TTC_3_BASEADDR 0XFF120000U\r
+#define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0U\r
+#define XPAR_PSU_TTC_4_DEVICE_ID 4U\r
+#define XPAR_PSU_TTC_4_BASEADDR 0XFF120004U\r
+#define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0U\r
+#define XPAR_PSU_TTC_5_DEVICE_ID 5U\r
+#define XPAR_PSU_TTC_5_BASEADDR 0XFF120008U\r
+#define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0U\r
 \r
 \r
 /* Definitions for peripheral PSU_TTC_2 */\r
-#define XPAR_PSU_TTC_6_DEVICE_ID 6\r
-#define XPAR_PSU_TTC_6_BASEADDR 0XFF130000\r
-#define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0\r
-#define XPAR_PSU_TTC_7_DEVICE_ID 7\r
-#define XPAR_PSU_TTC_7_BASEADDR 0XFF130004\r
-#define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0\r
-#define XPAR_PSU_TTC_8_DEVICE_ID 8\r
-#define XPAR_PSU_TTC_8_BASEADDR 0XFF130008\r
-#define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0\r
+#define XPAR_PSU_TTC_6_DEVICE_ID 6U\r
+#define XPAR_PSU_TTC_6_BASEADDR 0XFF130000U\r
+#define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0U\r
+#define XPAR_PSU_TTC_7_DEVICE_ID 7U\r
+#define XPAR_PSU_TTC_7_BASEADDR 0XFF130004U\r
+#define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0U\r
+#define XPAR_PSU_TTC_8_DEVICE_ID 8U\r
+#define XPAR_PSU_TTC_8_BASEADDR 0XFF130008U\r
+#define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0U\r
 \r
 \r
 /* Definitions for peripheral PSU_TTC_3 */\r
-#define XPAR_PSU_TTC_9_DEVICE_ID 9\r
-#define XPAR_PSU_TTC_9_BASEADDR 0XFF140000\r
-#define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0\r
-#define XPAR_PSU_TTC_10_DEVICE_ID 10\r
-#define XPAR_PSU_TTC_10_BASEADDR 0XFF140004\r
-#define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0\r
-#define XPAR_PSU_TTC_11_DEVICE_ID 11\r
-#define XPAR_PSU_TTC_11_BASEADDR 0XFF140008\r
-#define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0\r
+#define XPAR_PSU_TTC_9_DEVICE_ID 9U\r
+#define XPAR_PSU_TTC_9_BASEADDR 0XFF140000U\r
+#define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0U\r
+#define XPAR_PSU_TTC_10_DEVICE_ID 10U\r
+#define XPAR_PSU_TTC_10_BASEADDR 0XFF140004U\r
+#define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0U\r
+#define XPAR_PSU_TTC_11_DEVICE_ID 11U\r
+#define XPAR_PSU_TTC_11_BASEADDR 0XFF140008U\r
+#define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0U\r
 \r
 \r
 /******************************************************************/\r
 \r
 /* Canonical definitions for peripheral PSU_TTC_0 */\r
 #define XPAR_XTTCPS_0_DEVICE_ID XPAR_PSU_TTC_0_DEVICE_ID\r
-#define XPAR_XTTCPS_0_BASEADDR 0xFF110000\r
-#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0\r
+#define XPAR_XTTCPS_0_BASEADDR 0xFF110000U\r
+#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U\r
 \r
 #define XPAR_XTTCPS_1_DEVICE_ID XPAR_PSU_TTC_1_DEVICE_ID\r
-#define XPAR_XTTCPS_1_BASEADDR 0xFF110004\r
-#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0\r
+#define XPAR_XTTCPS_1_BASEADDR 0xFF110004U\r
+#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U\r
 \r
 #define XPAR_XTTCPS_2_DEVICE_ID XPAR_PSU_TTC_2_DEVICE_ID\r
-#define XPAR_XTTCPS_2_BASEADDR 0xFF110008\r
-#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0\r
+#define XPAR_XTTCPS_2_BASEADDR 0xFF110008U\r
+#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U\r
 \r
 /* Canonical definitions for peripheral PSU_TTC_1 */\r
 #define XPAR_XTTCPS_3_DEVICE_ID XPAR_PSU_TTC_3_DEVICE_ID\r
-#define XPAR_XTTCPS_3_BASEADDR 0xFF120000\r
-#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0\r
+#define XPAR_XTTCPS_3_BASEADDR 0xFF120000U\r
+#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0U\r
 \r
 #define XPAR_XTTCPS_4_DEVICE_ID XPAR_PSU_TTC_4_DEVICE_ID\r
-#define XPAR_XTTCPS_4_BASEADDR 0xFF120004\r
-#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0\r
+#define XPAR_XTTCPS_4_BASEADDR 0xFF120004U\r
+#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0U\r
 \r
 #define XPAR_XTTCPS_5_DEVICE_ID XPAR_PSU_TTC_5_DEVICE_ID\r
-#define XPAR_XTTCPS_5_BASEADDR 0xFF120008\r
-#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0\r
+#define XPAR_XTTCPS_5_BASEADDR 0xFF120008U\r
+#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0U\r
 \r
 /* Canonical definitions for peripheral PSU_TTC_2 */\r
 #define XPAR_XTTCPS_6_DEVICE_ID XPAR_PSU_TTC_6_DEVICE_ID\r
-#define XPAR_XTTCPS_6_BASEADDR 0xFF130000\r
-#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0\r
+#define XPAR_XTTCPS_6_BASEADDR 0xFF130000U\r
+#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0U\r
 \r
 #define XPAR_XTTCPS_7_DEVICE_ID XPAR_PSU_TTC_7_DEVICE_ID\r
-#define XPAR_XTTCPS_7_BASEADDR 0xFF130004\r
-#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0\r
+#define XPAR_XTTCPS_7_BASEADDR 0xFF130004U\r
+#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0U\r
 \r
 #define XPAR_XTTCPS_8_DEVICE_ID XPAR_PSU_TTC_8_DEVICE_ID\r
-#define XPAR_XTTCPS_8_BASEADDR 0xFF130008\r
-#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0\r
+#define XPAR_XTTCPS_8_BASEADDR 0xFF130008U\r
+#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0U\r
 \r
 /* Canonical definitions for peripheral PSU_TTC_3 */\r
 #define XPAR_XTTCPS_9_DEVICE_ID XPAR_PSU_TTC_9_DEVICE_ID\r
-#define XPAR_XTTCPS_9_BASEADDR 0xFF140000\r
-#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0\r
+#define XPAR_XTTCPS_9_BASEADDR 0xFF140000U\r
+#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0U\r
 \r
 #define XPAR_XTTCPS_10_DEVICE_ID XPAR_PSU_TTC_10_DEVICE_ID\r
-#define XPAR_XTTCPS_10_BASEADDR 0xFF140004\r
-#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0\r
+#define XPAR_XTTCPS_10_BASEADDR 0xFF140004U\r
+#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0U\r
 \r
 #define XPAR_XTTCPS_11_DEVICE_ID XPAR_PSU_TTC_11_DEVICE_ID\r
-#define XPAR_XTTCPS_11_BASEADDR 0xFF140008\r
-#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 100000000\r
-#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0\r
+#define XPAR_XTTCPS_11_BASEADDR 0xFF140008U\r
+#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 100000000U\r
+#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0U\r
 \r
 \r
 /******************************************************************/\r
@@ -1041,7 +1060,7 @@
 #define XPAR_PSU_UART_0_DEVICE_ID 0\r
 #define XPAR_PSU_UART_0_BASEADDR 0xFF000000\r
 #define XPAR_PSU_UART_0_HIGHADDR 0xFF00FFFF\r
-#define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 99998999\r
+#define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 99990000\r
 #define XPAR_PSU_UART_0_HAS_MODEM 0\r
 \r
 \r
@@ -1049,7 +1068,7 @@
 #define XPAR_PSU_UART_1_DEVICE_ID 1\r
 #define XPAR_PSU_UART_1_BASEADDR 0xFF010000\r
 #define XPAR_PSU_UART_1_HIGHADDR 0xFF01FFFF\r
-#define XPAR_PSU_UART_1_UART_CLK_FREQ_HZ 99998999\r
+#define XPAR_PSU_UART_1_UART_CLK_FREQ_HZ 99990000\r
 #define XPAR_PSU_UART_1_HAS_MODEM 0\r
 \r
 \r
@@ -1059,14 +1078,14 @@
 #define XPAR_XUARTPS_0_DEVICE_ID XPAR_PSU_UART_0_DEVICE_ID\r
 #define XPAR_XUARTPS_0_BASEADDR 0xFF000000\r
 #define XPAR_XUARTPS_0_HIGHADDR 0xFF00FFFF\r
-#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 99998999\r
+#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 99990000\r
 #define XPAR_XUARTPS_0_HAS_MODEM 0\r
 \r
 /* Canonical definitions for peripheral PSU_UART_1 */\r
 #define XPAR_XUARTPS_1_DEVICE_ID XPAR_PSU_UART_1_DEVICE_ID\r
 #define XPAR_XUARTPS_1_BASEADDR 0xFF010000\r
 #define XPAR_XUARTPS_1_HIGHADDR 0xFF01FFFF\r
-#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 99998999\r
+#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 99990000\r
 #define XPAR_XUARTPS_1_HAS_MODEM 0\r
 \r
 \r
@@ -1075,16 +1094,17 @@
 /* Definitions for driver USBPSU */\r
 #define XPAR_XUSBPSU_NUM_INSTANCES 1\r
 \r
-/* Definitions for peripheral PSU_USB_0 */\r
-#define XPAR_PSU_USB_0_DEVICE_ID 0\r
-#define XPAR_PSU_USB_0_BASEADDR 0xFE200000\r
-#define XPAR_PSU_USB_0_HIGHADDR 0xFE20FFFF\r
+/* Definitions for peripheral PSU_USB_XHCI_0 */\r
+#define XPAR_PSU_USB_XHCI_0_DEVICE_ID 0\r
+#define XPAR_PSU_USB_XHCI_0_BASEADDR 0xFE200000\r
+#define XPAR_PSU_USB_XHCI_0_HIGHADDR 0xFE20FFFF\r
 \r
 \r
 /******************************************************************/\r
 \r
-/* Canonical definitions for peripheral PSU_USB_0 */\r
-#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_0_DEVICE_ID\r
+#define XPAR_PSU_USB_XHCI_0_IS_CACHE_COHERENT 0\r
+/* Canonical definitions for peripheral PSU_USB_XHCI_0 */\r
+#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_XHCI_0_DEVICE_ID\r
 #define XPAR_XUSBPSU_0_BASEADDR 0xFE200000\r
 #define XPAR_XUSBPSU_0_HIGHADDR 0xFE20FFFF\r
 \r
@@ -1092,35 +1112,48 @@
 /******************************************************************/\r
 \r
 /* Definitions for driver WDTPS */\r
-#define XPAR_XWDTPS_NUM_INSTANCES 2\r
+#define XPAR_XWDTPS_NUM_INSTANCES 3\r
+\r
+/* Definitions for peripheral PSU_CSU_WDT */\r
+#define XPAR_PSU_CSU_WDT_DEVICE_ID 0\r
+#define XPAR_PSU_CSU_WDT_BASEADDR 0xFFCB0000\r
+#define XPAR_PSU_CSU_WDT_HIGHADDR 0xFFCBFFFF\r
+#define XPAR_PSU_CSU_WDT_WDT_CLK_FREQ_HZ 100000000\r
+\r
 \r
 /* Definitions for peripheral PSU_WDT_0 */\r
-#define XPAR_PSU_WDT_0_DEVICE_ID 0\r
+#define XPAR_PSU_WDT_0_DEVICE_ID 1\r
 #define XPAR_PSU_WDT_0_BASEADDR 0xFF150000\r
 #define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF\r
-#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99999001\r
+#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99989998\r
 \r
 \r
 /* Definitions for peripheral PSU_WDT_1 */\r
-#define XPAR_PSU_WDT_1_DEVICE_ID 1\r
+#define XPAR_PSU_WDT_1_DEVICE_ID 2\r
 #define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000\r
 #define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF\r
-#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99999001\r
+#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99989998\r
 \r
 \r
 /******************************************************************/\r
 \r
+/* Canonical definitions for peripheral PSU_CSU_WDT */\r
+#define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_CSU_WDT_DEVICE_ID\r
+#define XPAR_XWDTPS_0_BASEADDR 0xFFCB0000\r
+#define XPAR_XWDTPS_0_HIGHADDR 0xFFCBFFFF\r
+#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 100000000\r
+\r
 /* Canonical definitions for peripheral PSU_WDT_0 */\r
-#define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID\r
-#define XPAR_XWDTPS_0_BASEADDR 0xFF150000\r
-#define XPAR_XWDTPS_0_HIGHADDR 0xFF15FFFF\r
-#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 99999001\r
+#define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID\r
+#define XPAR_XWDTPS_1_BASEADDR 0xFF150000\r
+#define XPAR_XWDTPS_1_HIGHADDR 0xFF15FFFF\r
+#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99989998\r
 \r
 /* Canonical definitions for peripheral PSU_WDT_1 */\r
-#define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID\r
-#define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000\r
-#define XPAR_XWDTPS_1_HIGHADDR 0xFD4DFFFF\r
-#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99999001\r
+#define XPAR_XWDTPS_2_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID\r
+#define XPAR_XWDTPS_2_BASEADDR 0xFD4D0000\r
+#define XPAR_XWDTPS_2_HIGHADDR 0xFD4DFFFF\r
+#define XPAR_XWDTPS_2_WDT_CLK_FREQ_HZ 99989998\r
 \r
 \r
 /******************************************************************/\r
@@ -1258,6 +1291,22 @@
 \r
 /******************************************************************/\r
 \r
+#define XPAR_PSU_ADMA_0_IS_CACHE_COHERENT 0\r
+#define XPAR_PSU_ADMA_1_IS_CACHE_COHERENT 0\r
+#define XPAR_PSU_ADMA_2_IS_CACHE_COHERENT 0\r
+#define XPAR_PSU_ADMA_3_IS_CACHE_COHERENT 0\r
+#define XPAR_PSU_ADMA_4_IS_CACHE_COHERENT 0\r
+#define XPAR_PSU_ADMA_5_IS_CACHE_COHERENT 0\r
+#define XPAR_PSU_ADMA_6_IS_CACHE_COHERENT 0\r
+#define XPAR_PSU_ADMA_7_IS_CACHE_COHERENT 0\r
+#define XPAR_PSU_GDMA_0_IS_CACHE_COHERENT 0\r
+#define XPAR_PSU_GDMA_1_IS_CACHE_COHERENT 0\r
+#define XPAR_PSU_GDMA_2_IS_CACHE_COHERENT 0\r
+#define XPAR_PSU_GDMA_3_IS_CACHE_COHERENT 0\r
+#define XPAR_PSU_GDMA_4_IS_CACHE_COHERENT 0\r
+#define XPAR_PSU_GDMA_5_IS_CACHE_COHERENT 0\r
+#define XPAR_PSU_GDMA_6_IS_CACHE_COHERENT 0\r
+#define XPAR_PSU_GDMA_7_IS_CACHE_COHERENT 0\r
 /* Canonical definitions for peripheral PSU_ADMA_0 */\r
 #define XPAR_XZDMA_0_DEVICE_ID XPAR_PSU_ADMA_0_DEVICE_ID\r
 #define XPAR_XZDMA_0_BASEADDR 0xFFA80000\r
@@ -1373,3 +1422,4 @@
 \r
 /******************************************************************/\r
 \r
+#endif  /* end of protection macro */\r