\r
/******************************************************************/\r
\r
+ /* Definition for PSS REF CLK FREQUENCY */\r
+#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33333000U\r
+\r
#include "xparameters_ps.h"\r
\r
/******************************************************************/\r
\r
/******************************************************************/\r
\r
+\r
+/* Number of Fabric Resets */\r
+#define XPAR_NUM_FABRIC_RESETS 1\r
+\r
#define STDIN_BASEADDRESS 0xFF000000\r
#define STDOUT_BASEADDRESS 0xFF000000\r
\r
#define XPAR_XCSUDMA_0_CSUDMA_CLK_FREQ_HZ 0\r
\r
\r
+/******************************************************************/\r
+\r
+/* Definitions for driver DDRCPSU */\r
+#define XPAR_XDDRCPSU_NUM_INSTANCES 1\r
+\r
+/* Definitions for peripheral PSU_DDRC_0 */\r
+#define XPAR_PSU_DDRC_0_DEVICE_ID 0\r
+#define XPAR_PSU_DDRC_0_BASEADDR 0xFD070000\r
+#define XPAR_PSU_DDRC_0_HIGHADDR 0xFD070FFF\r
+#define XPAR_PSU_DDRC_0_HAS_ECC 0\r
+#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 533328002\r
+\r
+\r
+/******************************************************************/\r
+\r
+/* Canonical definitions for peripheral PSU_DDRC_0 */\r
+#define XPAR_DDRCPSU_0_DEVICE_ID XPAR_PSU_DDRC_0_DEVICE_ID\r
+#define XPAR_DDRCPSU_0_BASEADDR 0xFD070000\r
+#define XPAR_DDRCPSU_0_HIGHADDR 0xFD070FFF\r
+#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 533328002\r
+\r
+\r
/******************************************************************/\r
\r
/* Definitions for driver EMACPS */\r
#define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000\r
#define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF\r
#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749\r
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 50000000\r
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 50000000\r
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 50000000\r
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 50000000\r
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 50000000\r
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 50000000\r
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12\r
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1\r
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60\r
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1\r
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60\r
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10\r
\r
\r
/******************************************************************/\r
#define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000\r
#define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF\r
#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749\r
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 50000000\r
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 50000000\r
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 50000000\r
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 50000000\r
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 50000000\r
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50000000\r
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12\r
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1\r
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60\r
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1\r
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60\r
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10\r
\r
\r
/******************************************************************/\r
#define XPAR_PSU_APU_S_AXI_HIGHADDR 0xFD5CFFFF\r
\r
\r
-/* Definitions for peripheral PSU_BBRAM_0 */\r
-#define XPAR_PSU_BBRAM_0_S_AXI_BASEADDR 0xFFCD0000\r
-#define XPAR_PSU_BBRAM_0_S_AXI_HIGHADDR 0xFFCDFFFF\r
-\r
-\r
/* Definitions for peripheral PSU_CCI_GPV */\r
#define XPAR_PSU_CCI_GPV_S_AXI_BASEADDR 0xFD6E0000\r
#define XPAR_PSU_CCI_GPV_S_AXI_HIGHADDR 0xFD6EFFFF\r
#define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF\r
\r
\r
-/* Definitions for peripheral PSU_DDRC_0 */\r
-#define XPAR_PSU_DDRC_0_S_AXI_BASEADDR 0xFD070000\r
-#define XPAR_PSU_DDRC_0_S_AXI_HIGHADDR 0xFD070FFF\r
-\r
-\r
/* Definitions for peripheral PSU_DP */\r
#define XPAR_PSU_DP_S_AXI_BASEADDR 0xFD4A0000\r
#define XPAR_PSU_DP_S_AXI_HIGHADDR 0xFD4AFFFF\r
#define XPAR_PSU_GPU_S_AXI_HIGHADDR 0xFD4BFFFF\r
\r
\r
-/* Definitions for peripheral PSU_IOU_S */\r
-#define XPAR_PSU_IOU_S_S_AXI_BASEADDR 0xFF000000\r
-#define XPAR_PSU_IOU_S_S_AXI_HIGHADDR 0xFF2AFFFF\r
-\r
-\r
/* Definitions for peripheral PSU_IOU_SCNTR */\r
#define XPAR_PSU_IOU_SCNTR_S_AXI_BASEADDR 0xFF250000\r
#define XPAR_PSU_IOU_SCNTR_S_AXI_HIGHADDR 0xFF25FFFF\r
#define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFEFFFF\r
\r
\r
-/* Definitions for peripheral PSU_OCM_RAM_1 */\r
-#define XPAR_PSU_OCM_RAM_1_S_AXI_BASEADDR 0xFFFF0000\r
-#define XPAR_PSU_OCM_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF\r
-\r
-\r
/* Definitions for peripheral PSU_OCM_XMPU_CFG */\r
#define XPAR_PSU_OCM_XMPU_CFG_S_AXI_BASEADDR 0xFFA70000\r
#define XPAR_PSU_OCM_XMPU_CFG_S_AXI_HIGHADDR 0xFFA7FFFF\r
#define XPAR_PSU_PCIE_DMA_S_AXI_HIGHADDR 0xFD0FFFFF\r
\r
\r
+/* Definitions for peripheral PSU_PCIE_LOW */\r
+#define XPAR_PSU_PCIE_LOW_S_AXI_BASEADDR 0xE0000000\r
+#define XPAR_PSU_PCIE_LOW_S_AXI_HIGHADDR 0xEFFFFFFF\r
+\r
+\r
/* Definitions for peripheral PSU_PMU_GLOBAL_0 */\r
#define XPAR_PSU_PMU_GLOBAL_0_S_AXI_BASEADDR 0xFFD80000\r
#define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF\r
#define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF\r
\r
\r
-/* Definitions for peripheral PSU_PMU_RAM */\r
-#define XPAR_PSU_PMU_RAM_S_AXI_BASEADDR 0xFFDC0000\r
-#define XPAR_PSU_PMU_RAM_S_AXI_HIGHADDR 0xFFDDFFFF\r
-\r
-\r
/* Definitions for peripheral PSU_QSPI_LINEAR_0 */\r
#define XPAR_PSU_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000\r
#define XPAR_PSU_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF\r
\r
\r
/* Definitions for peripheral PSU_R5_0_ATCM */\r
-#define XPAR_PSU_R5_0_ATCM_S_AXI_BASEADDR 0xFFE00000\r
-#define XPAR_PSU_R5_0_ATCM_S_AXI_HIGHADDR 0xFFE0FFFF\r
-\r
-\r
-/* Definitions for peripheral PSU_R5_0_ATCM_LOCKSTEP */\r
-#define XPAR_PSU_R5_0_ATCM_LOCKSTEP_S_AXI_BASEADDR 0xFFE10000\r
-#define XPAR_PSU_R5_0_ATCM_LOCKSTEP_S_AXI_HIGHADDR 0xFFE1FFFF\r
+#define XPAR_PSU_R5_0_ATCM_S_AXI_BASEADDR 0x00000000\r
+#define XPAR_PSU_R5_0_ATCM_S_AXI_HIGHADDR 0x0000FFFF\r
\r
\r
/* Definitions for peripheral PSU_R5_0_BTCM */\r
-#define XPAR_PSU_R5_0_BTCM_S_AXI_BASEADDR 0xFFE20000\r
-#define XPAR_PSU_R5_0_BTCM_S_AXI_HIGHADDR 0xFFE2FFFF\r
-\r
-\r
-/* Definitions for peripheral PSU_R5_0_BTCM_LOCKSTEP */\r
-#define XPAR_PSU_R5_0_BTCM_LOCKSTEP_S_AXI_BASEADDR 0xFFE30000\r
-#define XPAR_PSU_R5_0_BTCM_LOCKSTEP_S_AXI_HIGHADDR 0xFFE3FFFF\r
-\r
-\r
-/* Definitions for peripheral PSU_R5_1_ATCM */\r
-#define XPAR_PSU_R5_1_ATCM_S_AXI_BASEADDR 0xFFE90000\r
-#define XPAR_PSU_R5_1_ATCM_S_AXI_HIGHADDR 0xFFE9FFFF\r
-\r
-\r
-/* Definitions for peripheral PSU_R5_1_BTCM */\r
-#define XPAR_PSU_R5_1_BTCM_S_AXI_BASEADDR 0xFFEB0000\r
-#define XPAR_PSU_R5_1_BTCM_S_AXI_HIGHADDR 0xFFEBFFFF\r
+#define XPAR_PSU_R5_0_BTCM_S_AXI_BASEADDR 0x00020000\r
+#define XPAR_PSU_R5_0_BTCM_S_AXI_HIGHADDR 0x0002FFFF\r
\r
\r
/* Definitions for peripheral PSU_R5_DDR_0 */\r
\r
/* Definitions for peripheral PSU_R5_TCM_RAM_0 */\r
#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_BASEADDR 0x00000000\r
-#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_HIGHADDR 0x00020000\r
+#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_HIGHADDR 0x0003FFFF\r
\r
\r
/* Definitions for peripheral PSU_RPU */\r
#define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF\r
\r
\r
-/* Definitions for peripheral PSU_USB_0 */\r
-#define XPAR_PSU_USB_0_S_AXI_BASEADDR 0xFE200000\r
-#define XPAR_PSU_USB_0_S_AXI_HIGHADDR 0xFE20FFFF\r
-\r
-\r
/******************************************************************/\r
\r
/* Definitions for driver GPIOPS */\r
\r
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK\r
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0\r
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_MASK XPAR_PSU_IPI_1_BIT_MASK\r
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_INDEX 1\r
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_MASK XPAR_PSU_IPI_2_BIT_MASK\r
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_INDEX 2\r
\r
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK\r
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0\r
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_MASK XPAR_PSU_IPI_1_BIT_MASK\r
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_INDEX 1\r
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_MASK XPAR_PSU_IPI_2_BIT_MASK\r
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_INDEX 2\r
\r
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK\r
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0\r
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_MASK XPAR_PSU_IPI_1_BIT_MASK\r
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_INDEX 1\r
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_MASK XPAR_PSU_IPI_2_BIT_MASK\r
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_INDEX 2\r
\r
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK\r
#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0\r
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_MASK XPAR_PSU_IPI_1_BIT_MASK\r
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_INDEX 1\r
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_MASK XPAR_PSU_IPI_2_BIT_MASK\r
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_INDEX 2\r
\r
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK\r
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 1\r
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_MASK XPAR_PSU_IPI_2_BIT_MASK\r
#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_INDEX 2\r
\r
-#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK XPAR_PSU_IPI_3_BIT_MASK\r
-#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 3\r
-#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK XPAR_PSU_IPI_4_BIT_MASK\r
-#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 4\r
-#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK XPAR_PSU_IPI_5_BIT_MASK\r
-#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 5\r
-#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK XPAR_PSU_IPI_6_BIT_MASK\r
-#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 6\r
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK\r
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 1\r
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK XPAR_PSU_IPI_2_BIT_MASK\r
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 2\r
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK XPAR_PSU_IPI_3_BIT_MASK\r
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 3\r
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK XPAR_PSU_IPI_4_BIT_MASK\r
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 4\r
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_MASK XPAR_PSU_IPI_5_BIT_MASK\r
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_INDEX 5\r
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_MASK XPAR_PSU_IPI_6_BIT_MASK\r
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_INDEX 6\r
\r
/* Definitions for driver QSPIPSU */\r
#define XPAR_XQSPIPSU_NUM_INSTANCES 1\r
#define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 199998006\r
#define XPAR_PSU_SD_1_HAS_CD 1\r
#define XPAR_PSU_SD_1_HAS_WP 1\r
+#define XPAR_PSU_SD_1_BUS_WIDTH 4\r
+#define XPAR_PSU_SD_1_MIO_BANK 1\r
+#define XPAR_PSU_SD_1_HAS_EMIO 0\r
\r
\r
/******************************************************************/\r
#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 199998006\r
#define XPAR_XSDPS_0_HAS_CD 1\r
#define XPAR_XSDPS_0_HAS_WP 1\r
+#define XPAR_XSDPS_0_BUS_WIDTH 4\r
+#define XPAR_XSDPS_0_MIO_BANK 1\r
+#define XPAR_XSDPS_0_HAS_EMIO 0\r
\r
\r
/******************************************************************/\r
#define XPAR_XUARTPS_1_HAS_MODEM 0\r
\r
\r
+/******************************************************************/\r
+\r
+/* Definitions for driver USBPSU */\r
+#define XPAR_XUSBPSU_NUM_INSTANCES 1\r
+\r
+/* Definitions for peripheral PSU_USB_0 */\r
+#define XPAR_PSU_USB_0_DEVICE_ID 0\r
+#define XPAR_PSU_USB_0_BASEADDR 0xFE200000\r
+#define XPAR_PSU_USB_0_HIGHADDR 0xFE20FFFF\r
+\r
+\r
+/******************************************************************/\r
+\r
+/* Canonical definitions for peripheral PSU_USB_0 */\r
+#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_0_DEVICE_ID\r
+#define XPAR_XUSBPSU_0_BASEADDR 0xFE200000\r
+#define XPAR_XUSBPSU_0_HIGHADDR 0xFE20FFFF\r
+\r
+\r
/******************************************************************/\r
\r
/* Definitions for driver WDTPS */\r
#define XPAR_PSU_WDT_0_DEVICE_ID 0\r
#define XPAR_PSU_WDT_0_BASEADDR 0xFF150000\r
#define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF\r
-#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 25000000\r
+#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99999001\r
\r
\r
/* Definitions for peripheral PSU_WDT_1 */\r
#define XPAR_PSU_WDT_1_DEVICE_ID 1\r
#define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000\r
#define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF\r
-#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 25000000\r
+#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99999001\r
\r
\r
/******************************************************************/\r
#define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID\r
#define XPAR_XWDTPS_0_BASEADDR 0xFF150000\r
#define XPAR_XWDTPS_0_HIGHADDR 0xFF15FFFF\r
-#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 25000000\r
+#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 99999001\r
\r
/* Canonical definitions for peripheral PSU_WDT_1 */\r
#define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID\r
#define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000\r
#define XPAR_XWDTPS_1_HIGHADDR 0xFD4DFFFF\r
-#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 25000000\r
+#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99999001\r
\r
\r
/******************************************************************/\r
projects / freertos / blobdiff