--- /dev/null
+ResetHalt\r
+\r
+; Set VBR to the beginning of what will be SRAM\r
+; VBR is an absolute CPU register\r
+writecontrolreg 0x0801 0x20000000\r
+\r
+; Set RAMBAR1 (SRAM)\r
+writecontrolreg 0x0C05 0x20000021\r
+\r
+; Set FLASHBAR (Flash)\r
+writecontrolreg 0x0C04 0x00000061\r
+\r
+; Enable PST[3:0] signals\r
+writemem.b 0x40100074 0x0F\r