+++ /dev/null
-/* Coldfire C Header File\r
- * Copyright Freescale Semiconductor Inc\r
- * All rights reserved.\r
- *\r
- * 2007/03/19 Revision: 0.9\r
- */\r
-\r
-#ifndef __MCF5282_RCM_H__\r
-#define __MCF5282_RCM_H__\r
-\r
-\r
-/*********************************************************************\r
-*\r
-* Reset Controller Module (RCM)\r
-*\r
-*********************************************************************/\r
-\r
-/* Register read/write macros */\r
-#define MCF_RCM_RCR (*(vuint8 *)(&__IPSBAR[0x110000]))\r
-#define MCF_RCM_RSR (*(vuint8 *)(&__IPSBAR[0x110001]))\r
-\r
-\r
-/* Bit definitions and macros for MCF_RCM_RCR */\r
-#define MCF_RCM_RCR_LVDE (0x1)\r
-#define MCF_RCM_RCR_LVDRE (0x4)\r
-#define MCF_RCM_RCR_LVDIE (0x8)\r
-#define MCF_RCM_RCR_LVDF (0x10)\r
-#define MCF_RCM_RCR_FRCRSTOUT (0x40)\r
-#define MCF_RCM_RCR_SOFTRST (0x80)\r
-\r
-/* Bit definitions and macros for MCF_RCM_RSR */\r
-#define MCF_RCM_RSR_LOL (0x1)\r
-#define MCF_RCM_RSR_LOC (0x2)\r
-#define MCF_RCM_RSR_EXT (0x4)\r
-#define MCF_RCM_RSR_POR (0x8)\r
-#define MCF_RCM_RSR_WDR (0x10)\r
-#define MCF_RCM_RSR_SOFT (0x20)\r
-#define MCF_RCM_RSR_LVD (0x40)\r
-\r
-\r
-#endif /* __MCF5282_RCM_H__ */\r