--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+/********************************************************************\r
+*\r
+* Standard register and bit definitions for the Texas Instruments\r
+* MSP430 microcontroller.\r
+*\r
+* This file supports assembler and C development for\r
+* MSP430FR5XX_FR6XXGENERIC device.\r
+*\r
+* Texas Instruments, Version 1.0\r
+*\r
+* Rev. 1.0, Setup\r
+*\r
+*\r
+********************************************************************/\r
+\r
+#ifndef __msp430FR5XX_FR6XXGENERIC\r
+#define __msp430FR5XX_FR6XXGENERIC\r
+\r
+//#define __MSP430_HEADER_VERSION__ 1125\r
+\r
+#ifdef __IAR_SYSTEMS_ICC__\r
+#ifndef _SYSTEM_BUILD\r
+#pragma system_include\r
+#endif\r
+#endif\r
+\r
+#if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */\r
+#error msp430fr5xx_6xxgeneric.h file for use with ICC430/A430 only\r
+#endif\r
+\r
+\r
+#ifdef __IAR_SYSTEMS_ICC__\r
+#include "in430.h"\r
+#pragma language=extended\r
+\r
+#define DEFC(name, address) __no_init volatile unsigned char name @ address;\r
+#define DEFW(name, address) __no_init volatile unsigned short name @ address;\r
+\r
+#define DEFCW(name, address) __no_init union \\r
+{ \\r
+ struct \\r
+ { \\r
+ volatile unsigned char name##_L; \\r
+ volatile unsigned char name##_H; \\r
+ }; \\r
+ volatile unsigned short name; \\r
+} @ address;\r
+\r
+#define READ_ONLY_DEFCW(name, address) __no_init union \\r
+{ \\r
+ struct \\r
+ { \\r
+ volatile READ_ONLY unsigned char name##_L; \\r
+ volatile READ_ONLY unsigned char name##_H; \\r
+ }; \\r
+ volatile READ_ONLY unsigned short name; \\r
+} @ address;\r
+\r
+\r
+#if __REGISTER_MODEL__ == __REGISTER_MODEL_REG20__\r
+#define __ACCESS_20BIT_REG__ void __data20 * volatile\r
+#else\r
+#define __ACCESS_20BIT_REG__ volatile unsigned short /* only short access from C is allowed in small memory model */\r
+#endif\r
+\r
+#define DEFA(name, address) __no_init union \\r
+{ \\r
+ struct \\r
+ { \\r
+ volatile unsigned char name##_L; \\r
+ volatile unsigned char name##_H; \\r
+ }; \\r
+ struct \\r
+ { \\r
+ volatile unsigned short name##L; \\r
+ volatile unsigned short name##H; \\r
+ }; \\r
+ __ACCESS_20BIT_REG__ name; \\r
+} @ address;\r
+\r
+#endif /* __IAR_SYSTEMS_ICC__ */\r
+\r
+\r
+#ifdef __IAR_SYSTEMS_ASM__\r
+#define DEFC(name, address) sfrb name = address;\r
+#define DEFW(name, address) sfrw name = address;\r
+\r
+#define DEFCW(name, address) sfrbw name, name##_L, name##_H, address;\r
+sfrbw macro name, name_L, name_H, address;\r
+sfrb name_L = address;\r
+sfrb name_H = address+1;\r
+sfrw name = address;\r
+ endm\r
+\r
+#define READ_ONLY_DEFCW(name, address) const_sfrbw name, name##_L, name##_H, address;\r
+const_sfrbw macro name, name_L, name_H, address;\r
+const sfrb name_L = address;\r
+const sfrb name_H = address+1;\r
+const sfrw name = address;\r
+ endm\r
+\r
+#define DEFA(name, address) sfrba name, name##L, name##H, name##_L, name##_H, address;\r
+sfrba macro name, nameL, nameH, name_L, name_H, address;\r
+sfrb name_L = address;\r
+sfrb name_H = address+1;\r
+sfrw nameL = address;\r
+sfrw nameH = address+2;\r
+sfrl name = address;\r
+ endm\r
+\r
+#endif /* __IAR_SYSTEMS_ASM__*/\r
+\r
+#ifdef __cplusplus\r
+#define READ_ONLY\r
+#else\r
+#define READ_ONLY const\r
+#endif\r
+\r
+/************************************************************\r
+* STANDARD BITS\r
+************************************************************/\r
+\r
+#define BIT0 (0x0001u)\r
+#define BIT1 (0x0002u)\r
+#define BIT2 (0x0004u)\r
+#define BIT3 (0x0008u)\r
+#define BIT4 (0x0010u)\r
+#define BIT5 (0x0020u)\r
+#define BIT6 (0x0040u)\r
+#define BIT7 (0x0080u)\r
+#define BIT8 (0x0100u)\r
+#define BIT9 (0x0200u)\r
+#define BITA (0x0400u)\r
+#define BITB (0x0800u)\r
+#define BITC (0x1000u)\r
+#define BITD (0x2000u)\r
+#define BITE (0x4000u)\r
+#define BITF (0x8000u)\r
+\r
+/************************************************************\r
+* STATUS REGISTER BITS\r
+************************************************************/\r
+\r
+#define C (0x0001u)\r
+#define Z (0x0002u)\r
+#define N (0x0004u)\r
+#define V (0x0100u)\r
+#define GIE (0x0008u)\r
+#define CPUOFF (0x0010u)\r
+#define OSCOFF (0x0020u)\r
+#define SCG0 (0x0040u)\r
+#define SCG1 (0x0080u)\r
+\r
+/* Low Power Modes coded with Bits 4-7 in SR */\r
+\r
+#ifndef __IAR_SYSTEMS_ICC__ /* Begin #defines for assembler */\r
+#define LPM0 (CPUOFF)\r
+#define LPM1 (SCG0+CPUOFF)\r
+#define LPM2 (SCG1+CPUOFF)\r
+#define LPM3 (SCG1+SCG0+CPUOFF)\r
+#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)\r
+/* End #defines for assembler */\r
+\r
+#else /* Begin #defines for C */\r
+#define LPM0_bits (CPUOFF)\r
+#define LPM1_bits (SCG0+CPUOFF)\r
+#define LPM2_bits (SCG1+CPUOFF)\r
+#define LPM3_bits (SCG1+SCG0+CPUOFF)\r
+#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)\r
+\r
+#include "in430.h"\r
+\r
+#if __MSP430_HEADER_VERSION__ < 1107\r
+#define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */\r
+#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */\r
+#define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */\r
+#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */\r
+#define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */\r
+#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */\r
+#define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */\r
+#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */\r
+#define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */\r
+#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */\r
+#else\r
+#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */\r
+#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */\r
+#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */\r
+#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */\r
+#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */\r
+#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */\r
+#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */\r
+#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */\r
+#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */\r
+#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */\r
+#endif\r
+#endif /* End #defines for C */\r
+\r
+/************************************************************\r
+* CPU\r
+************************************************************/\r
+#define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */\r
+\r
+#if defined(__MSP430_HAS_T0A2__) || defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T2A2__) || defined(__MSP430_HAS_T3A2__) \\r
+ || defined(__MSP430_HAS_T0A3__) || defined(__MSP430_HAS_T1A3__) || defined(__MSP430_HAS_T2A3__) || defined(__MSP430_HAS_T3A3__) \\r
+ || defined(__MSP430_HAS_T0A5__) || defined(__MSP430_HAS_T1A5__) || defined(__MSP430_HAS_T2A5__) || defined(__MSP430_HAS_T3A5__) \\r
+ || defined(__MSP430_HAS_T0A7__) || defined(__MSP430_HAS_T1A7__) || defined(__MSP430_HAS_T2A7__) || defined(__MSP430_HAS_T3A7__)\r
+ #define __MSP430_HAS_TxA7__\r
+#endif\r
+#if defined(__MSP430_HAS_T0B3__) || defined(__MSP430_HAS_T0B5__) || defined(__MSP430_HAS_T0B7__) \\r
+ || defined(__MSP430_HAS_T1B3__) || defined(__MSP430_HAS_T1B5__) || defined(__MSP430_HAS_T1B7__)\r
+ #define __MSP430_HAS_TxB7__\r
+#endif\r
+#if defined(__MSP430_HAS_T0D3__) || defined(__MSP430_HAS_T0D5__) || defined(__MSP430_HAS_T0D7__) \\r
+ || defined(__MSP430_HAS_T1D3__) || defined(__MSP430_HAS_T1D5__) || defined(__MSP430_HAS_T1D7__)\r
+ #define __MSP430_HAS_TxD7__\r
+#endif\r
+#if defined(__MSP430_HAS_USCI_A0__) || defined(__MSP430_HAS_USCI_A1__) || defined(__MSP430_HAS_USCI_A2__) || defined(__MSP430_HAS_USCI_A3__)\r
+ #define __MSP430_HAS_USCI_Ax__\r
+#endif\r
+#if defined(__MSP430_HAS_USCI_B0__) || defined(__MSP430_HAS_USCI_B1__) || defined(__MSP430_HAS_USCI_B2__) || defined(__MSP430_HAS_USCI_B3__)\r
+ #define __MSP430_HAS_USCI_Bx__\r
+#endif\r
+#if defined(__MSP430_HAS_EUSCI_A0__) || defined(__MSP430_HAS_EUSCI_A1__) || defined(__MSP430_HAS_EUSCI_A2__) || defined(__MSP430_HAS_EUSCI_A3__)\r
+ #define __MSP430_HAS_EUSCI_Ax__\r
+#endif\r
+#if defined(__MSP430_HAS_EUSCI_B0__) || defined(__MSP430_HAS_EUSCI_B1__) || defined(__MSP430_HAS_EUSCI_B2__) || defined(__MSP430_HAS_EUSCI_B3__)\r
+ #define __MSP430_HAS_EUSCI_Bx__\r
+#endif\r
+#ifdef __MSP430_HAS_EUSCI_B0__\r
+ #define __MSP430_HAS_EUSCI_Bx__\r
+#endif\r
+\r
+/************************************************************\r
+* ADC12_B\r
+************************************************************/\r
+#ifdef __MSP430_HAS_ADC12_B__ /* Definition to show that Module is available */\r
+\r
+#define OFS_ADC12CTL0 (0x0000u) /* ADC12 B Control 0 */\r
+#define OFS_ADC12CTL0_L OFS_ADC12CTL0\r
+#define OFS_ADC12CTL0_H OFS_ADC12CTL0+1\r
+#define OFS_ADC12CTL1 (0x0002u) /* ADC12 B Control 1 */\r
+#define OFS_ADC12CTL1_L OFS_ADC12CTL1\r
+#define OFS_ADC12CTL1_H OFS_ADC12CTL1+1\r
+#define OFS_ADC12CTL2 (0x0004u) /* ADC12 B Control 2 */\r
+#define OFS_ADC12CTL2_L OFS_ADC12CTL2\r
+#define OFS_ADC12CTL2_H OFS_ADC12CTL2+1\r
+#define OFS_ADC12CTL3 (0x0006u) /* ADC12 B Control 3 */\r
+#define OFS_ADC12CTL3_L OFS_ADC12CTL3\r
+#define OFS_ADC12CTL3_H OFS_ADC12CTL3+1\r
+#define OFS_ADC12LO (0x0008u) /* ADC12 B Window Comparator High Threshold */\r
+#define OFS_ADC12LO_L OFS_ADC12LO\r
+#define OFS_ADC12LO_H OFS_ADC12LO+1\r
+#define OFS_ADC12HI (0x000Au) /* ADC12 B Window Comparator High Threshold */\r
+#define OFS_ADC12HI_L OFS_ADC12HI\r
+#define OFS_ADC12HI_H OFS_ADC12HI+1\r
+#define OFS_ADC12IFGR0 (0x000Cu) /* ADC12 B Interrupt Flag 0 */\r
+#define OFS_ADC12IFGR0_L OFS_ADC12IFGR0\r
+#define OFS_ADC12IFGR0_H OFS_ADC12IFGR0+1\r
+#define OFS_ADC12IFGR1 (0x000Eu) /* ADC12 B Interrupt Flag 1 */\r
+#define OFS_ADC12IFGR1_L OFS_ADC12IFGR1\r
+#define OFS_ADC12IFGR1_H OFS_ADC12IFGR1+1\r
+#define OFS_ADC12IFGR2 (0x0010u) /* ADC12 B Interrupt Flag 2 */\r
+#define OFS_ADC12IFGR2_L OFS_ADC12IFGR2\r
+#define OFS_ADC12IFGR2_H OFS_ADC12IFGR2+1\r
+#define OFS_ADC12IER0 (0x0012u) /* ADC12 B Interrupt Enable 0 */\r
+#define OFS_ADC12IER0_L OFS_ADC12IER0\r
+#define OFS_ADC12IER0_H OFS_ADC12IER0+1\r
+#define OFS_ADC12IER1 (0x0014u) /* ADC12 B Interrupt Enable 1 */\r
+#define OFS_ADC12IER1_L OFS_ADC12IER1\r
+#define OFS_ADC12IER1_H OFS_ADC12IER1+1\r
+#define OFS_ADC12IER2 (0x0016u) /* ADC12 B Interrupt Enable 2 */\r
+#define OFS_ADC12IER2_L OFS_ADC12IER2\r
+#define OFS_ADC12IER2_H OFS_ADC12IER2+1\r
+#define OFS_ADC12IV (0x0018u) /* ADC12 B Interrupt Vector Word */\r
+#define OFS_ADC12IV_L OFS_ADC12IV\r
+#define OFS_ADC12IV_H OFS_ADC12IV+1\r
+\r
+#define OFS_ADC12MCTL0 (0x0020u) /* ADC12 Memory Control 0 */\r
+#define OFS_ADC12MCTL0_L OFS_ADC12MCTL0\r
+#define OFS_ADC12MCTL0_H OFS_ADC12MCTL0+1\r
+#define OFS_ADC12MCTL1 (0x0022u) /* ADC12 Memory Control 1 */\r
+#define OFS_ADC12MCTL1_L OFS_ADC12MCTL1\r
+#define OFS_ADC12MCTL1_H OFS_ADC12MCTL1+1\r
+#define OFS_ADC12MCTL2 (0x0024u) /* ADC12 Memory Control 2 */\r
+#define OFS_ADC12MCTL2_L OFS_ADC12MCTL2\r
+#define OFS_ADC12MCTL2_H OFS_ADC12MCTL2+1\r
+#define OFS_ADC12MCTL3 (0x0026u) /* ADC12 Memory Control 3 */\r
+#define OFS_ADC12MCTL3_L OFS_ADC12MCTL3\r
+#define OFS_ADC12MCTL3_H OFS_ADC12MCTL3+1\r
+#define OFS_ADC12MCTL4 (0x0028u) /* ADC12 Memory Control 4 */\r
+#define OFS_ADC12MCTL4_L OFS_ADC12MCTL4\r
+#define OFS_ADC12MCTL4_H OFS_ADC12MCTL4+1\r
+#define OFS_ADC12MCTL5 (0x002Au) /* ADC12 Memory Control 5 */\r
+#define OFS_ADC12MCTL5_L OFS_ADC12MCTL5\r
+#define OFS_ADC12MCTL5_H OFS_ADC12MCTL5+1\r
+#define OFS_ADC12MCTL6 (0x002Cu) /* ADC12 Memory Control 6 */\r
+#define OFS_ADC12MCTL6_L OFS_ADC12MCTL6\r
+#define OFS_ADC12MCTL6_H OFS_ADC12MCTL6+1\r
+#define OFS_ADC12MCTL7 (0x002Eu) /* ADC12 Memory Control 7 */\r
+#define OFS_ADC12MCTL7_L OFS_ADC12MCTL7\r
+#define OFS_ADC12MCTL7_H OFS_ADC12MCTL7+1\r
+#define OFS_ADC12MCTL8 (0x0030u) /* ADC12 Memory Control 8 */\r
+#define OFS_ADC12MCTL8_L OFS_ADC12MCTL8\r
+#define OFS_ADC12MCTL8_H OFS_ADC12MCTL8+1\r
+#define OFS_ADC12MCTL9 (0x0032u) /* ADC12 Memory Control 9 */\r
+#define OFS_ADC12MCTL9_L OFS_ADC12MCTL9\r
+#define OFS_ADC12MCTL9_H OFS_ADC12MCTL9+1\r
+#define OFS_ADC12MCTL10 (0x0034u) /* ADC12 Memory Control 10 */\r
+#define OFS_ADC12MCTL10_L OFS_ADC12MCTL10\r
+#define OFS_ADC12MCTL10_H OFS_ADC12MCTL10+1\r
+#define OFS_ADC12MCTL11 (0x0036u) /* ADC12 Memory Control 11 */\r
+#define OFS_ADC12MCTL11_L OFS_ADC12MCTL11\r
+#define OFS_ADC12MCTL11_H OFS_ADC12MCTL11+1\r
+#define OFS_ADC12MCTL12 (0x0038u) /* ADC12 Memory Control 12 */\r
+#define OFS_ADC12MCTL12_L OFS_ADC12MCTL12\r
+#define OFS_ADC12MCTL12_H OFS_ADC12MCTL12+1\r
+#define OFS_ADC12MCTL13 (0x003Au) /* ADC12 Memory Control 13 */\r
+#define OFS_ADC12MCTL13_L OFS_ADC12MCTL13\r
+#define OFS_ADC12MCTL13_H OFS_ADC12MCTL13+1\r
+#define OFS_ADC12MCTL14 (0x003Cu) /* ADC12 Memory Control 14 */\r
+#define OFS_ADC12MCTL14_L OFS_ADC12MCTL14\r
+#define OFS_ADC12MCTL14_H OFS_ADC12MCTL14+1\r
+#define OFS_ADC12MCTL15 (0x003Eu) /* ADC12 Memory Control 15 */\r
+#define OFS_ADC12MCTL15_L OFS_ADC12MCTL15\r
+#define OFS_ADC12MCTL15_H OFS_ADC12MCTL15+1\r
+#define OFS_ADC12MCTL16 (0x0040u) /* ADC12 Memory Control 16 */\r
+#define OFS_ADC12MCTL16_L OFS_ADC12MCTL16\r
+#define OFS_ADC12MCTL16_H OFS_ADC12MCTL16+1\r
+#define OFS_ADC12MCTL17 (0x0042u) /* ADC12 Memory Control 17 */\r
+#define OFS_ADC12MCTL17_L OFS_ADC12MCTL17\r
+#define OFS_ADC12MCTL17_H OFS_ADC12MCTL17+1\r
+#define OFS_ADC12MCTL18 (0x0044u) /* ADC12 Memory Control 18 */\r
+#define OFS_ADC12MCTL18_L OFS_ADC12MCTL18\r
+#define OFS_ADC12MCTL18_H OFS_ADC12MCTL18+1\r
+#define OFS_ADC12MCTL19 (0x0046u) /* ADC12 Memory Control 19 */\r
+#define OFS_ADC12MCTL19_L OFS_ADC12MCTL19\r
+#define OFS_ADC12MCTL19_H OFS_ADC12MCTL19+1\r
+#define OFS_ADC12MCTL20 (0x0048u) /* ADC12 Memory Control 20 */\r
+#define OFS_ADC12MCTL20_L OFS_ADC12MCTL20\r
+#define OFS_ADC12MCTL20_H OFS_ADC12MCTL20+1\r
+#define OFS_ADC12MCTL21 (0x004Au) /* ADC12 Memory Control 21 */\r
+#define OFS_ADC12MCTL21_L OFS_ADC12MCTL21\r
+#define OFS_ADC12MCTL21_H OFS_ADC12MCTL21+1\r
+#define OFS_ADC12MCTL22 (0x004Cu) /* ADC12 Memory Control 22 */\r
+#define OFS_ADC12MCTL22_L OFS_ADC12MCTL22\r
+#define OFS_ADC12MCTL22_H OFS_ADC12MCTL22+1\r
+#define OFS_ADC12MCTL23 (0x004Eu) /* ADC12 Memory Control 23 */\r
+#define OFS_ADC12MCTL23_L OFS_ADC12MCTL23\r
+#define OFS_ADC12MCTL23_H OFS_ADC12MCTL23+1\r
+#define OFS_ADC12MCTL24 (0x0050u) /* ADC12 Memory Control 24 */\r
+#define OFS_ADC12MCTL24_L OFS_ADC12MCTL24\r
+#define OFS_ADC12MCTL24_H OFS_ADC12MCTL24+1\r
+#define OFS_ADC12MCTL25 (0x0052u) /* ADC12 Memory Control 25 */\r
+#define OFS_ADC12MCTL25_L OFS_ADC12MCTL25\r
+#define OFS_ADC12MCTL25_H OFS_ADC12MCTL25+1\r
+#define OFS_ADC12MCTL26 (0x0054u) /* ADC12 Memory Control 26 */\r
+#define OFS_ADC12MCTL26_L OFS_ADC12MCTL26\r
+#define OFS_ADC12MCTL26_H OFS_ADC12MCTL26+1\r
+#define OFS_ADC12MCTL27 (0x0056u) /* ADC12 Memory Control 27 */\r
+#define OFS_ADC12MCTL27_L OFS_ADC12MCTL27\r
+#define OFS_ADC12MCTL27_H OFS_ADC12MCTL27+1\r
+#define OFS_ADC12MCTL28 (0x0058u) /* ADC12 Memory Control 28 */\r
+#define OFS_ADC12MCTL28_L OFS_ADC12MCTL28\r
+#define OFS_ADC12MCTL28_H OFS_ADC12MCTL28+1\r
+#define OFS_ADC12MCTL29 (0x005Au) /* ADC12 Memory Control 29 */\r
+#define OFS_ADC12MCTL29_L OFS_ADC12MCTL29\r
+#define OFS_ADC12MCTL29_H OFS_ADC12MCTL29+1\r
+#define OFS_ADC12MCTL30 (0x005Cu) /* ADC12 Memory Control 30 */\r
+#define OFS_ADC12MCTL30_L OFS_ADC12MCTL30\r
+#define OFS_ADC12MCTL30_H OFS_ADC12MCTL30+1\r
+#define OFS_ADC12MCTL31 (0x005Eu) /* ADC12 Memory Control 31 */\r
+#define OFS_ADC12MCTL31_L OFS_ADC12MCTL31\r
+#define OFS_ADC12MCTL31_H OFS_ADC12MCTL31+1\r
+#define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */\r
+#ifndef __IAR_SYSTEMS_ICC__\r
+#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */\r
+#else\r
+#define ADC12MCTL ((char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */\r
+#endif\r
+\r
+#define OFS_ADC12MEM0 (0x0060u) /* ADC12 Conversion Memory 0 */\r
+#define OFS_ADC12MEM0_L OFS_ADC12MEM0\r
+#define OFS_ADC12MEM0_H OFS_ADC12MEM0+1\r
+#define OFS_ADC12MEM1 (0x0062u) /* ADC12 Conversion Memory 1 */\r
+#define OFS_ADC12MEM1_L OFS_ADC12MEM1\r
+#define OFS_ADC12MEM1_H OFS_ADC12MEM1+1\r
+#define OFS_ADC12MEM2 (0x0064u) /* ADC12 Conversion Memory 2 */\r
+#define OFS_ADC12MEM2_L OFS_ADC12MEM2\r
+#define OFS_ADC12MEM2_H OFS_ADC12MEM2+1\r
+#define OFS_ADC12MEM3 (0x0066u) /* ADC12 Conversion Memory 3 */\r
+#define OFS_ADC12MEM3_L OFS_ADC12MEM3\r
+#define OFS_ADC12MEM3_H OFS_ADC12MEM3+1\r
+#define OFS_ADC12MEM4 (0x0068u) /* ADC12 Conversion Memory 4 */\r
+#define OFS_ADC12MEM4_L OFS_ADC12MEM4\r
+#define OFS_ADC12MEM4_H OFS_ADC12MEM4+1\r
+#define OFS_ADC12MEM5 (0x006Au) /* ADC12 Conversion Memory 5 */\r
+#define OFS_ADC12MEM5_L OFS_ADC12MEM5\r
+#define OFS_ADC12MEM5_H OFS_ADC12MEM5+1\r
+#define OFS_ADC12MEM6 (0x006Cu) /* ADC12 Conversion Memory 6 */\r
+#define OFS_ADC12MEM6_L OFS_ADC12MEM6\r
+#define OFS_ADC12MEM6_H OFS_ADC12MEM6+1\r
+#define OFS_ADC12MEM7 (0x006Eu) /* ADC12 Conversion Memory 7 */\r
+#define OFS_ADC12MEM7_L OFS_ADC12MEM7\r
+#define OFS_ADC12MEM7_H OFS_ADC12MEM7+1\r
+#define OFS_ADC12MEM8 (0x0070u) /* ADC12 Conversion Memory 8 */\r
+#define OFS_ADC12MEM8_L OFS_ADC12MEM8\r
+#define OFS_ADC12MEM8_H OFS_ADC12MEM8+1\r
+#define OFS_ADC12MEM9 (0x0072u) /* ADC12 Conversion Memory 9 */\r
+#define OFS_ADC12MEM9_L OFS_ADC12MEM9\r
+#define OFS_ADC12MEM9_H OFS_ADC12MEM9+1\r
+#define OFS_ADC12MEM10 (0x0074u) /* ADC12 Conversion Memory 10 */\r
+#define OFS_ADC12MEM10_L OFS_ADC12MEM10\r
+#define OFS_ADC12MEM10_H OFS_ADC12MEM10+1\r
+#define OFS_ADC12MEM11 (0x0076u) /* ADC12 Conversion Memory 11 */\r
+#define OFS_ADC12MEM11_L OFS_ADC12MEM11\r
+#define OFS_ADC12MEM11_H OFS_ADC12MEM11+1\r
+#define OFS_ADC12MEM12 (0x0078u) /* ADC12 Conversion Memory 12 */\r
+#define OFS_ADC12MEM12_L OFS_ADC12MEM12\r
+#define OFS_ADC12MEM12_H OFS_ADC12MEM12+1\r
+#define OFS_ADC12MEM13 (0x007Au) /* ADC12 Conversion Memory 13 */\r
+#define OFS_ADC12MEM13_L OFS_ADC12MEM13\r
+#define OFS_ADC12MEM13_H OFS_ADC12MEM13+1\r
+#define OFS_ADC12MEM14 (0x007Cu) /* ADC12 Conversion Memory 14 */\r
+#define OFS_ADC12MEM14_L OFS_ADC12MEM14\r
+#define OFS_ADC12MEM14_H OFS_ADC12MEM14+1\r
+#define OFS_ADC12MEM15 (0x007Eu) /* ADC12 Conversion Memory 15 */\r
+#define OFS_ADC12MEM15_L OFS_ADC12MEM15\r
+#define OFS_ADC12MEM15_H OFS_ADC12MEM15+1\r
+#define OFS_ADC12MEM16 (0x0080u) /* ADC12 Conversion Memory 16 */\r
+#define OFS_ADC12MEM16_L OFS_ADC12MEM16\r
+#define OFS_ADC12MEM16_H OFS_ADC12MEM16+1\r
+#define OFS_ADC12MEM17 (0x0082u) /* ADC12 Conversion Memory 17 */\r
+#define OFS_ADC12MEM17_L OFS_ADC12MEM17\r
+#define OFS_ADC12MEM17_H OFS_ADC12MEM17+1\r
+#define OFS_ADC12MEM18 (0x0084u) /* ADC12 Conversion Memory 18 */\r
+#define OFS_ADC12MEM18_L OFS_ADC12MEM18\r
+#define OFS_ADC12MEM18_H OFS_ADC12MEM18+1\r
+#define OFS_ADC12MEM19 (0x0086u) /* ADC12 Conversion Memory 19 */\r
+#define OFS_ADC12MEM19_L OFS_ADC12MEM19\r
+#define OFS_ADC12MEM19_H OFS_ADC12MEM19+1\r
+#define OFS_ADC12MEM20 (0x0088u) /* ADC12 Conversion Memory 20 */\r
+#define OFS_ADC12MEM20_L OFS_ADC12MEM20\r
+#define OFS_ADC12MEM20_H OFS_ADC12MEM20+1\r
+#define OFS_ADC12MEM21 (0x008Au) /* ADC12 Conversion Memory 21 */\r
+#define OFS_ADC12MEM21_L OFS_ADC12MEM21\r
+#define OFS_ADC12MEM21_H OFS_ADC12MEM21+1\r
+#define OFS_ADC12MEM22 (0x008Cu) /* ADC12 Conversion Memory 22 */\r
+#define OFS_ADC12MEM22_L OFS_ADC12MEM22\r
+#define OFS_ADC12MEM22_H OFS_ADC12MEM22+1\r
+#define OFS_ADC12MEM23 (0x008Eu) /* ADC12 Conversion Memory 23 */\r
+#define OFS_ADC12MEM23_L OFS_ADC12MEM23\r
+#define OFS_ADC12MEM23_H OFS_ADC12MEM23+1\r
+#define OFS_ADC12MEM24 (0x0090u) /* ADC12 Conversion Memory 24 */\r
+#define OFS_ADC12MEM24_L OFS_ADC12MEM24\r
+#define OFS_ADC12MEM24_H OFS_ADC12MEM24+1\r
+#define OFS_ADC12MEM25 (0x0092u) /* ADC12 Conversion Memory 25 */\r
+#define OFS_ADC12MEM25_L OFS_ADC12MEM25\r
+#define OFS_ADC12MEM25_H OFS_ADC12MEM25+1\r
+#define OFS_ADC12MEM26 (0x0094u) /* ADC12 Conversion Memory 26 */\r
+#define OFS_ADC12MEM26_L OFS_ADC12MEM26\r
+#define OFS_ADC12MEM26_H OFS_ADC12MEM26+1\r
+#define OFS_ADC12MEM27 (0x0096u) /* ADC12 Conversion Memory 27 */\r
+#define OFS_ADC12MEM27_L OFS_ADC12MEM27\r
+#define OFS_ADC12MEM27_H OFS_ADC12MEM27+1\r
+#define OFS_ADC12MEM28 (0x0098u) /* ADC12 Conversion Memory 28 */\r
+#define OFS_ADC12MEM28_L OFS_ADC12MEM28\r
+#define OFS_ADC12MEM28_H OFS_ADC12MEM28+1\r
+#define OFS_ADC12MEM29 (0x009Au) /* ADC12 Conversion Memory 29 */\r
+#define OFS_ADC12MEM29_L OFS_ADC12MEM29\r
+#define OFS_ADC12MEM29_H OFS_ADC12MEM29+1\r
+#define OFS_ADC12MEM30 (0x009Cu) /* ADC12 Conversion Memory 30 */\r
+#define OFS_ADC12MEM30_L OFS_ADC12MEM30\r
+#define OFS_ADC12MEM30_H OFS_ADC12MEM30+1\r
+#define OFS_ADC12MEM31 (0x009Eu) /* ADC12 Conversion Memory 31 */\r
+#define OFS_ADC12MEM31_L OFS_ADC12MEM31\r
+#define OFS_ADC12MEM31_H OFS_ADC12MEM31+1\r
+#define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */\r
+#ifndef __IAR_SYSTEMS_ICC__\r
+#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */\r
+#else\r
+#define ADC12MEM ((int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */\r
+#endif\r
+\r
+/* ADC12CTL0 Control Bits */\r
+#define ADC12SC (0x0001u) /* ADC12 Start Conversion */\r
+#define ADC12ENC (0x0002u) /* ADC12 Enable Conversion */\r
+#define ADC12ON (0x0010u) /* ADC12 On/enable */\r
+#define ADC12MSC (0x0080u) /* ADC12 Multiple SampleConversion */\r
+#define ADC12SHT00 (0x0100u) /* ADC12 Sample Hold 0 Select Bit: 0 */\r
+#define ADC12SHT01 (0x0200u) /* ADC12 Sample Hold 0 Select Bit: 1 */\r
+#define ADC12SHT02 (0x0400u) /* ADC12 Sample Hold 0 Select Bit: 2 */\r
+#define ADC12SHT03 (0x0800u) /* ADC12 Sample Hold 0 Select Bit: 3 */\r
+#define ADC12SHT10 (0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */\r
+#define ADC12SHT11 (0x2000u) /* ADC12 Sample Hold 1 Select Bit: 1 */\r
+#define ADC12SHT12 (0x4000u) /* ADC12 Sample Hold 1 Select Bit: 2 */\r
+#define ADC12SHT13 (0x8000u) /* ADC12 Sample Hold 1 Select Bit: 3 */\r
+\r
+/* ADC12CTL0 Control Bits */\r
+#define ADC12SC_L (0x0001u) /* ADC12 Start Conversion */\r
+#define ADC12ENC_L (0x0002u) /* ADC12 Enable Conversion */\r
+#define ADC12ON_L (0x0010u) /* ADC12 On/enable */\r
+#define ADC12MSC_L (0x0080u) /* ADC12 Multiple SampleConversion */\r
+\r
+/* ADC12CTL0 Control Bits */\r
+#define ADC12SHT00_H (0x0001u) /* ADC12 Sample Hold 0 Select Bit: 0 */\r
+#define ADC12SHT01_H (0x0002u) /* ADC12 Sample Hold 0 Select Bit: 1 */\r
+#define ADC12SHT02_H (0x0004u) /* ADC12 Sample Hold 0 Select Bit: 2 */\r
+#define ADC12SHT03_H (0x0008u) /* ADC12 Sample Hold 0 Select Bit: 3 */\r
+#define ADC12SHT10_H (0x0010u) /* ADC12 Sample Hold 1 Select Bit: 0 */\r
+#define ADC12SHT11_H (0x0020u) /* ADC12 Sample Hold 1 Select Bit: 1 */\r
+#define ADC12SHT12_H (0x0040u) /* ADC12 Sample Hold 1 Select Bit: 2 */\r
+#define ADC12SHT13_H (0x0080u) /* ADC12 Sample Hold 1 Select Bit: 3 */\r
+\r
+#define ADC12SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */\r
+#define ADC12SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */\r
+#define ADC12SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */\r
+#define ADC12SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */\r
+#define ADC12SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */\r
+#define ADC12SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */\r
+#define ADC12SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */\r
+#define ADC12SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */\r
+#define ADC12SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */\r
+#define ADC12SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */\r
+#define ADC12SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */\r
+#define ADC12SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */\r
+#define ADC12SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */\r
+#define ADC12SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */\r
+#define ADC12SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */\r
+#define ADC12SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */\r
+\r
+#define ADC12SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */\r
+#define ADC12SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */\r
+#define ADC12SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */\r
+#define ADC12SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */\r
+#define ADC12SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */\r
+#define ADC12SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */\r
+#define ADC12SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */\r
+#define ADC12SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */\r
+#define ADC12SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */\r
+#define ADC12SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */\r
+#define ADC12SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */\r
+#define ADC12SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */\r
+#define ADC12SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */\r
+#define ADC12SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */\r
+#define ADC12SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */\r
+#define ADC12SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */\r
+\r
+/* ADC12CTL1 Control Bits */\r
+#define ADC12BUSY (0x0001u) /* ADC12 Busy */\r
+#define ADC12CONSEQ0 (0x0002u) /* ADC12 Conversion Sequence Select Bit: 0 */\r
+#define ADC12CONSEQ1 (0x0004u) /* ADC12 Conversion Sequence Select Bit: 1 */\r
+#define ADC12SSEL0 (0x0008u) /* ADC12 Clock Source Select Bit: 0 */\r
+#define ADC12SSEL1 (0x0010u) /* ADC12 Clock Source Select Bit: 1 */\r
+#define ADC12DIV0 (0x0020u) /* ADC12 Clock Divider Select Bit: 0 */\r
+#define ADC12DIV1 (0x0040u) /* ADC12 Clock Divider Select Bit: 1 */\r
+#define ADC12DIV2 (0x0080u) /* ADC12 Clock Divider Select Bit: 2 */\r
+#define ADC12ISSH (0x0100u) /* ADC12 Invert Sample Hold Signal */\r
+#define ADC12SHP (0x0200u) /* ADC12 Sample/Hold Pulse Mode */\r
+#define ADC12SHS0 (0x0400u) /* ADC12 Sample/Hold Source Bit: 0 */\r
+#define ADC12SHS1 (0x0800u) /* ADC12 Sample/Hold Source Bit: 1 */\r
+#define ADC12SHS2 (0x1000u) /* ADC12 Sample/Hold Source Bit: 2 */\r
+#define ADC12PDIV0 (0x2000u) /* ADC12 Predivider Bit: 0 */\r
+#define ADC12PDIV1 (0x4000u) /* ADC12 Predivider Bit: 1 */\r
+\r
+/* ADC12CTL1 Control Bits */\r
+#define ADC12BUSY_L (0x0001u) /* ADC12 Busy */\r
+#define ADC12CONSEQ0_L (0x0002u) /* ADC12 Conversion Sequence Select Bit: 0 */\r
+#define ADC12CONSEQ1_L (0x0004u) /* ADC12 Conversion Sequence Select Bit: 1 */\r
+#define ADC12SSEL0_L (0x0008u) /* ADC12 Clock Source Select Bit: 0 */\r
+#define ADC12SSEL1_L (0x0010u) /* ADC12 Clock Source Select Bit: 1 */\r
+#define ADC12DIV0_L (0x0020u) /* ADC12 Clock Divider Select Bit: 0 */\r
+#define ADC12DIV1_L (0x0040u) /* ADC12 Clock Divider Select Bit: 1 */\r
+#define ADC12DIV2_L (0x0080u) /* ADC12 Clock Divider Select Bit: 2 */\r
+\r
+/* ADC12CTL1 Control Bits */\r
+#define ADC12ISSH_H (0x0001u) /* ADC12 Invert Sample Hold Signal */\r
+#define ADC12SHP_H (0x0002u) /* ADC12 Sample/Hold Pulse Mode */\r
+#define ADC12SHS0_H (0x0004u) /* ADC12 Sample/Hold Source Bit: 0 */\r
+#define ADC12SHS1_H (0x0008u) /* ADC12 Sample/Hold Source Bit: 1 */\r
+#define ADC12SHS2_H (0x0010u) /* ADC12 Sample/Hold Source Bit: 2 */\r
+#define ADC12PDIV0_H (0x0020u) /* ADC12 Predivider Bit: 0 */\r
+#define ADC12PDIV1_H (0x0040u) /* ADC12 Predivider Bit: 1 */\r
+\r
+#define ADC12CONSEQ_0 (0*0x0002u) /* ADC12 Conversion Sequence Select: 0 */\r
+#define ADC12CONSEQ_1 (1*0x0002u) /* ADC12 Conversion Sequence Select: 1 */\r
+#define ADC12CONSEQ_2 (2*0x0002u) /* ADC12 Conversion Sequence Select: 2 */\r
+#define ADC12CONSEQ_3 (3*0x0002u) /* ADC12 Conversion Sequence Select: 3 */\r
+\r
+#define ADC12SSEL_0 (0*0x0008u) /* ADC12 Clock Source Select: 0 */\r
+#define ADC12SSEL_1 (1*0x0008u) /* ADC12 Clock Source Select: 1 */\r
+#define ADC12SSEL_2 (2*0x0008u) /* ADC12 Clock Source Select: 2 */\r
+#define ADC12SSEL_3 (3*0x0008u) /* ADC12 Clock Source Select: 3 */\r
+\r
+#define ADC12DIV_0 (0*0x0020u) /* ADC12 Clock Divider Select: 0 */\r
+#define ADC12DIV_1 (1*0x0020u) /* ADC12 Clock Divider Select: 1 */\r
+#define ADC12DIV_2 (2*0x0020u) /* ADC12 Clock Divider Select: 2 */\r
+#define ADC12DIV_3 (3*0x0020u) /* ADC12 Clock Divider Select: 3 */\r
+#define ADC12DIV_4 (4*0x0020u) /* ADC12 Clock Divider Select: 4 */\r
+#define ADC12DIV_5 (5*0x0020u) /* ADC12 Clock Divider Select: 5 */\r
+#define ADC12DIV_6 (6*0x0020u) /* ADC12 Clock Divider Select: 6 */\r
+#define ADC12DIV_7 (7*0x0020u) /* ADC12 Clock Divider Select: 7 */\r
+\r
+#define ADC12SHS_0 (0*0x0400u) /* ADC12 Sample/Hold Source: 0 */\r
+#define ADC12SHS_1 (1*0x0400u) /* ADC12 Sample/Hold Source: 1 */\r
+#define ADC12SHS_2 (2*0x0400u) /* ADC12 Sample/Hold Source: 2 */\r
+#define ADC12SHS_3 (3*0x0400u) /* ADC12 Sample/Hold Source: 3 */\r
+#define ADC12SHS_4 (4*0x0400u) /* ADC12 Sample/Hold Source: 4 */\r
+#define ADC12SHS_5 (5*0x0400u) /* ADC12 Sample/Hold Source: 5 */\r
+#define ADC12SHS_6 (6*0x0400u) /* ADC12 Sample/Hold Source: 6 */\r
+#define ADC12SHS_7 (7*0x0400u) /* ADC12 Sample/Hold Source: 7 */\r
+\r
+#define ADC12PDIV_0 (0*0x2000u) /* ADC12 Clock predivider Select 0 */\r
+#define ADC12PDIV_1 (1*0x2000u) /* ADC12 Clock predivider Select 1 */\r
+#define ADC12PDIV_2 (2*0x2000u) /* ADC12 Clock predivider Select 2 */\r
+#define ADC12PDIV_3 (3*0x2000u) /* ADC12 Clock predivider Select 3 */\r
+#define ADC12PDIV__1 (0*0x2000u) /* ADC12 Clock predivider Select: /1 */\r
+#define ADC12PDIV__4 (1*0x2000u) /* ADC12 Clock predivider Select: /4 */\r
+#define ADC12PDIV__32 (2*0x2000u) /* ADC12 Clock predivider Select: /32 */\r
+#define ADC12PDIV__64 (3*0x2000u) /* ADC12 Clock predivider Select: /64 */\r
+\r
+/* ADC12CTL2 Control Bits */\r
+#define ADC12PWRMD (0x0001u) /* ADC12 Power Mode */\r
+#define ADC12DF (0x0008u) /* ADC12 Data Format */\r
+#define ADC12RES0 (0x0010u) /* ADC12 Resolution Bit: 0 */\r
+#define ADC12RES1 (0x0020u) /* ADC12 Resolution Bit: 1 */\r
+\r
+/* ADC12CTL2 Control Bits */\r
+#define ADC12PWRMD_L (0x0001u) /* ADC12 Power Mode */\r
+#define ADC12DF_L (0x0008u) /* ADC12 Data Format */\r
+#define ADC12RES0_L (0x0010u) /* ADC12 Resolution Bit: 0 */\r
+#define ADC12RES1_L (0x0020u) /* ADC12 Resolution Bit: 1 */\r
+\r
+#define ADC12RES_0 (0x0000u) /* ADC12+ Resolution : 8 Bit */\r
+#define ADC12RES_1 (0x0010u) /* ADC12+ Resolution : 10 Bit */\r
+#define ADC12RES_2 (0x0020u) /* ADC12+ Resolution : 12 Bit */\r
+#define ADC12RES_3 (0x0030u) /* ADC12+ Resolution : reserved */\r
+\r
+#define ADC12RES__8BIT (0x0000u) /* ADC12+ Resolution : 8 Bit */\r
+#define ADC12RES__10BIT (0x0010u) /* ADC12+ Resolution : 10 Bit */\r
+#define ADC12RES__12BIT (0x0020u) /* ADC12+ Resolution : 12 Bit */\r
+\r
+/* ADC12CTL3 Control Bits */\r
+#define ADC12CSTARTADD0 (0x0001u) /* ADC12 Conversion Start Address Bit: 0 */\r
+#define ADC12CSTARTADD1 (0x0002u) /* ADC12 Conversion Start Address Bit: 1 */\r
+#define ADC12CSTARTADD2 (0x0004u) /* ADC12 Conversion Start Address Bit: 2 */\r
+#define ADC12CSTARTADD3 (0x0008u) /* ADC12 Conversion Start Address Bit: 3 */\r
+#define ADC12CSTARTADD4 (0x0010u) /* ADC12 Conversion Start Address Bit: 4 */\r
+#define ADC12BATMAP (0x0040u) /* ADC12 Internal AVCC/2 select */\r
+#define ADC12TCMAP (0x0080u) /* ADC12 Internal TempSensor select */\r
+#define ADC12ICH0MAP (0x0100u) /* ADC12 Internal Channel 0 select */\r
+#define ADC12ICH1MAP (0x0200u) /* ADC12 Internal Channel 1 select */\r
+#define ADC12ICH2MAP (0x0400u) /* ADC12 Internal Channel 2 select */\r
+#define ADC12ICH3MAP (0x0800u) /* ADC12 Internal Channel 3 select */\r
+\r
+/* ADC12CTL3 Control Bits */\r
+#define ADC12CSTARTADD0_L (0x0001u) /* ADC12 Conversion Start Address Bit: 0 */\r
+#define ADC12CSTARTADD1_L (0x0002u) /* ADC12 Conversion Start Address Bit: 1 */\r
+#define ADC12CSTARTADD2_L (0x0004u) /* ADC12 Conversion Start Address Bit: 2 */\r
+#define ADC12CSTARTADD3_L (0x0008u) /* ADC12 Conversion Start Address Bit: 3 */\r
+#define ADC12CSTARTADD4_L (0x0010u) /* ADC12 Conversion Start Address Bit: 4 */\r
+#define ADC12BATMAP_L (0x0040u) /* ADC12 Internal AVCC/2 select */\r
+#define ADC12TCMAP_L (0x0080u) /* ADC12 Internal TempSensor select */\r
+\r
+/* ADC12CTL3 Control Bits */\r
+#define ADC12ICH0MAP_H (0x0001u) /* ADC12 Internal Channel 0 select */\r
+#define ADC12ICH1MAP_H (0x0002u) /* ADC12 Internal Channel 1 select */\r
+#define ADC12ICH2MAP_H (0x0004u) /* ADC12 Internal Channel 2 select */\r
+#define ADC12ICH3MAP_H (0x0008u) /* ADC12 Internal Channel 3 select */\r
+\r
+#define ADC12CSTARTADD_0 ( 0*0x0001u) /* ADC12 Conversion Start Address: 0 */\r
+#define ADC12CSTARTADD_1 ( 1*0x0001u) /* ADC12 Conversion Start Address: 1 */\r
+#define ADC12CSTARTADD_2 ( 2*0x0001u) /* ADC12 Conversion Start Address: 2 */\r
+#define ADC12CSTARTADD_3 ( 3*0x0001u) /* ADC12 Conversion Start Address: 3 */\r
+#define ADC12CSTARTADD_4 ( 4*0x0001u) /* ADC12 Conversion Start Address: 4 */\r
+#define ADC12CSTARTADD_5 ( 5*0x0001u) /* ADC12 Conversion Start Address: 5 */\r
+#define ADC12CSTARTADD_6 ( 6*0x0001u) /* ADC12 Conversion Start Address: 6 */\r
+#define ADC12CSTARTADD_7 ( 7*0x0001u) /* ADC12 Conversion Start Address: 7 */\r
+#define ADC12CSTARTADD_8 ( 8*0x0001u) /* ADC12 Conversion Start Address: 8 */\r
+#define ADC12CSTARTADD_9 ( 9*0x0001u) /* ADC12 Conversion Start Address: 9 */\r
+#define ADC12CSTARTADD_10 (10*0x0001u) /* ADC12 Conversion Start Address: 10 */\r
+#define ADC12CSTARTADD_11 (11*0x0001u) /* ADC12 Conversion Start Address: 11 */\r
+#define ADC12CSTARTADD_12 (12*0x0001u) /* ADC12 Conversion Start Address: 12 */\r
+#define ADC12CSTARTADD_13 (13*0x0001u) /* ADC12 Conversion Start Address: 13 */\r
+#define ADC12CSTARTADD_14 (14*0x0001u) /* ADC12 Conversion Start Address: 14 */\r
+#define ADC12CSTARTADD_15 (15*0x0001u) /* ADC12 Conversion Start Address: 15 */\r
+#define ADC12CSTARTADD_16 (16*0x0001u) /* ADC12 Conversion Start Address: 16 */\r
+#define ADC12CSTARTADD_17 (17*0x0001u) /* ADC12 Conversion Start Address: 17 */\r
+#define ADC12CSTARTADD_18 (18*0x0001u) /* ADC12 Conversion Start Address: 18 */\r
+#define ADC12CSTARTADD_19 (19*0x0001u) /* ADC12 Conversion Start Address: 19 */\r
+#define ADC12CSTARTADD_20 (20*0x0001u) /* ADC12 Conversion Start Address: 20 */\r
+#define ADC12CSTARTADD_21 (21*0x0001u) /* ADC12 Conversion Start Address: 21 */\r
+#define ADC12CSTARTADD_22 (22*0x0001u) /* ADC12 Conversion Start Address: 22 */\r
+#define ADC12CSTARTADD_23 (23*0x0001u) /* ADC12 Conversion Start Address: 23 */\r
+#define ADC12CSTARTADD_24 (24*0x0001u) /* ADC12 Conversion Start Address: 24 */\r
+#define ADC12CSTARTADD_25 (25*0x0001u) /* ADC12 Conversion Start Address: 25 */\r
+#define ADC12CSTARTADD_26 (26*0x0001u) /* ADC12 Conversion Start Address: 26 */\r
+#define ADC12CSTARTADD_27 (27*0x0001u) /* ADC12 Conversion Start Address: 27 */\r
+#define ADC12CSTARTADD_28 (28*0x0001u) /* ADC12 Conversion Start Address: 28 */\r
+#define ADC12CSTARTADD_29 (29*0x0001u) /* ADC12 Conversion Start Address: 29 */\r
+#define ADC12CSTARTADD_30 (30*0x0001u) /* ADC12 Conversion Start Address: 30 */\r
+#define ADC12CSTARTADD_31 (31*0x0001u) /* ADC12 Conversion Start Address: 31 */\r
+\r
+/* ADC12MCTLx Control Bits */\r
+#define ADC12INCH0 (0x0001u) /* ADC12 Input Channel Select Bit 0 */\r
+#define ADC12INCH1 (0x0002u) /* ADC12 Input Channel Select Bit 1 */\r
+#define ADC12INCH2 (0x0004u) /* ADC12 Input Channel Select Bit 2 */\r
+#define ADC12INCH3 (0x0008u) /* ADC12 Input Channel Select Bit 3 */\r
+#define ADC12INCH4 (0x0010u) /* ADC12 Input Channel Select Bit 4 */\r
+#define ADC12EOS (0x0080u) /* ADC12 End of Sequence */\r
+#define ADC12VRSEL0 (0x0100u) /* ADC12 VR Select Bit 0 */\r
+#define ADC12VRSEL1 (0x0200u) /* ADC12 VR Select Bit 1 */\r
+#define ADC12VRSEL2 (0x0400u) /* ADC12 VR Select Bit 2 */\r
+#define ADC12VRSEL3 (0x0800u) /* ADC12 VR Select Bit 3 */\r
+#define ADC12DIF (0x2000u) /* ADC12 Differential mode (only for even Registers) */\r
+#define ADC12WINC (0x4000u) /* ADC12 Comparator window enable */\r
+\r
+/* ADC12MCTLx Control Bits */\r
+#define ADC12INCH0_L (0x0001u) /* ADC12 Input Channel Select Bit 0 */\r
+#define ADC12INCH1_L (0x0002u) /* ADC12 Input Channel Select Bit 1 */\r
+#define ADC12INCH2_L (0x0004u) /* ADC12 Input Channel Select Bit 2 */\r
+#define ADC12INCH3_L (0x0008u) /* ADC12 Input Channel Select Bit 3 */\r
+#define ADC12INCH4_L (0x0010u) /* ADC12 Input Channel Select Bit 4 */\r
+#define ADC12EOS_L (0x0080u) /* ADC12 End of Sequence */\r
+\r
+/* ADC12MCTLx Control Bits */\r
+#define ADC12VRSEL0_H (0x0001u) /* ADC12 VR Select Bit 0 */\r
+#define ADC12VRSEL1_H (0x0002u) /* ADC12 VR Select Bit 1 */\r
+#define ADC12VRSEL2_H (0x0004u) /* ADC12 VR Select Bit 2 */\r
+#define ADC12VRSEL3_H (0x0008u) /* ADC12 VR Select Bit 3 */\r
+#define ADC12DIF_H (0x0020u) /* ADC12 Differential mode (only for even Registers) */\r
+#define ADC12WINC_H (0x0040u) /* ADC12 Comparator window enable */\r
+\r
+#define ADC12INCH_0 (0x0000u) /* ADC12 Input Channel 0 */\r
+#define ADC12INCH_1 (0x0001u) /* ADC12 Input Channel 1 */\r
+#define ADC12INCH_2 (0x0002u) /* ADC12 Input Channel 2 */\r
+#define ADC12INCH_3 (0x0003u) /* ADC12 Input Channel 3 */\r
+#define ADC12INCH_4 (0x0004u) /* ADC12 Input Channel 4 */\r
+#define ADC12INCH_5 (0x0005u) /* ADC12 Input Channel 5 */\r
+#define ADC12INCH_6 (0x0006u) /* ADC12 Input Channel 6 */\r
+#define ADC12INCH_7 (0x0007u) /* ADC12 Input Channel 7 */\r
+#define ADC12INCH_8 (0x0008u) /* ADC12 Input Channel 8 */\r
+#define ADC12INCH_9 (0x0009u) /* ADC12 Input Channel 9 */\r
+#define ADC12INCH_10 (0x000Au) /* ADC12 Input Channel 10 */\r
+#define ADC12INCH_11 (0x000Bu) /* ADC12 Input Channel 11 */\r
+#define ADC12INCH_12 (0x000Cu) /* ADC12 Input Channel 12 */\r
+#define ADC12INCH_13 (0x000Du) /* ADC12 Input Channel 13 */\r
+#define ADC12INCH_14 (0x000Eu) /* ADC12 Input Channel 14 */\r
+#define ADC12INCH_15 (0x000Fu) /* ADC12 Input Channel 15 */\r
+#define ADC12INCH_16 (0x0010u) /* ADC12 Input Channel 16 */\r
+#define ADC12INCH_17 (0x0011u) /* ADC12 Input Channel 17 */\r
+#define ADC12INCH_18 (0x0012u) /* ADC12 Input Channel 18 */\r
+#define ADC12INCH_19 (0x0013u) /* ADC12 Input Channel 19 */\r
+#define ADC12INCH_20 (0x0014u) /* ADC12 Input Channel 20 */\r
+#define ADC12INCH_21 (0x0015u) /* ADC12 Input Channel 21 */\r
+#define ADC12INCH_22 (0x0016u) /* ADC12 Input Channel 22 */\r
+#define ADC12INCH_23 (0x0017u) /* ADC12 Input Channel 23 */\r
+#define ADC12INCH_24 (0x0018u) /* ADC12 Input Channel 24 */\r
+#define ADC12INCH_25 (0x0019u) /* ADC12 Input Channel 25 */\r
+#define ADC12INCH_26 (0x001Au) /* ADC12 Input Channel 26 */\r
+#define ADC12INCH_27 (0x001Bu) /* ADC12 Input Channel 27 */\r
+#define ADC12INCH_28 (0x001Cu) /* ADC12 Input Channel 28 */\r
+#define ADC12INCH_29 (0x001Du) /* ADC12 Input Channel 29 */\r
+#define ADC12INCH_30 (0x001Eu) /* ADC12 Input Channel 30 */\r
+#define ADC12INCH_31 (0x001Fu) /* ADC12 Input Channel 31 */\r
+\r
+#define ADC12VRSEL_0 (0*0x100u) /* ADC12 Select Reference 0 */\r
+#define ADC12VRSEL_1 (1*0x100u) /* ADC12 Select Reference 1 */\r
+#define ADC12VRSEL_2 (2*0x100u) /* ADC12 Select Reference 2 */\r
+#define ADC12VRSEL_3 (3*0x100u) /* ADC12 Select Reference 3 */\r
+#define ADC12VRSEL_4 (4*0x100u) /* ADC12 Select Reference 4 */\r
+#define ADC12VRSEL_5 (5*0x100u) /* ADC12 Select Reference 5 */\r
+#define ADC12VRSEL_6 (6*0x100u) /* ADC12 Select Reference 6 */\r
+#define ADC12VRSEL_7 (7*0x100u) /* ADC12 Select Reference 7 */\r
+#define ADC12VRSEL_8 (8*0x100u) /* ADC12 Select Reference 8 */\r
+#define ADC12VRSEL_9 (9*0x100u) /* ADC12 Select Reference 9 */\r
+#define ADC12VRSEL_10 (10*0x100u) /* ADC12 Select Reference 10 */\r
+#define ADC12VRSEL_11 (11*0x100u) /* ADC12 Select Reference 11 */\r
+#define ADC12VRSEL_12 (12*0x100u) /* ADC12 Select Reference 12 */\r
+#define ADC12VRSEL_13 (13*0x100u) /* ADC12 Select Reference 13 */\r
+#define ADC12VRSEL_14 (14*0x100u) /* ADC12 Select Reference 14 */\r
+#define ADC12VRSEL_15 (15*0x100u) /* ADC12 Select Reference 15 */\r
+\r
+/* ADC12HI Control Bits */\r
+\r
+/* ADC12LO Control Bits */\r
+\r
+/* ADC12IER0 Control Bits */\r
+#define ADC12IE0 (0x0001u) /* ADC12 Memory 0 Interrupt Enable */\r
+#define ADC12IE1 (0x0002u) /* ADC12 Memory 1 Interrupt Enable */\r
+#define ADC12IE2 (0x0004u) /* ADC12 Memory 2 Interrupt Enable */\r
+#define ADC12IE3 (0x0008u) /* ADC12 Memory 3 Interrupt Enable */\r
+#define ADC12IE4 (0x0010u) /* ADC12 Memory 4 Interrupt Enable */\r
+#define ADC12IE5 (0x0020u) /* ADC12 Memory 5 Interrupt Enable */\r
+#define ADC12IE6 (0x0040u) /* ADC12 Memory 6 Interrupt Enable */\r
+#define ADC12IE7 (0x0080u) /* ADC12 Memory 7 Interrupt Enable */\r
+#define ADC12IE8 (0x0100u) /* ADC12 Memory 8 Interrupt Enable */\r
+#define ADC12IE9 (0x0200u) /* ADC12 Memory 9 Interrupt Enable */\r
+#define ADC12IE10 (0x0400u) /* ADC12 Memory 10 Interrupt Enable */\r
+#define ADC12IE11 (0x0800u) /* ADC12 Memory 11 Interrupt Enable */\r
+#define ADC12IE12 (0x1000u) /* ADC12 Memory 12 Interrupt Enable */\r
+#define ADC12IE13 (0x2000u) /* ADC12 Memory 13 Interrupt Enable */\r
+#define ADC12IE14 (0x4000u) /* ADC12 Memory 14 Interrupt Enable */\r
+#define ADC12IE15 (0x8000u) /* ADC12 Memory 15 Interrupt Enable */\r
+\r
+/* ADC12IER0 Control Bits */\r
+#define ADC12IE0_L (0x0001u) /* ADC12 Memory 0 Interrupt Enable */\r
+#define ADC12IE1_L (0x0002u) /* ADC12 Memory 1 Interrupt Enable */\r
+#define ADC12IE2_L (0x0004u) /* ADC12 Memory 2 Interrupt Enable */\r
+#define ADC12IE3_L (0x0008u) /* ADC12 Memory 3 Interrupt Enable */\r
+#define ADC12IE4_L (0x0010u) /* ADC12 Memory 4 Interrupt Enable */\r
+#define ADC12IE5_L (0x0020u) /* ADC12 Memory 5 Interrupt Enable */\r
+#define ADC12IE6_L (0x0040u) /* ADC12 Memory 6 Interrupt Enable */\r
+#define ADC12IE7_L (0x0080u) /* ADC12 Memory 7 Interrupt Enable */\r
+\r
+/* ADC12IER0 Control Bits */\r
+#define ADC12IE8_H (0x0001u) /* ADC12 Memory 8 Interrupt Enable */\r
+#define ADC12IE9_H (0x0002u) /* ADC12 Memory 9 Interrupt Enable */\r
+#define ADC12IE10_H (0x0004u) /* ADC12 Memory 10 Interrupt Enable */\r
+#define ADC12IE11_H (0x0008u) /* ADC12 Memory 11 Interrupt Enable */\r
+#define ADC12IE12_H (0x0010u) /* ADC12 Memory 12 Interrupt Enable */\r
+#define ADC12IE13_H (0x0020u) /* ADC12 Memory 13 Interrupt Enable */\r
+#define ADC12IE14_H (0x0040u) /* ADC12 Memory 14 Interrupt Enable */\r
+#define ADC12IE15_H (0x0080u) /* ADC12 Memory 15 Interrupt Enable */\r
+\r
+/* ADC12IER1 Control Bits */\r
+#define ADC12IE16 (0x0001u) /* ADC12 Memory 16 Interrupt Enable */\r
+#define ADC12IE17 (0x0002u) /* ADC12 Memory 17 Interrupt Enable */\r
+#define ADC12IE18 (0x0004u) /* ADC12 Memory 18 Interrupt Enable */\r
+#define ADC12IE19 (0x0008u) /* ADC12 Memory 19 Interrupt Enable */\r
+#define ADC12IE20 (0x0010u) /* ADC12 Memory 20 Interrupt Enable */\r
+#define ADC12IE21 (0x0020u) /* ADC12 Memory 21 Interrupt Enable */\r
+#define ADC12IE22 (0x0040u) /* ADC12 Memory 22 Interrupt Enable */\r
+#define ADC12IE23 (0x0080u) /* ADC12 Memory 23 Interrupt Enable */\r
+#define ADC12IE24 (0x0100u) /* ADC12 Memory 24 Interrupt Enable */\r
+#define ADC12IE25 (0x0200u) /* ADC12 Memory 25 Interrupt Enable */\r
+#define ADC12IE26 (0x0400u) /* ADC12 Memory 26 Interrupt Enable */\r
+#define ADC12IE27 (0x0800u) /* ADC12 Memory 27 Interrupt Enable */\r
+#define ADC12IE28 (0x1000u) /* ADC12 Memory 28 Interrupt Enable */\r
+#define ADC12IE29 (0x2000u) /* ADC12 Memory 29 Interrupt Enable */\r
+#define ADC12IE30 (0x4000u) /* ADC12 Memory 30 Interrupt Enable */\r
+#define ADC12IE31 (0x8000u) /* ADC12 Memory 31 Interrupt Enable */\r
+\r
+/* ADC12IER1 Control Bits */\r
+#define ADC12IE16_L (0x0001u) /* ADC12 Memory 16 Interrupt Enable */\r
+#define ADC12IE17_L (0x0002u) /* ADC12 Memory 17 Interrupt Enable */\r
+#define ADC12IE18_L (0x0004u) /* ADC12 Memory 18 Interrupt Enable */\r
+#define ADC12IE19_L (0x0008u) /* ADC12 Memory 19 Interrupt Enable */\r
+#define ADC12IE20_L (0x0010u) /* ADC12 Memory 20 Interrupt Enable */\r
+#define ADC12IE21_L (0x0020u) /* ADC12 Memory 21 Interrupt Enable */\r
+#define ADC12IE22_L (0x0040u) /* ADC12 Memory 22 Interrupt Enable */\r
+#define ADC12IE23_L (0x0080u) /* ADC12 Memory 23 Interrupt Enable */\r
+\r
+/* ADC12IER1 Control Bits */\r
+#define ADC12IE24_H (0x0001u) /* ADC12 Memory 24 Interrupt Enable */\r
+#define ADC12IE25_H (0x0002u) /* ADC12 Memory 25 Interrupt Enable */\r
+#define ADC12IE26_H (0x0004u) /* ADC12 Memory 26 Interrupt Enable */\r
+#define ADC12IE27_H (0x0008u) /* ADC12 Memory 27 Interrupt Enable */\r
+#define ADC12IE28_H (0x0010u) /* ADC12 Memory 28 Interrupt Enable */\r
+#define ADC12IE29_H (0x0020u) /* ADC12 Memory 29 Interrupt Enable */\r
+#define ADC12IE30_H (0x0040u) /* ADC12 Memory 30 Interrupt Enable */\r
+#define ADC12IE31_H (0x0080u) /* ADC12 Memory 31 Interrupt Enable */\r
+\r
+/* ADC12IER2 Control Bits */\r
+#define ADC12INIE (0x0002u) /* ADC12 Interrupt enable for the inside of window of the Window comparator */\r
+#define ADC12LOIE (0x0004u) /* ADC12 Interrupt enable for lower threshold of the Window comparator */\r
+#define ADC12HIIE (0x0008u) /* ADC12 Interrupt enable for upper threshold of the Window comparator */\r
+#define ADC12OVIE (0x0010u) /* ADC12 ADC12MEMx Overflow interrupt enable */\r
+#define ADC12TOVIE (0x0020u) /* ADC12 Timer Overflow interrupt enable */\r
+#define ADC12RDYIE (0x0040u) /* ADC12 local buffered reference ready interrupt enable */\r
+\r
+/* ADC12IER2 Control Bits */\r
+#define ADC12INIE_L (0x0002u) /* ADC12 Interrupt enable for the inside of window of the Window comparator */\r
+#define ADC12LOIE_L (0x0004u) /* ADC12 Interrupt enable for lower threshold of the Window comparator */\r
+#define ADC12HIIE_L (0x0008u) /* ADC12 Interrupt enable for upper threshold of the Window comparator */\r
+#define ADC12OVIE_L (0x0010u) /* ADC12 ADC12MEMx Overflow interrupt enable */\r
+#define ADC12TOVIE_L (0x0020u) /* ADC12 Timer Overflow interrupt enable */\r
+#define ADC12RDYIE_L (0x0040u) /* ADC12 local buffered reference ready interrupt enable */\r
+\r
+/* ADC12IFGR0 Control Bits */\r
+#define ADC12IFG0 (0x0001u) /* ADC12 Memory 0 Interrupt Flag */\r
+#define ADC12IFG1 (0x0002u) /* ADC12 Memory 1 Interrupt Flag */\r
+#define ADC12IFG2 (0x0004u) /* ADC12 Memory 2 Interrupt Flag */\r
+#define ADC12IFG3 (0x0008u) /* ADC12 Memory 3 Interrupt Flag */\r
+#define ADC12IFG4 (0x0010u) /* ADC12 Memory 4 Interrupt Flag */\r
+#define ADC12IFG5 (0x0020u) /* ADC12 Memory 5 Interrupt Flag */\r
+#define ADC12IFG6 (0x0040u) /* ADC12 Memory 6 Interrupt Flag */\r
+#define ADC12IFG7 (0x0080u) /* ADC12 Memory 7 Interrupt Flag */\r
+#define ADC12IFG8 (0x0100u) /* ADC12 Memory 8 Interrupt Flag */\r
+#define ADC12IFG9 (0x0200u) /* ADC12 Memory 9 Interrupt Flag */\r
+#define ADC12IFG10 (0x0400u) /* ADC12 Memory 10 Interrupt Flag */\r
+#define ADC12IFG11 (0x0800u) /* ADC12 Memory 11 Interrupt Flag */\r
+#define ADC12IFG12 (0x1000u) /* ADC12 Memory 12 Interrupt Flag */\r
+#define ADC12IFG13 (0x2000u) /* ADC12 Memory 13 Interrupt Flag */\r
+#define ADC12IFG14 (0x4000u) /* ADC12 Memory 14 Interrupt Flag */\r
+#define ADC12IFG15 (0x8000u) /* ADC12 Memory 15 Interrupt Flag */\r
+\r
+/* ADC12IFGR0 Control Bits */\r
+#define ADC12IFG0_L (0x0001u) /* ADC12 Memory 0 Interrupt Flag */\r
+#define ADC12IFG1_L (0x0002u) /* ADC12 Memory 1 Interrupt Flag */\r
+#define ADC12IFG2_L (0x0004u) /* ADC12 Memory 2 Interrupt Flag */\r
+#define ADC12IFG3_L (0x0008u) /* ADC12 Memory 3 Interrupt Flag */\r
+#define ADC12IFG4_L (0x0010u) /* ADC12 Memory 4 Interrupt Flag */\r
+#define ADC12IFG5_L (0x0020u) /* ADC12 Memory 5 Interrupt Flag */\r
+#define ADC12IFG6_L (0x0040u) /* ADC12 Memory 6 Interrupt Flag */\r
+#define ADC12IFG7_L (0x0080u) /* ADC12 Memory 7 Interrupt Flag */\r
+\r
+/* ADC12IFGR0 Control Bits */\r
+#define ADC12IFG8_H (0x0001u) /* ADC12 Memory 8 Interrupt Flag */\r
+#define ADC12IFG9_H (0x0002u) /* ADC12 Memory 9 Interrupt Flag */\r
+#define ADC12IFG10_H (0x0004u) /* ADC12 Memory 10 Interrupt Flag */\r
+#define ADC12IFG11_H (0x0008u) /* ADC12 Memory 11 Interrupt Flag */\r
+#define ADC12IFG12_H (0x0010u) /* ADC12 Memory 12 Interrupt Flag */\r
+#define ADC12IFG13_H (0x0020u) /* ADC12 Memory 13 Interrupt Flag */\r
+#define ADC12IFG14_H (0x0040u) /* ADC12 Memory 14 Interrupt Flag */\r
+#define ADC12IFG15_H (0x0080u) /* ADC12 Memory 15 Interrupt Flag */\r
+\r
+/* ADC12IFGR1 Control Bits */\r
+#define ADC12IFG16 (0x0001u) /* ADC12 Memory 16 Interrupt Flag */\r
+#define ADC12IFG17 (0x0002u) /* ADC12 Memory 17 Interrupt Flag */\r
+#define ADC12IFG18 (0x0004u) /* ADC12 Memory 18 Interrupt Flag */\r
+#define ADC12IFG19 (0x0008u) /* ADC12 Memory 19 Interrupt Flag */\r
+#define ADC12IFG20 (0x0010u) /* ADC12 Memory 20 Interrupt Flag */\r
+#define ADC12IFG21 (0x0020u) /* ADC12 Memory 21 Interrupt Flag */\r
+#define ADC12IFG22 (0x0040u) /* ADC12 Memory 22 Interrupt Flag */\r
+#define ADC12IFG23 (0x0080u) /* ADC12 Memory 23 Interrupt Flag */\r
+#define ADC12IFG24 (0x0100u) /* ADC12 Memory 24 Interrupt Flag */\r
+#define ADC12IFG25 (0x0200u) /* ADC12 Memory 25 Interrupt Flag */\r
+#define ADC12IFG26 (0x0400u) /* ADC12 Memory 26 Interrupt Flag */\r
+#define ADC12IFG27 (0x0800u) /* ADC12 Memory 27 Interrupt Flag */\r
+#define ADC12IFG28 (0x1000u) /* ADC12 Memory 28 Interrupt Flag */\r
+#define ADC12IFG29 (0x2000u) /* ADC12 Memory 29 Interrupt Flag */\r
+#define ADC12IFG30 (0x4000u) /* ADC12 Memory 30 Interrupt Flag */\r
+#define ADC12IFG31 (0x8000u) /* ADC12 Memory 31 Interrupt Flag */\r
+\r
+/* ADC12IFGR1 Control Bits */\r
+#define ADC12IFG16_L (0x0001u) /* ADC12 Memory 16 Interrupt Flag */\r
+#define ADC12IFG17_L (0x0002u) /* ADC12 Memory 17 Interrupt Flag */\r
+#define ADC12IFG18_L (0x0004u) /* ADC12 Memory 18 Interrupt Flag */\r
+#define ADC12IFG19_L (0x0008u) /* ADC12 Memory 19 Interrupt Flag */\r
+#define ADC12IFG20_L (0x0010u) /* ADC12 Memory 20 Interrupt Flag */\r
+#define ADC12IFG21_L (0x0020u) /* ADC12 Memory 21 Interrupt Flag */\r
+#define ADC12IFG22_L (0x0040u) /* ADC12 Memory 22 Interrupt Flag */\r
+#define ADC12IFG23_L (0x0080u) /* ADC12 Memory 23 Interrupt Flag */\r
+\r
+/* ADC12IFGR1 Control Bits */\r
+#define ADC12IFG24_H (0x0001u) /* ADC12 Memory 24 Interrupt Flag */\r
+#define ADC12IFG25_H (0x0002u) /* ADC12 Memory 25 Interrupt Flag */\r
+#define ADC12IFG26_H (0x0004u) /* ADC12 Memory 26 Interrupt Flag */\r
+#define ADC12IFG27_H (0x0008u) /* ADC12 Memory 27 Interrupt Flag */\r
+#define ADC12IFG28_H (0x0010u) /* ADC12 Memory 28 Interrupt Flag */\r
+#define ADC12IFG29_H (0x0020u) /* ADC12 Memory 29 Interrupt Flag */\r
+#define ADC12IFG30_H (0x0040u) /* ADC12 Memory 30 Interrupt Flag */\r
+#define ADC12IFG31_H (0x0080u) /* ADC12 Memory 31 Interrupt Flag */\r
+\r
+/* ADC12IFGR2 Control Bits */\r
+#define ADC12INIFG (0x0002u) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */\r
+#define ADC12LOIFG (0x0004u) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */\r
+#define ADC12HIIFG (0x0008u) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */\r
+#define ADC12OVIFG (0x0010u) /* ADC12 ADC12MEMx Overflow interrupt Flag */\r
+#define ADC12TOVIFG (0x0020u) /* ADC12 Timer Overflow interrupt Flag */\r
+#define ADC12RDYIFG (0x0040u) /* ADC12 local buffered reference ready interrupt Flag */\r
+\r
+/* ADC12IFGR2 Control Bits */\r
+#define ADC12INIFG_L (0x0002u) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */\r
+#define ADC12LOIFG_L (0x0004u) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */\r
+#define ADC12HIIFG_L (0x0008u) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */\r
+#define ADC12OVIFG_L (0x0010u) /* ADC12 ADC12MEMx Overflow interrupt Flag */\r
+#define ADC12TOVIFG_L (0x0020u) /* ADC12 Timer Overflow interrupt Flag */\r
+#define ADC12RDYIFG_L (0x0040u) /* ADC12 local buffered reference ready interrupt Flag */\r
+\r
+/* ADC12IV Definitions */\r
+#define ADC12IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define ADC12IV_ADC12OVIFG (0x0002u) /* ADC12OVIFG */\r
+#define ADC12IV_ADC12TOVIFG (0x0004u) /* ADC12TOVIFG */\r
+#define ADC12IV_ADC12HIIFG (0x0006u) /* ADC12HIIFG */\r
+#define ADC12IV_ADC12LOIFG (0x0008u) /* ADC12LOIFG */\r
+#define ADC12IV_ADC12INIFG (0x000Au) /* ADC12INIFG */\r
+#define ADC12IV_ADC12IFG0 (0x000Cu) /* ADC12IFG0 */\r
+#define ADC12IV_ADC12IFG1 (0x000Eu) /* ADC12IFG1 */\r
+#define ADC12IV_ADC12IFG2 (0x0010u) /* ADC12IFG2 */\r
+#define ADC12IV_ADC12IFG3 (0x0012u) /* ADC12IFG3 */\r
+#define ADC12IV_ADC12IFG4 (0x0014u) /* ADC12IFG4 */\r
+#define ADC12IV_ADC12IFG5 (0x0016u) /* ADC12IFG5 */\r
+#define ADC12IV_ADC12IFG6 (0x0018u) /* ADC12IFG6 */\r
+#define ADC12IV_ADC12IFG7 (0x001Au) /* ADC12IFG7 */\r
+#define ADC12IV_ADC12IFG8 (0x001Cu) /* ADC12IFG8 */\r
+#define ADC12IV_ADC12IFG9 (0x001Eu) /* ADC12IFG9 */\r
+#define ADC12IV_ADC12IFG10 (0x0020u) /* ADC12IFG10 */\r
+#define ADC12IV_ADC12IFG11 (0x0022u) /* ADC12IFG11 */\r
+#define ADC12IV_ADC12IFG12 (0x0024u) /* ADC12IFG12 */\r
+#define ADC12IV_ADC12IFG13 (0x0026u) /* ADC12IFG13 */\r
+#define ADC12IV_ADC12IFG14 (0x0028u) /* ADC12IFG14 */\r
+#define ADC12IV_ADC12IFG15 (0x002Au) /* ADC12IFG15 */\r
+#define ADC12IV_ADC12IFG16 (0x002Cu) /* ADC12IFG16 */\r
+#define ADC12IV_ADC12IFG17 (0x002Eu) /* ADC12IFG17 */\r
+#define ADC12IV_ADC12IFG18 (0x0030u) /* ADC12IFG18 */\r
+#define ADC12IV_ADC12IFG19 (0x0032u) /* ADC12IFG19 */\r
+#define ADC12IV_ADC12IFG20 (0x0034u) /* ADC12IFG20 */\r
+#define ADC12IV_ADC12IFG21 (0x0036u) /* ADC12IFG21 */\r
+#define ADC12IV_ADC12IFG22 (0x0038u) /* ADC12IFG22 */\r
+#define ADC12IV_ADC12IFG23 (0x003Au) /* ADC12IFG23 */\r
+#define ADC12IV_ADC12IFG24 (0x003Cu) /* ADC12IFG24 */\r
+#define ADC12IV_ADC12IFG25 (0x003Eu) /* ADC12IFG25 */\r
+#define ADC12IV_ADC12IFG26 (0x0040u) /* ADC12IFG26 */\r
+#define ADC12IV_ADC12IFG27 (0x0042u) /* ADC12IFG27 */\r
+#define ADC12IV_ADC12IFG28 (0x0044u) /* ADC12IFG28 */\r
+#define ADC12IV_ADC12IFG29 (0x0046u) /* ADC12IFG29 */\r
+#define ADC12IV_ADC12IFG30 (0x0048u) /* ADC12IFG30 */\r
+#define ADC12IV_ADC12IFG31 (0x004Au) /* ADC12IFG31 */\r
+#define ADC12IV_ADC12RDYIFG (0x004Cu) /* ADC12RDYIFG */\r
+\r
+\r
+#endif\r
+/************************************************************\r
+* AES256 Accelerator\r
+************************************************************/\r
+#ifdef __MSP430_HAS_AES256__ /* Definition to show that Module is available */\r
+\r
+#define OFS_AESACTL0 (0x0000u) /* AES accelerator control register 0 */\r
+#define OFS_AESACTL0_L OFS_AESACTL0\r
+#define OFS_AESACTL0_H OFS_AESACTL0+1\r
+#define OFS_AESACTL1 (0x0002u) /* AES accelerator control register 1 */\r
+#define OFS_AESACTL1_L OFS_AESACTL1\r
+#define OFS_AESACTL1_H OFS_AESACTL1+1\r
+#define OFS_AESASTAT (0x0004u) /* AES accelerator status register */\r
+#define OFS_AESASTAT_L OFS_AESASTAT\r
+#define OFS_AESASTAT_H OFS_AESASTAT+1\r
+#define OFS_AESAKEY (0x0006u) /* AES accelerator key register */\r
+#define OFS_AESAKEY_L OFS_AESAKEY\r
+#define OFS_AESAKEY_H OFS_AESAKEY+1\r
+#define OFS_AESADIN (0x0008u) /* AES accelerator data in register */\r
+#define OFS_AESADIN_L OFS_AESADIN\r
+#define OFS_AESADIN_H OFS_AESADIN+1\r
+#define OFS_AESADOUT (0x000Au) /* AES accelerator data out register */\r
+#define OFS_AESADOUT_L OFS_AESADOUT\r
+#define OFS_AESADOUT_H OFS_AESADOUT+1\r
+#define OFS_AESAXDIN (0x000Cu) /* AES accelerator XORed data in register */\r
+#define OFS_AESAXDIN_L OFS_AESAXDIN\r
+#define OFS_AESAXDIN_H OFS_AESAXDIN+1\r
+#define OFS_AESAXIN (0x000Eu) /* AES accelerator XORed data in register (no trigger) */\r
+#define OFS_AESAXIN_L OFS_AESAXIN\r
+#define OFS_AESAXIN_H OFS_AESAXIN+1\r
+\r
+/* AESACTL0 Control Bits */\r
+#define AESOP0 (0x0001u) /* AES Operation Bit: 0 */\r
+#define AESOP1 (0x0002u) /* AES Operation Bit: 1 */\r
+#define AESKL0 (0x0004u) /* AES Key length Bit: 0 */\r
+#define AESKL1 (0x0008u) /* AES Key length Bit: 1 */\r
+#define AESTRIG (0x0010u) /* AES Trigger Select */\r
+#define AESCM0 (0x0020u) /* AES Cipher mode select Bit: 0 */\r
+#define AESCM1 (0x0040u) /* AES Cipher mode select Bit: 1 */\r
+#define AESSWRST (0x0080u) /* AES Software Reset */\r
+#define AESRDYIFG (0x0100u) /* AES ready interrupt flag */\r
+#define AESERRFG (0x0800u) /* AES Error Flag */\r
+#define AESRDYIE (0x1000u) /* AES ready interrupt enable*/\r
+#define AESCMEN (0x8000u) /* AES DMA cipher mode enable*/\r
+\r
+/* AESACTL0 Control Bits */\r
+#define AESOP0_L (0x0001u) /* AES Operation Bit: 0 */\r
+#define AESOP1_L (0x0002u) /* AES Operation Bit: 1 */\r
+#define AESKL0_L (0x0004u) /* AES Key length Bit: 0 */\r
+#define AESKL1_L (0x0008u) /* AES Key length Bit: 1 */\r
+#define AESTRIG_L (0x0010u) /* AES Trigger Select */\r
+#define AESCM0_L (0x0020u) /* AES Cipher mode select Bit: 0 */\r
+#define AESCM1_L (0x0040u) /* AES Cipher mode select Bit: 1 */\r
+#define AESSWRST_L (0x0080u) /* AES Software Reset */\r
+\r
+/* AESACTL0 Control Bits */\r
+#define AESRDYIFG_H (0x0001u) /* AES ready interrupt flag */\r
+#define AESERRFG_H (0x0008u) /* AES Error Flag */\r
+#define AESRDYIE_H (0x0010u) /* AES ready interrupt enable*/\r
+#define AESCMEN_H (0x0080u) /* AES DMA cipher mode enable*/\r
+\r
+#define AESOP_0 (0x0000u) /* AES Operation: Encrypt */\r
+#define AESOP_1 (0x0001u) /* AES Operation: Decrypt (same Key) */\r
+#define AESOP_2 (0x0002u) /* AES Operation: Decrypt (frist round Key) */\r
+#define AESOP_3 (0x0003u) /* AES Operation: Generate first round Key */\r
+\r
+#define AESKL_0 (0x0000u) /* AES Key length: AES128 */\r
+#define AESKL_1 (0x0004u) /* AES Key length: AES192 */\r
+#define AESKL_2 (0x0008u) /* AES Key length: AES256 */\r
+#define AESKL__128 (0x0000u) /* AES Key length: AES128 */\r
+#define AESKL__192 (0x0004u) /* AES Key length: AES192 */\r
+#define AESKL__256 (0x0008u) /* AES Key length: AES256 */\r
+\r
+#define AESCM_0 (0x0000u) /* AES Cipher mode select: ECB */\r
+#define AESCM_1 (0x0020u) /* AES Cipher mode select: CBC */\r
+#define AESCM_2 (0x0040u) /* AES Cipher mode select: OFB */\r
+#define AESCM_3 (0x0060u) /* AES Cipher mode select: CFB */\r
+#define AESCM__ECB (0x0000u) /* AES Cipher mode select: ECB */\r
+#define AESCM__CBC (0x0020u) /* AES Cipher mode select: CBC */\r
+#define AESCM__OFB (0x0040u) /* AES Cipher mode select: OFB */\r
+#define AESCM__CFB (0x0060u) /* AES Cipher mode select: CFB */\r
+\r
+/* AESACTL1 Control Bits */\r
+#define AESBLKCNT0 (0x0001u) /* AES Cipher Block Counter Bit: 0 */\r
+#define AESBLKCNT1 (0x0002u) /* AES Cipher Block Counter Bit: 1 */\r
+#define AESBLKCNT2 (0x0004u) /* AES Cipher Block Counter Bit: 2 */\r
+#define AESBLKCNT3 (0x0008u) /* AES Cipher Block Counter Bit: 3 */\r
+#define AESBLKCNT4 (0x0010u) /* AES Cipher Block Counter Bit: 4 */\r
+#define AESBLKCNT5 (0x0020u) /* AES Cipher Block Counter Bit: 5 */\r
+#define AESBLKCNT6 (0x0040u) /* AES Cipher Block Counter Bit: 6 */\r
+#define AESBLKCNT7 (0x0080u) /* AES Cipher Block Counter Bit: 7 */\r
+\r
+/* AESACTL1 Control Bits */\r
+#define AESBLKCNT0_L (0x0001u) /* AES Cipher Block Counter Bit: 0 */\r
+#define AESBLKCNT1_L (0x0002u) /* AES Cipher Block Counter Bit: 1 */\r
+#define AESBLKCNT2_L (0x0004u) /* AES Cipher Block Counter Bit: 2 */\r
+#define AESBLKCNT3_L (0x0008u) /* AES Cipher Block Counter Bit: 3 */\r
+#define AESBLKCNT4_L (0x0010u) /* AES Cipher Block Counter Bit: 4 */\r
+#define AESBLKCNT5_L (0x0020u) /* AES Cipher Block Counter Bit: 5 */\r
+#define AESBLKCNT6_L (0x0040u) /* AES Cipher Block Counter Bit: 6 */\r
+#define AESBLKCNT7_L (0x0080u) /* AES Cipher Block Counter Bit: 7 */\r
+\r
+/* AESASTAT Control Bits */\r
+#define AESBUSY (0x0001u) /* AES Busy */\r
+#define AESKEYWR (0x0002u) /* AES All 16 bytes written to AESAKEY */\r
+#define AESDINWR (0x0004u) /* AES All 16 bytes written to AESADIN */\r
+#define AESDOUTRD (0x0008u) /* AES All 16 bytes read from AESADOUT */\r
+#define AESKEYCNT0 (0x0010u) /* AES Bytes written via AESAKEY Bit: 0 */\r
+#define AESKEYCNT1 (0x0020u) /* AES Bytes written via AESAKEY Bit: 1 */\r
+#define AESKEYCNT2 (0x0040u) /* AES Bytes written via AESAKEY Bit: 2 */\r
+#define AESKEYCNT3 (0x0080u) /* AES Bytes written via AESAKEY Bit: 3 */\r
+#define AESDINCNT0 (0x0100u) /* AES Bytes written via AESADIN Bit: 0 */\r
+#define AESDINCNT1 (0x0200u) /* AES Bytes written via AESADIN Bit: 1 */\r
+#define AESDINCNT2 (0x0400u) /* AES Bytes written via AESADIN Bit: 2 */\r
+#define AESDINCNT3 (0x0800u) /* AES Bytes written via AESADIN Bit: 3 */\r
+#define AESDOUTCNT0 (0x1000u) /* AES Bytes read via AESADOUT Bit: 0 */\r
+#define AESDOUTCNT1 (0x2000u) /* AES Bytes read via AESADOUT Bit: 1 */\r
+#define AESDOUTCNT2 (0x4000u) /* AES Bytes read via AESADOUT Bit: 2 */\r
+#define AESDOUTCNT3 (0x8000u) /* AES Bytes read via AESADOUT Bit: 3 */\r
+\r
+/* AESASTAT Control Bits */\r
+#define AESBUSY_L (0x0001u) /* AES Busy */\r
+#define AESKEYWR_L (0x0002u) /* AES All 16 bytes written to AESAKEY */\r
+#define AESDINWR_L (0x0004u) /* AES All 16 bytes written to AESADIN */\r
+#define AESDOUTRD_L (0x0008u) /* AES All 16 bytes read from AESADOUT */\r
+#define AESKEYCNT0_L (0x0010u) /* AES Bytes written via AESAKEY Bit: 0 */\r
+#define AESKEYCNT1_L (0x0020u) /* AES Bytes written via AESAKEY Bit: 1 */\r
+#define AESKEYCNT2_L (0x0040u) /* AES Bytes written via AESAKEY Bit: 2 */\r
+#define AESKEYCNT3_L (0x0080u) /* AES Bytes written via AESAKEY Bit: 3 */\r
+\r
+/* AESASTAT Control Bits */\r
+#define AESDINCNT0_H (0x0001u) /* AES Bytes written via AESADIN Bit: 0 */\r
+#define AESDINCNT1_H (0x0002u) /* AES Bytes written via AESADIN Bit: 1 */\r
+#define AESDINCNT2_H (0x0004u) /* AES Bytes written via AESADIN Bit: 2 */\r
+#define AESDINCNT3_H (0x0008u) /* AES Bytes written via AESADIN Bit: 3 */\r
+#define AESDOUTCNT0_H (0x0010u) /* AES Bytes read via AESADOUT Bit: 0 */\r
+#define AESDOUTCNT1_H (0x0020u) /* AES Bytes read via AESADOUT Bit: 1 */\r
+#define AESDOUTCNT2_H (0x0040u) /* AES Bytes read via AESADOUT Bit: 2 */\r
+#define AESDOUTCNT3_H (0x0080u) /* AES Bytes read via AESADOUT Bit: 3 */\r
+\r
+#endif\r
+/************************************************************\r
+* Capacitive_Touch_IO 0\r
+************************************************************/\r
+#ifdef __MSP430_HAS_CAP_TOUCH_IO_0__ /* Definition to show that Module is available */\r
+\r
+#define OFS_CAPTIO0CTL (0x000Eu) /* Capacitive_Touch_IO 0 control register */\r
+#define OFS_CAPTIO0CTL_L OFS_CAPTIO0CTL\r
+#define OFS_CAPTIO0CTL_H OFS_CAPTIO0CTL+1\r
+\r
+#define CAPSIO0CTL CAPTIO0CTL /* legacy define */\r
+\r
+/* CAPTIOxCTL Control Bits */\r
+#define CAPTIOPISEL0 (0x0002u) /* CapTouchIO Pin Select Bit: 0 */\r
+#define CAPTIOPISEL1 (0x0004u) /* CapTouchIO Pin Select Bit: 1 */\r
+#define CAPTIOPISEL2 (0x0008u) /* CapTouchIO Pin Select Bit: 2 */\r
+#define CAPTIOPOSEL0 (0x0010u) /* CapTouchIO Port Select Bit: 0 */\r
+#define CAPTIOPOSEL1 (0x0020u) /* CapTouchIO Port Select Bit: 1 */\r
+#define CAPTIOPOSEL2 (0x0040u) /* CapTouchIO Port Select Bit: 2 */\r
+#define CAPTIOPOSEL3 (0x0080u) /* CapTouchIO Port Select Bit: 3 */\r
+#define CAPTIOEN (0x0100u) /* CapTouchIO Enable */\r
+#define CAPTIO (0x0200u) /* CapTouchIO state */\r
+\r
+/* CAPTIOxCTL Control Bits */\r
+#define CAPTIOPISEL0_L (0x0002u) /* CapTouchIO Pin Select Bit: 0 */\r
+#define CAPTIOPISEL1_L (0x0004u) /* CapTouchIO Pin Select Bit: 1 */\r
+#define CAPTIOPISEL2_L (0x0008u) /* CapTouchIO Pin Select Bit: 2 */\r
+#define CAPTIOPOSEL0_L (0x0010u) /* CapTouchIO Port Select Bit: 0 */\r
+#define CAPTIOPOSEL1_L (0x0020u) /* CapTouchIO Port Select Bit: 1 */\r
+#define CAPTIOPOSEL2_L (0x0040u) /* CapTouchIO Port Select Bit: 2 */\r
+#define CAPTIOPOSEL3_L (0x0080u) /* CapTouchIO Port Select Bit: 3 */\r
+\r
+/* CAPTIOxCTL Control Bits */\r
+#define CAPTIOEN_H (0x0001u) /* CapTouchIO Enable */\r
+#define CAPTIO_H (0x0002u) /* CapTouchIO state */\r
+\r
+/* Legacy defines */\r
+#define CAPSIOPISEL0 (0x0002u) /* CapTouchIO Pin Select Bit: 0 */\r
+#define CAPSIOPISEL1 (0x0004u) /* CapTouchIO Pin Select Bit: 1 */\r
+#define CAPSIOPISEL2 (0x0008u) /* CapTouchIO Pin Select Bit: 2 */\r
+#define CAPSIOPOSEL0 (0x0010u) /* CapTouchIO Port Select Bit: 0 */\r
+#define CAPSIOPOSEL1 (0x0020u) /* CapTouchIO Port Select Bit: 1 */\r
+#define CAPSIOPOSEL2 (0x0040u) /* CapTouchIO Port Select Bit: 2 */\r
+#define CAPSIOPOSEL3 (0x0080u) /* CapTouchIO Port Select Bit: 3 */\r
+#define CAPSIOEN (0x0100u) /* CapTouchIO Enable */\r
+#define CAPSIO (0x0200u) /* CapTouchIO state */\r
+\r
+#endif\r
+/************************************************************\r
+* Capacitive_Touch_IO 1\r
+************************************************************/\r
+#ifdef __MSP430_HAS_CAP_TOUCH_IO_1__ /* Definition to show that Module is available */\r
+\r
+#define OFS_CAPTIO1CTL (0x000Eu) /* Capacitive_Touch_IO 1 control register */\r
+#define OFS_CAPTIO1CTL_L OFS_CAPTIO1CTL\r
+#define OFS_CAPTIO1CTL_H OFS_CAPTIO1CTL+1\r
+\r
+#define CAPSIO1CTL CAPTIO1CTL /* legacy define */\r
+\r
+#endif\r
+/************************************************************\r
+* Comparator E\r
+************************************************************/\r
+#ifdef __MSP430_HAS_COMP_E__ /* Definition to show that Module is available */\r
+\r
+#define OFS_CECTL0 (0x0000u) /* Comparator E Control Register 0 */\r
+#define OFS_CECTL0_L OFS_CECTL0\r
+#define OFS_CECTL0_H OFS_CECTL0+1\r
+#define OFS_CECTL1 (0x0002u) /* Comparator E Control Register 1 */\r
+#define OFS_CECTL1_L OFS_CECTL1\r
+#define OFS_CECTL1_H OFS_CECTL1+1\r
+#define OFS_CECTL2 (0x0004u) /* Comparator E Control Register 2 */\r
+#define OFS_CECTL2_L OFS_CECTL2\r
+#define OFS_CECTL2_H OFS_CECTL2+1\r
+#define OFS_CECTL3 (0x0006u) /* Comparator E Control Register 3 */\r
+#define OFS_CECTL3_L OFS_CECTL3\r
+#define OFS_CECTL3_H OFS_CECTL3+1\r
+#define OFS_CEINT (0x000Cu) /* Comparator E Interrupt Register */\r
+#define OFS_CEINT_L OFS_CEINT\r
+#define OFS_CEINT_H OFS_CEINT+1\r
+#define OFS_CEIV (0x000Eu) /* Comparator E Interrupt Vector Word */\r
+#define OFS_CEIV_L OFS_CEIV\r
+#define OFS_CEIV_H OFS_CEIV+1\r
+\r
+/* CECTL0 Control Bits */\r
+#define CEIPSEL0 (0x0001u) /* Comp. E Pos. Channel Input Select 0 */\r
+#define CEIPSEL1 (0x0002u) /* Comp. E Pos. Channel Input Select 1 */\r
+#define CEIPSEL2 (0x0004u) /* Comp. E Pos. Channel Input Select 2 */\r
+#define CEIPSEL3 (0x0008u) /* Comp. E Pos. Channel Input Select 3 */\r
+//#define RESERVED (0x0010u) /* Comp. E */\r
+//#define RESERVED (0x0020u) /* Comp. E */\r
+//#define RESERVED (0x0040u) /* Comp. E */\r
+#define CEIPEN (0x0080u) /* Comp. E Pos. Channel Input Enable */\r
+#define CEIMSEL0 (0x0100u) /* Comp. E Neg. Channel Input Select 0 */\r
+#define CEIMSEL1 (0x0200u) /* Comp. E Neg. Channel Input Select 1 */\r
+#define CEIMSEL2 (0x0400u) /* Comp. E Neg. Channel Input Select 2 */\r
+#define CEIMSEL3 (0x0800u) /* Comp. E Neg. Channel Input Select 3 */\r
+//#define RESERVED (0x1000u) /* Comp. E */\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+#define CEIMEN (0x8000u) /* Comp. E Neg. Channel Input Enable */\r
+\r
+/* CECTL0 Control Bits */\r
+#define CEIPSEL0_L (0x0001u) /* Comp. E Pos. Channel Input Select 0 */\r
+#define CEIPSEL1_L (0x0002u) /* Comp. E Pos. Channel Input Select 1 */\r
+#define CEIPSEL2_L (0x0004u) /* Comp. E Pos. Channel Input Select 2 */\r
+#define CEIPSEL3_L (0x0008u) /* Comp. E Pos. Channel Input Select 3 */\r
+//#define RESERVED (0x0010u) /* Comp. E */\r
+//#define RESERVED (0x0020u) /* Comp. E */\r
+//#define RESERVED (0x0040u) /* Comp. E */\r
+#define CEIPEN_L (0x0080u) /* Comp. E Pos. Channel Input Enable */\r
+//#define RESERVED (0x1000u) /* Comp. E */\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+\r
+/* CECTL0 Control Bits */\r
+//#define RESERVED (0x0010u) /* Comp. E */\r
+//#define RESERVED (0x0020u) /* Comp. E */\r
+//#define RESERVED (0x0040u) /* Comp. E */\r
+#define CEIMSEL0_H (0x0001u) /* Comp. E Neg. Channel Input Select 0 */\r
+#define CEIMSEL1_H (0x0002u) /* Comp. E Neg. Channel Input Select 1 */\r
+#define CEIMSEL2_H (0x0004u) /* Comp. E Neg. Channel Input Select 2 */\r
+#define CEIMSEL3_H (0x0008u) /* Comp. E Neg. Channel Input Select 3 */\r
+//#define RESERVED (0x1000u) /* Comp. E */\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+#define CEIMEN_H (0x0080u) /* Comp. E Neg. Channel Input Enable */\r
+\r
+#define CEIPSEL_0 (0x0000u) /* Comp. E V+ terminal Input Select: Channel 0 */\r
+#define CEIPSEL_1 (0x0001u) /* Comp. E V+ terminal Input Select: Channel 1 */\r
+#define CEIPSEL_2 (0x0002u) /* Comp. E V+ terminal Input Select: Channel 2 */\r
+#define CEIPSEL_3 (0x0003u) /* Comp. E V+ terminal Input Select: Channel 3 */\r
+#define CEIPSEL_4 (0x0004u) /* Comp. E V+ terminal Input Select: Channel 4 */\r
+#define CEIPSEL_5 (0x0005u) /* Comp. E V+ terminal Input Select: Channel 5 */\r
+#define CEIPSEL_6 (0x0006u) /* Comp. E V+ terminal Input Select: Channel 6 */\r
+#define CEIPSEL_7 (0x0007u) /* Comp. E V+ terminal Input Select: Channel 7 */\r
+#define CEIPSEL_8 (0x0008u) /* Comp. E V+ terminal Input Select: Channel 8 */\r
+#define CEIPSEL_9 (0x0009u) /* Comp. E V+ terminal Input Select: Channel 9 */\r
+#define CEIPSEL_10 (0x000Au) /* Comp. E V+ terminal Input Select: Channel 10 */\r
+#define CEIPSEL_11 (0x000Bu) /* Comp. E V+ terminal Input Select: Channel 11 */\r
+#define CEIPSEL_12 (0x000Cu) /* Comp. E V+ terminal Input Select: Channel 12 */\r
+#define CEIPSEL_13 (0x000Du) /* Comp. E V+ terminal Input Select: Channel 13 */\r
+#define CEIPSEL_14 (0x000Eu) /* Comp. E V+ terminal Input Select: Channel 14 */\r
+#define CEIPSEL_15 (0x000Fu) /* Comp. E V+ terminal Input Select: Channel 15 */\r
+\r
+#define CEIMSEL_0 (0x0000u) /* Comp. E V- Terminal Input Select: Channel 0 */\r
+#define CEIMSEL_1 (0x0100u) /* Comp. E V- Terminal Input Select: Channel 1 */\r
+#define CEIMSEL_2 (0x0200u) /* Comp. E V- Terminal Input Select: Channel 2 */\r
+#define CEIMSEL_3 (0x0300u) /* Comp. E V- Terminal Input Select: Channel 3 */\r
+#define CEIMSEL_4 (0x0400u) /* Comp. E V- Terminal Input Select: Channel 4 */\r
+#define CEIMSEL_5 (0x0500u) /* Comp. E V- Terminal Input Select: Channel 5 */\r
+#define CEIMSEL_6 (0x0600u) /* Comp. E V- Terminal Input Select: Channel 6 */\r
+#define CEIMSEL_7 (0x0700u) /* Comp. E V- Terminal Input Select: Channel 7 */\r
+#define CEIMSEL_8 (0x0800u) /* Comp. E V- terminal Input Select: Channel 8 */\r
+#define CEIMSEL_9 (0x0900u) /* Comp. E V- terminal Input Select: Channel 9 */\r
+#define CEIMSEL_10 (0x0A00u) /* Comp. E V- terminal Input Select: Channel 10 */\r
+#define CEIMSEL_11 (0x0B00u) /* Comp. E V- terminal Input Select: Channel 11 */\r
+#define CEIMSEL_12 (0x0C00u) /* Comp. E V- terminal Input Select: Channel 12 */\r
+#define CEIMSEL_13 (0x0D00u) /* Comp. E V- terminal Input Select: Channel 13 */\r
+#define CEIMSEL_14 (0x0E00u) /* Comp. E V- terminal Input Select: Channel 14 */\r
+#define CEIMSEL_15 (0x0F00u) /* Comp. E V- terminal Input Select: Channel 15 */\r
+\r
+/* CECTL1 Control Bits */\r
+#define CEOUT (0x0001u) /* Comp. E Output */\r
+#define CEOUTPOL (0x0002u) /* Comp. E Output Polarity */\r
+#define CEF (0x0004u) /* Comp. E Enable Output Filter */\r
+#define CEIES (0x0008u) /* Comp. E Interrupt Edge Select */\r
+#define CESHORT (0x0010u) /* Comp. E Input Short */\r
+#define CEEX (0x0020u) /* Comp. E Exchange Inputs */\r
+#define CEFDLY0 (0x0040u) /* Comp. E Filter delay Bit 0 */\r
+#define CEFDLY1 (0x0080u) /* Comp. E Filter delay Bit 1 */\r
+#define CEPWRMD0 (0x0100u) /* Comp. E Power mode Bit 0 */\r
+#define CEPWRMD1 (0x0200u) /* Comp. E Power mode Bit 1 */\r
+#define CEON (0x0400u) /* Comp. E enable */\r
+#define CEMRVL (0x0800u) /* Comp. E CEMRV Level */\r
+#define CEMRVS (0x1000u) /* Comp. E Output selects between VREF0 or VREF1*/\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+//#define RESERVED (0x8000u) /* Comp. E */\r
+\r
+/* CECTL1 Control Bits */\r
+#define CEOUT_L (0x0001u) /* Comp. E Output */\r
+#define CEOUTPOL_L (0x0002u) /* Comp. E Output Polarity */\r
+#define CEF_L (0x0004u) /* Comp. E Enable Output Filter */\r
+#define CEIES_L (0x0008u) /* Comp. E Interrupt Edge Select */\r
+#define CESHORT_L (0x0010u) /* Comp. E Input Short */\r
+#define CEEX_L (0x0020u) /* Comp. E Exchange Inputs */\r
+#define CEFDLY0_L (0x0040u) /* Comp. E Filter delay Bit 0 */\r
+#define CEFDLY1_L (0x0080u) /* Comp. E Filter delay Bit 1 */\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+//#define RESERVED (0x8000u) /* Comp. E */\r
+\r
+/* CECTL1 Control Bits */\r
+#define CEPWRMD0_H (0x0001u) /* Comp. E Power mode Bit 0 */\r
+#define CEPWRMD1_H (0x0002u) /* Comp. E Power mode Bit 1 */\r
+#define CEON_H (0x0004u) /* Comp. E enable */\r
+#define CEMRVL_H (0x0008u) /* Comp. E CEMRV Level */\r
+#define CEMRVS_H (0x0010u) /* Comp. E Output selects between VREF0 or VREF1*/\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+//#define RESERVED (0x8000u) /* Comp. E */\r
+\r
+#define CEPWRMD_0 (0x0000u) /* Comp. E Power mode 0 */\r
+#define CEPWRMD_1 (0x0100u) /* Comp. E Power mode 1 */\r
+#define CEPWRMD_2 (0x0200u) /* Comp. E Power mode 2 */\r
+#define CEPWRMD_3 (0x0300u) /* Comp. E Power mode 3*/\r
+\r
+#define CEFDLY_0 (0x0000u) /* Comp. E Filter delay 0 : 450ns */\r
+#define CEFDLY_1 (0x0040u) /* Comp. E Filter delay 1 : 900ns */\r
+#define CEFDLY_2 (0x0080u) /* Comp. E Filter delay 2 : 1800ns */\r
+#define CEFDLY_3 (0x00C0u) /* Comp. E Filter delay 3 : 3600ns */\r
+\r
+/* CECTL2 Control Bits */\r
+#define CEREF00 (0x0001u) /* Comp. E Reference 0 Resistor Select Bit : 0 */\r
+#define CEREF01 (0x0002u) /* Comp. E Reference 0 Resistor Select Bit : 1 */\r
+#define CEREF02 (0x0004u) /* Comp. E Reference 0 Resistor Select Bit : 2 */\r
+#define CEREF03 (0x0008u) /* Comp. E Reference 0 Resistor Select Bit : 3 */\r
+#define CEREF04 (0x0010u) /* Comp. E Reference 0 Resistor Select Bit : 4 */\r
+#define CERSEL (0x0020u) /* Comp. E Reference select */\r
+#define CERS0 (0x0040u) /* Comp. E Reference Source Bit : 0 */\r
+#define CERS1 (0x0080u) /* Comp. E Reference Source Bit : 1 */\r
+#define CEREF10 (0x0100u) /* Comp. E Reference 1 Resistor Select Bit : 0 */\r
+#define CEREF11 (0x0200u) /* Comp. E Reference 1 Resistor Select Bit : 1 */\r
+#define CEREF12 (0x0400u) /* Comp. E Reference 1 Resistor Select Bit : 2 */\r
+#define CEREF13 (0x0800u) /* Comp. E Reference 1 Resistor Select Bit : 3 */\r
+#define CEREF14 (0x1000u) /* Comp. E Reference 1 Resistor Select Bit : 4 */\r
+#define CEREFL0 (0x2000u) /* Comp. E Reference voltage level Bit : 0 */\r
+#define CEREFL1 (0x4000u) /* Comp. E Reference voltage level Bit : 1 */\r
+#define CEREFACC (0x8000u) /* Comp. E Reference Accuracy */\r
+\r
+/* CECTL2 Control Bits */\r
+#define CEREF00_L (0x0001u) /* Comp. E Reference 0 Resistor Select Bit : 0 */\r
+#define CEREF01_L (0x0002u) /* Comp. E Reference 0 Resistor Select Bit : 1 */\r
+#define CEREF02_L (0x0004u) /* Comp. E Reference 0 Resistor Select Bit : 2 */\r
+#define CEREF03_L (0x0008u) /* Comp. E Reference 0 Resistor Select Bit : 3 */\r
+#define CEREF04_L (0x0010u) /* Comp. E Reference 0 Resistor Select Bit : 4 */\r
+#define CERSEL_L (0x0020u) /* Comp. E Reference select */\r
+#define CERS0_L (0x0040u) /* Comp. E Reference Source Bit : 0 */\r
+#define CERS1_L (0x0080u) /* Comp. E Reference Source Bit : 1 */\r
+\r
+/* CECTL2 Control Bits */\r
+#define CEREF10_H (0x0001u) /* Comp. E Reference 1 Resistor Select Bit : 0 */\r
+#define CEREF11_H (0x0002u) /* Comp. E Reference 1 Resistor Select Bit : 1 */\r
+#define CEREF12_H (0x0004u) /* Comp. E Reference 1 Resistor Select Bit : 2 */\r
+#define CEREF13_H (0x0008u) /* Comp. E Reference 1 Resistor Select Bit : 3 */\r
+#define CEREF14_H (0x0010u) /* Comp. E Reference 1 Resistor Select Bit : 4 */\r
+#define CEREFL0_H (0x0020u) /* Comp. E Reference voltage level Bit : 0 */\r
+#define CEREFL1_H (0x0040u) /* Comp. E Reference voltage level Bit : 1 */\r
+#define CEREFACC_H (0x0080u) /* Comp. E Reference Accuracy */\r
+\r
+#define CEREF0_0 (0x0000u) /* Comp. E Int. Ref.0 Select 0 : 1/32 */\r
+#define CEREF0_1 (0x0001u) /* Comp. E Int. Ref.0 Select 1 : 2/32 */\r
+#define CEREF0_2 (0x0002u) /* Comp. E Int. Ref.0 Select 2 : 3/32 */\r
+#define CEREF0_3 (0x0003u) /* Comp. E Int. Ref.0 Select 3 : 4/32 */\r
+#define CEREF0_4 (0x0004u) /* Comp. E Int. Ref.0 Select 4 : 5/32 */\r
+#define CEREF0_5 (0x0005u) /* Comp. E Int. Ref.0 Select 5 : 6/32 */\r
+#define CEREF0_6 (0x0006u) /* Comp. E Int. Ref.0 Select 6 : 7/32 */\r
+#define CEREF0_7 (0x0007u) /* Comp. E Int. Ref.0 Select 7 : 8/32 */\r
+#define CEREF0_8 (0x0008u) /* Comp. E Int. Ref.0 Select 0 : 9/32 */\r
+#define CEREF0_9 (0x0009u) /* Comp. E Int. Ref.0 Select 1 : 10/32 */\r
+#define CEREF0_10 (0x000Au) /* Comp. E Int. Ref.0 Select 2 : 11/32 */\r
+#define CEREF0_11 (0x000Bu) /* Comp. E Int. Ref.0 Select 3 : 12/32 */\r
+#define CEREF0_12 (0x000Cu) /* Comp. E Int. Ref.0 Select 4 : 13/32 */\r
+#define CEREF0_13 (0x000Du) /* Comp. E Int. Ref.0 Select 5 : 14/32 */\r
+#define CEREF0_14 (0x000Eu) /* Comp. E Int. Ref.0 Select 6 : 15/32 */\r
+#define CEREF0_15 (0x000Fu) /* Comp. E Int. Ref.0 Select 7 : 16/32 */\r
+#define CEREF0_16 (0x0010u) /* Comp. E Int. Ref.0 Select 0 : 17/32 */\r
+#define CEREF0_17 (0x0011u) /* Comp. E Int. Ref.0 Select 1 : 18/32 */\r
+#define CEREF0_18 (0x0012u) /* Comp. E Int. Ref.0 Select 2 : 19/32 */\r
+#define CEREF0_19 (0x0013u) /* Comp. E Int. Ref.0 Select 3 : 20/32 */\r
+#define CEREF0_20 (0x0014u) /* Comp. E Int. Ref.0 Select 4 : 21/32 */\r
+#define CEREF0_21 (0x0015u) /* Comp. E Int. Ref.0 Select 5 : 22/32 */\r
+#define CEREF0_22 (0x0016u) /* Comp. E Int. Ref.0 Select 6 : 23/32 */\r
+#define CEREF0_23 (0x0017u) /* Comp. E Int. Ref.0 Select 7 : 24/32 */\r
+#define CEREF0_24 (0x0018u) /* Comp. E Int. Ref.0 Select 0 : 25/32 */\r
+#define CEREF0_25 (0x0019u) /* Comp. E Int. Ref.0 Select 1 : 26/32 */\r
+#define CEREF0_26 (0x001Au) /* Comp. E Int. Ref.0 Select 2 : 27/32 */\r
+#define CEREF0_27 (0x001Bu) /* Comp. E Int. Ref.0 Select 3 : 28/32 */\r
+#define CEREF0_28 (0x001Cu) /* Comp. E Int. Ref.0 Select 4 : 29/32 */\r
+#define CEREF0_29 (0x001Du) /* Comp. E Int. Ref.0 Select 5 : 30/32 */\r
+#define CEREF0_30 (0x001Eu) /* Comp. E Int. Ref.0 Select 6 : 31/32 */\r
+#define CEREF0_31 (0x001Fu) /* Comp. E Int. Ref.0 Select 7 : 32/32 */\r
+\r
+#define CERS_0 (0x0000u) /* Comp. E Reference Source 0 : Off */\r
+#define CERS_1 (0x0040u) /* Comp. E Reference Source 1 : Vcc */\r
+#define CERS_2 (0x0080u) /* Comp. E Reference Source 2 : Shared Ref. */\r
+#define CERS_3 (0x00C0u) /* Comp. E Reference Source 3 : Shared Ref. / Off */\r
+\r
+#define CEREF1_0 (0x0000u) /* Comp. E Int. Ref.1 Select 0 : 1/32 */\r
+#define CEREF1_1 (0x0100u) /* Comp. E Int. Ref.1 Select 1 : 2/32 */\r
+#define CEREF1_2 (0x0200u) /* Comp. E Int. Ref.1 Select 2 : 3/32 */\r
+#define CEREF1_3 (0x0300u) /* Comp. E Int. Ref.1 Select 3 : 4/32 */\r
+#define CEREF1_4 (0x0400u) /* Comp. E Int. Ref.1 Select 4 : 5/32 */\r
+#define CEREF1_5 (0x0500u) /* Comp. E Int. Ref.1 Select 5 : 6/32 */\r
+#define CEREF1_6 (0x0600u) /* Comp. E Int. Ref.1 Select 6 : 7/32 */\r
+#define CEREF1_7 (0x0700u) /* Comp. E Int. Ref.1 Select 7 : 8/32 */\r
+#define CEREF1_8 (0x0800u) /* Comp. E Int. Ref.1 Select 0 : 9/32 */\r
+#define CEREF1_9 (0x0900u) /* Comp. E Int. Ref.1 Select 1 : 10/32 */\r
+#define CEREF1_10 (0x0A00u) /* Comp. E Int. Ref.1 Select 2 : 11/32 */\r
+#define CEREF1_11 (0x0B00u) /* Comp. E Int. Ref.1 Select 3 : 12/32 */\r
+#define CEREF1_12 (0x0C00u) /* Comp. E Int. Ref.1 Select 4 : 13/32 */\r
+#define CEREF1_13 (0x0D00u) /* Comp. E Int. Ref.1 Select 5 : 14/32 */\r
+#define CEREF1_14 (0x0E00u) /* Comp. E Int. Ref.1 Select 6 : 15/32 */\r
+#define CEREF1_15 (0x0F00u) /* Comp. E Int. Ref.1 Select 7 : 16/32 */\r
+#define CEREF1_16 (0x1000u) /* Comp. E Int. Ref.1 Select 0 : 17/32 */\r
+#define CEREF1_17 (0x1100u) /* Comp. E Int. Ref.1 Select 1 : 18/32 */\r
+#define CEREF1_18 (0x1200u) /* Comp. E Int. Ref.1 Select 2 : 19/32 */\r
+#define CEREF1_19 (0x1300u) /* Comp. E Int. Ref.1 Select 3 : 20/32 */\r
+#define CEREF1_20 (0x1400u) /* Comp. E Int. Ref.1 Select 4 : 21/32 */\r
+#define CEREF1_21 (0x1500u) /* Comp. E Int. Ref.1 Select 5 : 22/32 */\r
+#define CEREF1_22 (0x1600u) /* Comp. E Int. Ref.1 Select 6 : 23/32 */\r
+#define CEREF1_23 (0x1700u) /* Comp. E Int. Ref.1 Select 7 : 24/32 */\r
+#define CEREF1_24 (0x1800u) /* Comp. E Int. Ref.1 Select 0 : 25/32 */\r
+#define CEREF1_25 (0x1900u) /* Comp. E Int. Ref.1 Select 1 : 26/32 */\r
+#define CEREF1_26 (0x1A00u) /* Comp. E Int. Ref.1 Select 2 : 27/32 */\r
+#define CEREF1_27 (0x1B00u) /* Comp. E Int. Ref.1 Select 3 : 28/32 */\r
+#define CEREF1_28 (0x1C00u) /* Comp. E Int. Ref.1 Select 4 : 29/32 */\r
+#define CEREF1_29 (0x1D00u) /* Comp. E Int. Ref.1 Select 5 : 30/32 */\r
+#define CEREF1_30 (0x1E00u) /* Comp. E Int. Ref.1 Select 6 : 31/32 */\r
+#define CEREF1_31 (0x1F00u) /* Comp. E Int. Ref.1 Select 7 : 32/32 */\r
+\r
+#define CEREFL_0 (0x0000u) /* Comp. E Reference voltage level 0 : None */\r
+#define CEREFL_1 (0x2000u) /* Comp. E Reference voltage level 1 : 1.2V */\r
+#define CEREFL_2 (0x4000u) /* Comp. E Reference voltage level 2 : 2.0V */\r
+#define CEREFL_3 (0x6000u) /* Comp. E Reference voltage level 3 : 2.5V */\r
+\r
+#define CEPD0 (0x0001u) /* Comp. E Disable Input Buffer of Port Register .0 */\r
+#define CEPD1 (0x0002u) /* Comp. E Disable Input Buffer of Port Register .1 */\r
+#define CEPD2 (0x0004u) /* Comp. E Disable Input Buffer of Port Register .2 */\r
+#define CEPD3 (0x0008u) /* Comp. E Disable Input Buffer of Port Register .3 */\r
+#define CEPD4 (0x0010u) /* Comp. E Disable Input Buffer of Port Register .4 */\r
+#define CEPD5 (0x0020u) /* Comp. E Disable Input Buffer of Port Register .5 */\r
+#define CEPD6 (0x0040u) /* Comp. E Disable Input Buffer of Port Register .6 */\r
+#define CEPD7 (0x0080u) /* Comp. E Disable Input Buffer of Port Register .7 */\r
+#define CEPD8 (0x0100u) /* Comp. E Disable Input Buffer of Port Register .8 */\r
+#define CEPD9 (0x0200u) /* Comp. E Disable Input Buffer of Port Register .9 */\r
+#define CEPD10 (0x0400u) /* Comp. E Disable Input Buffer of Port Register .10 */\r
+#define CEPD11 (0x0800u) /* Comp. E Disable Input Buffer of Port Register .11 */\r
+#define CEPD12 (0x1000u) /* Comp. E Disable Input Buffer of Port Register .12 */\r
+#define CEPD13 (0x2000u) /* Comp. E Disable Input Buffer of Port Register .13 */\r
+#define CEPD14 (0x4000u) /* Comp. E Disable Input Buffer of Port Register .14 */\r
+#define CEPD15 (0x8000u) /* Comp. E Disable Input Buffer of Port Register .15 */\r
+\r
+#define CEPD0_L (0x0001u) /* Comp. E Disable Input Buffer of Port Register .0 */\r
+#define CEPD1_L (0x0002u) /* Comp. E Disable Input Buffer of Port Register .1 */\r
+#define CEPD2_L (0x0004u) /* Comp. E Disable Input Buffer of Port Register .2 */\r
+#define CEPD3_L (0x0008u) /* Comp. E Disable Input Buffer of Port Register .3 */\r
+#define CEPD4_L (0x0010u) /* Comp. E Disable Input Buffer of Port Register .4 */\r
+#define CEPD5_L (0x0020u) /* Comp. E Disable Input Buffer of Port Register .5 */\r
+#define CEPD6_L (0x0040u) /* Comp. E Disable Input Buffer of Port Register .6 */\r
+#define CEPD7_L (0x0080u) /* Comp. E Disable Input Buffer of Port Register .7 */\r
+\r
+#define CEPD8_H (0x0001u) /* Comp. E Disable Input Buffer of Port Register .8 */\r
+#define CEPD9_H (0x0002u) /* Comp. E Disable Input Buffer of Port Register .9 */\r
+#define CEPD10_H (0x0004u) /* Comp. E Disable Input Buffer of Port Register .10 */\r
+#define CEPD11_H (0x0008u) /* Comp. E Disable Input Buffer of Port Register .11 */\r
+#define CEPD12_H (0x0010u) /* Comp. E Disable Input Buffer of Port Register .12 */\r
+#define CEPD13_H (0x0020u) /* Comp. E Disable Input Buffer of Port Register .13 */\r
+#define CEPD14_H (0x0040u) /* Comp. E Disable Input Buffer of Port Register .14 */\r
+#define CEPD15_H (0x0080u) /* Comp. E Disable Input Buffer of Port Register .15 */\r
+\r
+/* CEINT Control Bits */\r
+#define CEIFG (0x0001u) /* Comp. E Interrupt Flag */\r
+#define CEIIFG (0x0002u) /* Comp. E Interrupt Flag Inverted Polarity */\r
+//#define RESERVED (0x0004u) /* Comp. E */\r
+//#define RESERVED (0x0008u) /* Comp. E */\r
+#define CERDYIFG (0x0010u) /* Comp. E Comparator_E ready interrupt flag */\r
+//#define RESERVED (0x0020u) /* Comp. E */\r
+//#define RESERVED (0x0040u) /* Comp. E */\r
+//#define RESERVED (0x0080u) /* Comp. E */\r
+#define CEIE (0x0100u) /* Comp. E Interrupt Enable */\r
+#define CEIIE (0x0200u) /* Comp. E Interrupt Enable Inverted Polarity */\r
+//#define RESERVED (0x0400u) /* Comp. E */\r
+//#define RESERVED (0x0800u) /* Comp. E */\r
+#define CERDYIE (0x1000u) /* Comp. E Comparator_E ready interrupt enable */\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+//#define RESERVED (0x8000u) /* Comp. E */\r
+\r
+/* CEINT Control Bits */\r
+#define CEIFG_L (0x0001u) /* Comp. E Interrupt Flag */\r
+#define CEIIFG_L (0x0002u) /* Comp. E Interrupt Flag Inverted Polarity */\r
+//#define RESERVED (0x0004u) /* Comp. E */\r
+//#define RESERVED (0x0008u) /* Comp. E */\r
+#define CERDYIFG_L (0x0010u) /* Comp. E Comparator_E ready interrupt flag */\r
+//#define RESERVED (0x0020u) /* Comp. E */\r
+//#define RESERVED (0x0040u) /* Comp. E */\r
+//#define RESERVED (0x0080u) /* Comp. E */\r
+//#define RESERVED (0x0400u) /* Comp. E */\r
+//#define RESERVED (0x0800u) /* Comp. E */\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+//#define RESERVED (0x8000u) /* Comp. E */\r
+\r
+/* CEINT Control Bits */\r
+//#define RESERVED (0x0004u) /* Comp. E */\r
+//#define RESERVED (0x0008u) /* Comp. E */\r
+//#define RESERVED (0x0020u) /* Comp. E */\r
+//#define RESERVED (0x0040u) /* Comp. E */\r
+//#define RESERVED (0x0080u) /* Comp. E */\r
+#define CEIE_H (0x0001u) /* Comp. E Interrupt Enable */\r
+#define CEIIE_H (0x0002u) /* Comp. E Interrupt Enable Inverted Polarity */\r
+//#define RESERVED (0x0400u) /* Comp. E */\r
+//#define RESERVED (0x0800u) /* Comp. E */\r
+#define CERDYIE_H (0x0010u) /* Comp. E Comparator_E ready interrupt enable */\r
+//#define RESERVED (0x2000u) /* Comp. E */\r
+//#define RESERVED (0x4000u) /* Comp. E */\r
+//#define RESERVED (0x8000u) /* Comp. E */\r
+\r
+/* CEIV Definitions */\r
+#define CEIV_NONE (0x0000u) /* No Interrupt pending */\r
+#define CEIV_CEIFG (0x0002u) /* CEIFG */\r
+#define CEIV_CEIIFG (0x0004u) /* CEIIFG */\r
+#define CEIV_CERDYIFG (0x000Au) /* CERDYIFG */\r
+\r
+#endif\r
+/*************************************************************\r
+* CRC Module\r
+*************************************************************/\r
+#ifdef __MSP430_HAS_CRC__ /* Definition to show that Module is available */\r
+\r
+#define OFS_CRCDI (0x0000u) /* CRC Data In Register */\r
+#define OFS_CRCDI_L OFS_CRCDI\r
+#define OFS_CRCDI_H OFS_CRCDI+1\r
+#define OFS_CRCDIRB (0x0002u) /* CRC data in reverse byte Register */\r
+#define OFS_CRCDIRB_L OFS_CRCDIRB\r
+#define OFS_CRCDIRB_H OFS_CRCDIRB+1\r
+#define OFS_CRCINIRES (0x0004u) /* CRC Initialisation Register and Result Register */\r
+#define OFS_CRCINIRES_L OFS_CRCINIRES\r
+#define OFS_CRCINIRES_H OFS_CRCINIRES+1\r
+#define OFS_CRCRESR (0x0006u) /* CRC reverse result Register */\r
+#define OFS_CRCRESR_L OFS_CRCRESR\r
+#define OFS_CRCRESR_H OFS_CRCRESR+1\r
+\r
+#endif\r
+/*************************************************************\r
+* CRC Module\r
+*************************************************************/\r
+#ifdef __MSP430_HAS_CRC32__ /* Definition to show that Module is available */\r
+\r
+\r
+//#define CRC32DIL0_O (0x0000u) /* CRC32 Data In */\r
+#define OFS_CRC32DIW0 (0x0000u) /* CRC32 Data In */\r
+#define OFS_CRC32DIW0_L OFS_CRC32DIW0\r
+#define OFS_CRC32DIW0_H OFS_CRC32DIW0+1\r
+#define OFS_CRC32DIW1 (0x0002u) /* CRC32 Data In */\r
+#define OFS_CRC32DIW1_L OFS_CRC32DIW1\r
+#define OFS_CRC32DIW1_H OFS_CRC32DIW1+1\r
+#define CRC32DIB0 CRC32DIW0_L\r
+\r
+//#define CRC32DIRBL0_O (0x0004u) /* CRC32 Data In Reversed Bit */\r
+#define OFS_CRC32DIRBW1 (0x0004u) /* CRC32 Data In Reversed Bit */\r
+#define OFS_CRC32DIRBW1_L OFS_CRC32DIRBW1\r
+#define OFS_CRC32DIRBW1_H OFS_CRC32DIRBW1+1\r
+#define OFS_CRC32DIRBW0 (0x0006u) /* CRC32 Data In Reversed Bit */\r
+#define OFS_CRC32DIRBW0_L OFS_CRC32DIRBW0\r
+#define OFS_CRC32DIRBW0_H OFS_CRC32DIRBW0+1\r
+#define CRC32DIRBB0 CRC32DIRBW0_H\r
+\r
+//#define CRC32INIRESL0_O (0x0008u) /* CRC32 Initialization and Result */\r
+#define OFS_CRC32INIRESW0 (0x0008u) /* CRC32 Initialization and Result */\r
+#define OFS_CRC32INIRESW0_L OFS_CRC32INIRESW0\r
+#define OFS_CRC32INIRESW0_H OFS_CRC32INIRESW0+1\r
+#define OFS_CRC32INIRESW1 (0x000Au) /* CRC32 Initialization and Result */\r
+#define OFS_CRC32INIRESW1_L OFS_CRC32INIRESW1\r
+#define OFS_CRC32INIRESW1_H OFS_CRC32INIRESW1+1\r
+#define CRC32RESB0 CRC32INIRESW0_L\r
+#define CRC32RESB1 CRC32INIRESW0_H\r
+#define CRC32RESB2 CRC32INIRESW1_L\r
+#define CRC32RESB3 CRC32INIRESW1_H\r
+\r
+//#define CRC32RESRL0_O (0x000Cu) /* CRC32 Result Reverse */\r
+#define OFS_CRC32RESRW1 (0x000Cu) /* CRC32 Result Reverse */\r
+#define OFS_CRC32RESRW1_L OFS_CRC32RESRW1\r
+#define OFS_CRC32RESRW1_H OFS_CRC32RESRW1+1\r
+#define OFS_CRC32RESRW0 (0x000Eu) /* CRC32 Result Reverse */\r
+#define OFS_CRC32RESRW0_L OFS_CRC32RESRW0\r
+#define OFS_CRC32RESRW0_H OFS_CRC32RESRW0+1\r
+#define CRC32RESRB3 CRC32RESRW1_L\r
+#define CRC32RESRB2 CRC32RESRW1_H\r
+#define CRC32RESRB1 CRC32RESRW0_L\r
+#define CRC32RESRB0 CRC32RESRW0_H\r
+\r
+//#define CRC16DIL0_O (0x0010u) /* CRC16 Data Input */\r
+#define OFS_CRC16DIW0 (0x0010u) /* CRC16 Data Input */\r
+#define OFS_CRC16DIW0_L OFS_CRC16DIW0\r
+#define OFS_CRC16DIW0_H OFS_CRC16DIW0+1\r
+#define OFS_CRC16DIW1 (0x0012u) /* CRC16 Data Input */\r
+#define OFS_CRC16DIW1_L OFS_CRC16DIW1\r
+#define OFS_CRC16DIW1_H OFS_CRC16DIW1+1\r
+#define CRC16DIB0 CRC16DIW0_L\r
+//#define CRC16DIRBL0_O (0x0014u) /* CRC16 Data In Reverse */\r
+#define OFS_CRC16DIRBW1 (0x0014u) /* CRC16 Data In Reverse */\r
+#define OFS_CRC16DIRBW1_L OFS_CRC16DIRBW1\r
+#define OFS_CRC16DIRBW1_H OFS_CRC16DIRBW1+1\r
+#define OFS_CRC16DIRBW0 (0x0016u) /* CRC16 Data In Reverse */\r
+#define OFS_CRC16DIRBW0_L OFS_CRC16DIRBW0\r
+#define OFS_CRC16DIRBW0_H OFS_CRC16DIRBW0+1\r
+#define CRC16DIRBB0 CRC16DIRBW0_L\r
+\r
+//#define CRC16INIRESL0_O (0x0018u) /* CRC16 Init and Result */\r
+#define OFS_CRC16INIRESW0 (0x0018u) /* CRC16 Init and Result */\r
+#define OFS_CRC16INIRESW0_L OFS_CRC16INIRESW0\r
+#define OFS_CRC16INIRESW0_H OFS_CRC16INIRESW0+1\r
+#define CRC16INIRESB1 CRC16INIRESW0_H\r
+#define CRC16INIRESB0 CRC16INIRESW0_L\r
+\r
+//#define CRC16RESRL0_O (0x001Eu) /* CRC16 Result Reverse */\r
+#define OFS_CRC16RESRW0 (0x001Eu) /* CRC16 Result Reverse */\r
+#define OFS_CRC16RESRW0_L OFS_CRC16RESRW0\r
+#define OFS_CRC16RESRW0_H OFS_CRC16RESRW0+1\r
+#define OFS_CRC16RESRW1 (0x001Cu) /* CRC16 Result Reverse */\r
+#define OFS_CRC16RESRW1_L OFS_CRC16RESRW1\r
+#define OFS_CRC16RESRW1_H OFS_CRC16RESRW1+1\r
+#define CRC16RESRB1 CRC16RESRW0_L\r
+#define CRC16RESRB0 CRC16RESRW0_H\r
+\r
+#endif\r
+/************************************************************\r
+* CLOCK SYSTEM\r
+************************************************************/\r
+#ifdef __MSP430_HAS_CS__ /* Definition to show that Module is available */\r
+\r
+#define OFS_CSCTL0 (0x0000u) /* CS Control Register 0 */\r
+#define OFS_CSCTL0_L OFS_CSCTL0\r
+#define OFS_CSCTL0_H OFS_CSCTL0+1\r
+#define OFS_CSCTL1 (0x0002u) /* CS Control Register 1 */\r
+#define OFS_CSCTL1_L OFS_CSCTL1\r
+#define OFS_CSCTL1_H OFS_CSCTL1+1\r
+#define OFS_CSCTL2 (0x0004u) /* CS Control Register 2 */\r
+#define OFS_CSCTL2_L OFS_CSCTL2\r
+#define OFS_CSCTL2_H OFS_CSCTL2+1\r
+#define OFS_CSCTL3 (0x0006u) /* CS Control Register 3 */\r
+#define OFS_CSCTL3_L OFS_CSCTL3\r
+#define OFS_CSCTL3_H OFS_CSCTL3+1\r
+#define OFS_CSCTL4 (0x0008u) /* CS Control Register 4 */\r
+#define OFS_CSCTL4_L OFS_CSCTL4\r
+#define OFS_CSCTL4_H OFS_CSCTL4+1\r
+#define OFS_CSCTL5 (0x000Au) /* CS Control Register 5 */\r
+#define OFS_CSCTL5_L OFS_CSCTL5\r
+#define OFS_CSCTL5_H OFS_CSCTL5+1\r
+#define OFS_CSCTL6 (0x000Cu) /* CS Control Register 6 */\r
+#define OFS_CSCTL6_L OFS_CSCTL6\r
+#define OFS_CSCTL6_H OFS_CSCTL6+1\r
+\r
+/* CSCTL0 Control Bits */\r
+\r
+#define CSKEY (0xA500u) /* CS Password */\r
+#define CSKEY_H (0xA5) /* CS Password for high byte access */\r
+\r
+/* CSCTL1 Control Bits */\r
+#define DCOFSEL0 (0x0002u) /* DCO frequency select Bit: 0 */\r
+#define DCOFSEL1 (0x0004u) /* DCO frequency select Bit: 1 */\r
+#define DCOFSEL2 (0x0008u) /* DCO frequency select Bit: 2 */\r
+#define DCORSEL (0x0040u) /* DCO range select. */\r
+\r
+/* CSCTL1 Control Bits */\r
+#define DCOFSEL0_L (0x0002u) /* DCO frequency select Bit: 0 */\r
+#define DCOFSEL1_L (0x0004u) /* DCO frequency select Bit: 1 */\r
+#define DCOFSEL2_L (0x0008u) /* DCO frequency select Bit: 2 */\r
+#define DCORSEL_L (0x0040u) /* DCO range select. */\r
+\r
+#define DCOFSEL_0 (0x0000u) /* DCO frequency select: 0 */\r
+#define DCOFSEL_1 (0x0002u) /* DCO frequency select: 1 */\r
+#define DCOFSEL_2 (0x0004u) /* DCO frequency select: 2 */\r
+#define DCOFSEL_3 (0x0006u) /* DCO frequency select: 3 */\r
+#define DCOFSEL_4 (0x0008u) /* DCO frequency select: 4 */\r
+#define DCOFSEL_5 (0x000Au) /* DCO frequency select: 5 */\r
+#define DCOFSEL_6 (0x000Cu) /* DCO frequency select: 6 */\r
+#define DCOFSEL_7 (0x000Eu) /* DCO frequency select: 7 */\r
+\r
+/* CSCTL2 Control Bits */\r
+#define SELM0 (0x0001u) /* MCLK Source Select Bit: 0 */\r
+#define SELM1 (0x0002u) /* MCLK Source Select Bit: 1 */\r
+#define SELM2 (0x0004u) /* MCLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0004u) /* RESERVED */\r
+//#define RESERVED (0x0008u) /* RESERVED */\r
+#define SELS0 (0x0010u) /* SMCLK Source Select Bit: 0 */\r
+#define SELS1 (0x0020u) /* SMCLK Source Select Bit: 1 */\r
+#define SELS2 (0x0040u) /* SMCLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0040u) /* RESERVED */\r
+//#define RESERVED (0x0080u) /* RESERVED */\r
+#define SELA0 (0x0100u) /* ACLK Source Select Bit: 0 */\r
+#define SELA1 (0x0200u) /* ACLK Source Select Bit: 1 */\r
+#define SELA2 (0x0400u) /* ACLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x1000u) /* RESERVED */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+//#define RESERVED (0x4000u) /* RESERVED */\r
+//#define RESERVED (0x8000u) /* RESERVED */\r
+\r
+/* CSCTL2 Control Bits */\r
+#define SELM0_L (0x0001u) /* MCLK Source Select Bit: 0 */\r
+#define SELM1_L (0x0002u) /* MCLK Source Select Bit: 1 */\r
+#define SELM2_L (0x0004u) /* MCLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0004u) /* RESERVED */\r
+//#define RESERVED (0x0008u) /* RESERVED */\r
+#define SELS0_L (0x0010u) /* SMCLK Source Select Bit: 0 */\r
+#define SELS1_L (0x0020u) /* SMCLK Source Select Bit: 1 */\r
+#define SELS2_L (0x0040u) /* SMCLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0040u) /* RESERVED */\r
+//#define RESERVED (0x0080u) /* RESERVED */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x1000u) /* RESERVED */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+//#define RESERVED (0x4000u) /* RESERVED */\r
+//#define RESERVED (0x8000u) /* RESERVED */\r
+\r
+/* CSCTL2 Control Bits */\r
+//#define RESERVED (0x0004u) /* RESERVED */\r
+//#define RESERVED (0x0008u) /* RESERVED */\r
+//#define RESERVED (0x0040u) /* RESERVED */\r
+//#define RESERVED (0x0080u) /* RESERVED */\r
+#define SELA0_H (0x0001u) /* ACLK Source Select Bit: 0 */\r
+#define SELA1_H (0x0002u) /* ACLK Source Select Bit: 1 */\r
+#define SELA2_H (0x0004u) /* ACLK Source Select Bit: 2 */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x1000u) /* RESERVED */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+//#define RESERVED (0x4000u) /* RESERVED */\r
+//#define RESERVED (0x8000u) /* RESERVED */\r
+\r
+#define SELM_0 (0x0000u) /* MCLK Source Select 0 */\r
+#define SELM_1 (0x0001u) /* MCLK Source Select 1 */\r
+#define SELM_2 (0x0002u) /* MCLK Source Select 2 */\r
+#define SELM_3 (0x0003u) /* MCLK Source Select 3 */\r
+#define SELM_4 (0x0004u) /* MCLK Source Select 4 */\r
+#define SELM_5 (0x0005u) /* MCLK Source Select 5 */\r
+#define SELM_6 (0x0006u) /* MCLK Source Select 6 */\r
+#define SELM_7 (0x0007u) /* MCLK Source Select 7 */\r
+#define SELM__LFXTCLK (0x0000u) /* MCLK Source Select LFXTCLK */\r
+#define SELM__VLOCLK (0x0001u) /* MCLK Source Select VLOCLK */\r
+#define SELM__LFMODOSC (0x0002u) /* MCLK Source Select LFMODOSC */\r
+#define SELM__DCOCLK (0x0003u) /* MCLK Source Select DCOCLK */\r
+#define SELM__MODOSC (0x0004u) /* MCLK Source Select MODOSC */\r
+#define SELM__HFXTCLK (0x0005u) /* MCLK Source Select HFXTCLK */\r
+\r
+#define SELS_0 (0x0000u) /* SMCLK Source Select 0 */\r
+#define SELS_1 (0x0010u) /* SMCLK Source Select 1 */\r
+#define SELS_2 (0x0020u) /* SMCLK Source Select 2 */\r
+#define SELS_3 (0x0030u) /* SMCLK Source Select 3 */\r
+#define SELS_4 (0x0040u) /* SMCLK Source Select 4 */\r
+#define SELS_5 (0x0050u) /* SMCLK Source Select 5 */\r
+#define SELS_6 (0x0060u) /* SMCLK Source Select 6 */\r
+#define SELS_7 (0x0070u) /* SMCLK Source Select 7 */\r
+#define SELS__LFXTCLK (0x0000u) /* SMCLK Source Select LFXTCLK */\r
+#define SELS__VLOCLK (0x0010u) /* SMCLK Source Select VLOCLK */\r
+#define SELS__LFMODOSC (0x0020u) /* SMCLK Source Select LFMODOSC */\r
+#define SELS__DCOCLK (0x0030u) /* SMCLK Source Select DCOCLK */\r
+#define SELS__MODOSC (0x0040u) /* SMCLK Source Select MODOSC */\r
+#define SELS__HFXTCLK (0x0050u) /* SMCLK Source Select HFXTCLK */\r
+\r
+#define SELA_0 (0x0000u) /* ACLK Source Select 0 */\r
+#define SELA_1 (0x0100u) /* ACLK Source Select 1 */\r
+#define SELA_2 (0x0200u) /* ACLK Source Select 2 */\r
+#define SELA_3 (0x0300u) /* ACLK Source Select 3 */\r
+#define SELA_4 (0x0400u) /* ACLK Source Select 4 */\r
+#define SELA_5 (0x0500u) /* ACLK Source Select 5 */\r
+#define SELA_6 (0x0600u) /* ACLK Source Select 6 */\r
+#define SELA_7 (0x0700u) /* ACLK Source Select 7 */\r
+#define SELA__LFXTCLK (0x0000u) /* ACLK Source Select LFXTCLK */\r
+#define SELA__VLOCLK (0x0100u) /* ACLK Source Select VLOCLK */\r
+#define SELA__LFMODOSC (0x0200u) /* ACLK Source Select LFMODOSC */\r
+\r
+/* CSCTL3 Control Bits */\r
+#define DIVM0 (0x0001u) /* MCLK Divider Bit: 0 */\r
+#define DIVM1 (0x0002u) /* MCLK Divider Bit: 1 */\r
+#define DIVM2 (0x0004u) /* MCLK Divider Bit: 2 */\r
+//#define RESERVED (0x0004u) /* RESERVED */\r
+//#define RESERVED (0x0008u) /* RESERVED */\r
+#define DIVS0 (0x0010u) /* SMCLK Divider Bit: 0 */\r
+#define DIVS1 (0x0020u) /* SMCLK Divider Bit: 1 */\r
+#define DIVS2 (0x0040u) /* SMCLK Divider Bit: 2 */\r
+//#define RESERVED (0x0040u) /* RESERVED */\r
+//#define RESERVED (0x0080u) /* RESERVED */\r
+#define DIVA0 (0x0100u) /* ACLK Divider Bit: 0 */\r
+#define DIVA1 (0x0200u) /* ACLK Divider Bit: 1 */\r
+#define DIVA2 (0x0400u) /* ACLK Divider Bit: 2 */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x1000u) /* RESERVED */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+//#define RESERVED (0x4000u) /* RESERVED */\r
+//#define RESERVED (0x8000u) /* RESERVED */\r
+\r
+/* CSCTL3 Control Bits */\r
+#define DIVM0_L (0x0001u) /* MCLK Divider Bit: 0 */\r
+#define DIVM1_L (0x0002u) /* MCLK Divider Bit: 1 */\r
+#define DIVM2_L (0x0004u) /* MCLK Divider Bit: 2 */\r
+//#define RESERVED (0x0004u) /* RESERVED */\r
+//#define RESERVED (0x0008u) /* RESERVED */\r
+#define DIVS0_L (0x0010u) /* SMCLK Divider Bit: 0 */\r
+#define DIVS1_L (0x0020u) /* SMCLK Divider Bit: 1 */\r
+#define DIVS2_L (0x0040u) /* SMCLK Divider Bit: 2 */\r
+//#define RESERVED (0x0040u) /* RESERVED */\r
+//#define RESERVED (0x0080u) /* RESERVED */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x1000u) /* RESERVED */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+//#define RESERVED (0x4000u) /* RESERVED */\r
+//#define RESERVED (0x8000u) /* RESERVED */\r
+\r
+/* CSCTL3 Control Bits */\r
+//#define RESERVED (0x0004u) /* RESERVED */\r
+//#define RESERVED (0x0008u) /* RESERVED */\r
+//#define RESERVED (0x0040u) /* RESERVED */\r
+//#define RESERVED (0x0080u) /* RESERVED */\r
+#define DIVA0_H (0x0001u) /* ACLK Divider Bit: 0 */\r
+#define DIVA1_H (0x0002u) /* ACLK Divider Bit: 1 */\r
+#define DIVA2_H (0x0004u) /* ACLK Divider Bit: 2 */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x1000u) /* RESERVED */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+//#define RESERVED (0x4000u) /* RESERVED */\r
+//#define RESERVED (0x8000u) /* RESERVED */\r
+\r
+#define DIVM_0 (0x0000u) /* MCLK Source Divider 0 */\r
+#define DIVM_1 (0x0001u) /* MCLK Source Divider 1 */\r
+#define DIVM_2 (0x0002u) /* MCLK Source Divider 2 */\r
+#define DIVM_3 (0x0003u) /* MCLK Source Divider 3 */\r
+#define DIVM_4 (0x0004u) /* MCLK Source Divider 4 */\r
+#define DIVM_5 (0x0005u) /* MCLK Source Divider 5 */\r
+#define DIVM__1 (0x0000u) /* MCLK Source Divider f(MCLK)/1 */\r
+#define DIVM__2 (0x0001u) /* MCLK Source Divider f(MCLK)/2 */\r
+#define DIVM__4 (0x0002u) /* MCLK Source Divider f(MCLK)/4 */\r
+#define DIVM__8 (0x0003u) /* MCLK Source Divider f(MCLK)/8 */\r
+#define DIVM__16 (0x0004u) /* MCLK Source Divider f(MCLK)/16 */\r
+#define DIVM__32 (0x0005u) /* MCLK Source Divider f(MCLK)/32 */\r
+\r
+#define DIVS_0 (0x0000u) /* SMCLK Source Divider 0 */\r
+#define DIVS_1 (0x0010u) /* SMCLK Source Divider 1 */\r
+#define DIVS_2 (0x0020u) /* SMCLK Source Divider 2 */\r
+#define DIVS_3 (0x0030u) /* SMCLK Source Divider 3 */\r
+#define DIVS_4 (0x0040u) /* SMCLK Source Divider 4 */\r
+#define DIVS_5 (0x0050u) /* SMCLK Source Divider 5 */\r
+#define DIVS__1 (0x0000u) /* SMCLK Source Divider f(SMCLK)/1 */\r
+#define DIVS__2 (0x0010u) /* SMCLK Source Divider f(SMCLK)/2 */\r
+#define DIVS__4 (0x0020u) /* SMCLK Source Divider f(SMCLK)/4 */\r
+#define DIVS__8 (0x0030u) /* SMCLK Source Divider f(SMCLK)/8 */\r
+#define DIVS__16 (0x0040u) /* SMCLK Source Divider f(SMCLK)/16 */\r
+#define DIVS__32 (0x0050u) /* SMCLK Source Divider f(SMCLK)/32 */\r
+\r
+#define DIVA_0 (0x0000u) /* ACLK Source Divider 0 */\r
+#define DIVA_1 (0x0100u) /* ACLK Source Divider 1 */\r
+#define DIVA_2 (0x0200u) /* ACLK Source Divider 2 */\r
+#define DIVA_3 (0x0300u) /* ACLK Source Divider 3 */\r
+#define DIVA_4 (0x0400u) /* ACLK Source Divider 4 */\r
+#define DIVA_5 (0x0500u) /* ACLK Source Divider 5 */\r
+#define DIVA__1 (0x0000u) /* ACLK Source Divider f(ACLK)/1 */\r
+#define DIVA__2 (0x0100u) /* ACLK Source Divider f(ACLK)/2 */\r
+#define DIVA__4 (0x0200u) /* ACLK Source Divider f(ACLK)/4 */\r
+#define DIVA__8 (0x0300u) /* ACLK Source Divider f(ACLK)/8 */\r
+#define DIVA__16 (0x0400u) /* ACLK Source Divider f(ACLK)/16 */\r
+#define DIVA__32 (0x0500u) /* ACLK Source Divider f(ACLK)/32 */\r
+\r
+/* CSCTL4 Control Bits */\r
+#define LFXTOFF (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */\r
+#define SMCLKOFF (0x0002u) /* SMCLK Off */\r
+#define VLOOFF (0x0008u) /* VLO Off */\r
+#define LFXTBYPASS (0x0010u) /* LFXT bypass mode : 0: internal 1:sourced from external pin */\r
+#define LFXTAGCOFF (0x0020u) /* LFXT automatic gain control off */\r
+#define LFXTDRIVE0 (0x0040u) /* LFXT Drive Level mode Bit 0 */\r
+#define LFXTDRIVE1 (0x0080u) /* LFXT Drive Level mode Bit 1 */\r
+#define HFXTOFF (0x0100u) /* High Frequency Oscillator disable */\r
+#define HFFREQ0 (0x0400u) /* HFXT frequency selection Bit 1 */\r
+#define HFFREQ1 (0x0800u) /* HFXT frequency selection Bit 0 */\r
+#define HFXTBYPASS (0x1000u) /* HFXT bypass mode : 0: internal 1:sourced from external pin */\r
+#define HFXTDRIVE0 (0x4000u) /* HFXT Drive Level mode Bit 0 */\r
+#define HFXTDRIVE1 (0x8000u) /* HFXT Drive Level mode Bit 1 */\r
+\r
+/* CSCTL4 Control Bits */\r
+#define LFXTOFF_L (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */\r
+#define SMCLKOFF_L (0x0002u) /* SMCLK Off */\r
+#define VLOOFF_L (0x0008u) /* VLO Off */\r
+#define LFXTBYPASS_L (0x0010u) /* LFXT bypass mode : 0: internal 1:sourced from external pin */\r
+#define LFXTAGCOFF_L (0x0020u) /* LFXT automatic gain control off */\r
+#define LFXTDRIVE0_L (0x0040u) /* LFXT Drive Level mode Bit 0 */\r
+#define LFXTDRIVE1_L (0x0080u) /* LFXT Drive Level mode Bit 1 */\r
+\r
+/* CSCTL4 Control Bits */\r
+#define HFXTOFF_H (0x0001u) /* High Frequency Oscillator disable */\r
+#define HFFREQ0_H (0x0004u) /* HFXT frequency selection Bit 1 */\r
+#define HFFREQ1_H (0x0008u) /* HFXT frequency selection Bit 0 */\r
+#define HFXTBYPASS_H (0x0010u) /* HFXT bypass mode : 0: internal 1:sourced from external pin */\r
+#define HFXTDRIVE0_H (0x0040u) /* HFXT Drive Level mode Bit 0 */\r
+#define HFXTDRIVE1_H (0x0080u) /* HFXT Drive Level mode Bit 1 */\r
+\r
+#define LFXTDRIVE_0 (0x0000u) /* LFXT Drive Level mode: 0 */\r
+#define LFXTDRIVE_1 (0x0040u) /* LFXT Drive Level mode: 1 */\r
+#define LFXTDRIVE_2 (0x0080u) /* LFXT Drive Level mode: 2 */\r
+#define LFXTDRIVE_3 (0x00C0u) /* LFXT Drive Level mode: 3 */\r
+\r
+#define HFFREQ_0 (0x0000u) /* HFXT frequency selection: 0 */\r
+#define HFFREQ_1 (0x0400u) /* HFXT frequency selection: 1 */\r
+#define HFFREQ_2 (0x0800u) /* HFXT frequency selection: 2 */\r
+#define HFFREQ_3 (0x0C00u) /* HFXT frequency selection: 3 */\r
+\r
+#define HFXTDRIVE_0 (0x0000u) /* HFXT Drive Level mode: 0 */\r
+#define HFXTDRIVE_1 (0x4000u) /* HFXT Drive Level mode: 1 */\r
+#define HFXTDRIVE_2 (0x8000u) /* HFXT Drive Level mode: 2 */\r
+#define HFXTDRIVE_3 (0xC000u) /* HFXT Drive Level mode: 3 */\r
+\r
+/* CSCTL5 Control Bits */\r
+#define LFXTOFFG (0x0001u) /* LFXT Low Frequency Oscillator Fault Flag */\r
+#define HFXTOFFG (0x0002u) /* HFXT High Frequency Oscillator Fault Flag */\r
+#define ENSTFCNT1 (0x0040u) /* Enable start counter for XT1 */\r
+#define ENSTFCNT2 (0x0080u) /* Enable start counter for XT2 */\r
+\r
+/* CSCTL5 Control Bits */\r
+#define LFXTOFFG_L (0x0001u) /* LFXT Low Frequency Oscillator Fault Flag */\r
+#define HFXTOFFG_L (0x0002u) /* HFXT High Frequency Oscillator Fault Flag */\r
+#define ENSTFCNT1_L (0x0040u) /* Enable start counter for XT1 */\r
+#define ENSTFCNT2_L (0x0080u) /* Enable start counter for XT2 */\r
+\r
+/* CSCTL6 Control Bits */\r
+#define ACLKREQEN (0x0001u) /* ACLK Clock Request Enable */\r
+#define MCLKREQEN (0x0002u) /* MCLK Clock Request Enable */\r
+#define SMCLKREQEN (0x0004u) /* SMCLK Clock Request Enable */\r
+#define MODCLKREQEN (0x0008u) /* MODOSC Clock Request Enable */\r
+\r
+/* CSCTL6 Control Bits */\r
+#define ACLKREQEN_L (0x0001u) /* ACLK Clock Request Enable */\r
+#define MCLKREQEN_L (0x0002u) /* MCLK Clock Request Enable */\r
+#define SMCLKREQEN_L (0x0004u) /* SMCLK Clock Request Enable */\r
+#define MODCLKREQEN_L (0x0008u) /* MODOSC Clock Request Enable */\r
+\r
+#endif\r
+/************************************************************\r
+* DMA_X\r
+************************************************************/\r
+#ifdef __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */\r
+\r
+#define OFS_DMACTL0 (0x0000u) /* DMA Module Control 0 */\r
+#define OFS_DMACTL0_L OFS_DMACTL0\r
+#define OFS_DMACTL0_H OFS_DMACTL0+1\r
+#define OFS_DMACTL1 (0x0002u) /* DMA Module Control 1 */\r
+#define OFS_DMACTL1_L OFS_DMACTL1\r
+#define OFS_DMACTL1_H OFS_DMACTL1+1\r
+#define OFS_DMACTL2 (0x0004u) /* DMA Module Control 2 */\r
+#define OFS_DMACTL2_L OFS_DMACTL2\r
+#define OFS_DMACTL2_H OFS_DMACTL2+1\r
+#define OFS_DMACTL3 (0x0006u) /* DMA Module Control 3 */\r
+#define OFS_DMACTL3_L OFS_DMACTL3\r
+#define OFS_DMACTL3_H OFS_DMACTL3+1\r
+#define OFS_DMACTL4 (0x0008u) /* DMA Module Control 4 */\r
+#define OFS_DMACTL4_L OFS_DMACTL4\r
+#define OFS_DMACTL4_H OFS_DMACTL4+1\r
+#define OFS_DMAIV (0x000Eu) /* DMA Interrupt Vector Word */\r
+#define OFS_DMAIV_L OFS_DMAIV\r
+#define OFS_DMAIV_H OFS_DMAIV+1\r
+\r
+#define OFS_DMA0CTL (0x0010u) /* DMA Channel 0 Control */\r
+#define OFS_DMA0CTL_L OFS_DMA0CTL\r
+#define OFS_DMA0CTL_H OFS_DMA0CTL+1\r
+#define OFS_DMA0SA (0x0012u) /* DMA Channel 0 Source Address */\r
+#define OFS_DMA0DA (0x0016u) /* DMA Channel 0 Destination Address */\r
+#define OFS_DMA0SZ (0x001Au) /* DMA Channel 0 Transfer Size */\r
+\r
+#define OFS_DMA1CTL (0x0020u) /* DMA Channel 1 Control */\r
+#define OFS_DMA1CTL_L OFS_DMA1CTL\r
+#define OFS_DMA1CTL_H OFS_DMA1CTL+1\r
+#define OFS_DMA1SA (0x0022u) /* DMA Channel 1 Source Address */\r
+#define OFS_DMA1DA (0x0026u) /* DMA Channel 1 Destination Address */\r
+#define OFS_DMA1SZ (0x002Au) /* DMA Channel 1 Transfer Size */\r
+\r
+#define OFS_DMA2CTL (0x0030u) /* DMA Channel 2 Control */\r
+#define OFS_DMA2CTL_L OFS_DMA2CTL\r
+#define OFS_DMA2CTL_H OFS_DMA2CTL+1\r
+#define OFS_DMA2SA (0x0032u) /* DMA Channel 2 Source Address */\r
+#define OFS_DMA2DA (0x0036u) /* DMA Channel 2 Destination Address */\r
+#define OFS_DMA2SZ (0x003Au) /* DMA Channel 2 Transfer Size */\r
+\r
+/* DMACTL0 Control Bits */\r
+#define DMA0TSEL0 (0x0001u) /* DMA channel 0 transfer select bit 0 */\r
+#define DMA0TSEL1 (0x0002u) /* DMA channel 0 transfer select bit 1 */\r
+#define DMA0TSEL2 (0x0004u) /* DMA channel 0 transfer select bit 2 */\r
+#define DMA0TSEL3 (0x0008u) /* DMA channel 0 transfer select bit 3 */\r
+#define DMA0TSEL4 (0x0010u) /* DMA channel 0 transfer select bit 4 */\r
+#define DMA1TSEL0 (0x0100u) /* DMA channel 1 transfer select bit 0 */\r
+#define DMA1TSEL1 (0x0200u) /* DMA channel 1 transfer select bit 1 */\r
+#define DMA1TSEL2 (0x0400u) /* DMA channel 1 transfer select bit 2 */\r
+#define DMA1TSEL3 (0x0800u) /* DMA channel 1 transfer select bit 3 */\r
+#define DMA1TSEL4 (0x1000u) /* DMA channel 1 transfer select bit 4 */\r
+\r
+/* DMACTL0 Control Bits */\r
+#define DMA0TSEL0_L (0x0001u) /* DMA channel 0 transfer select bit 0 */\r
+#define DMA0TSEL1_L (0x0002u) /* DMA channel 0 transfer select bit 1 */\r
+#define DMA0TSEL2_L (0x0004u) /* DMA channel 0 transfer select bit 2 */\r
+#define DMA0TSEL3_L (0x0008u) /* DMA channel 0 transfer select bit 3 */\r
+#define DMA0TSEL4_L (0x0010u) /* DMA channel 0 transfer select bit 4 */\r
+\r
+/* DMACTL0 Control Bits */\r
+#define DMA1TSEL0_H (0x0001u) /* DMA channel 1 transfer select bit 0 */\r
+#define DMA1TSEL1_H (0x0002u) /* DMA channel 1 transfer select bit 1 */\r
+#define DMA1TSEL2_H (0x0004u) /* DMA channel 1 transfer select bit 2 */\r
+#define DMA1TSEL3_H (0x0008u) /* DMA channel 1 transfer select bit 3 */\r
+#define DMA1TSEL4_H (0x0010u) /* DMA channel 1 transfer select bit 4 */\r
+\r
+/* DMACTL01 Control Bits */\r
+#define DMA2TSEL0 (0x0001u) /* DMA channel 2 transfer select bit 0 */\r
+#define DMA2TSEL1 (0x0002u) /* DMA channel 2 transfer select bit 1 */\r
+#define DMA2TSEL2 (0x0004u) /* DMA channel 2 transfer select bit 2 */\r
+#define DMA2TSEL3 (0x0008u) /* DMA channel 2 transfer select bit 3 */\r
+#define DMA2TSEL4 (0x0010u) /* DMA channel 2 transfer select bit 4 */\r
+\r
+/* DMACTL01 Control Bits */\r
+#define DMA2TSEL0_L (0x0001u) /* DMA channel 2 transfer select bit 0 */\r
+#define DMA2TSEL1_L (0x0002u) /* DMA channel 2 transfer select bit 1 */\r
+#define DMA2TSEL2_L (0x0004u) /* DMA channel 2 transfer select bit 2 */\r
+#define DMA2TSEL3_L (0x0008u) /* DMA channel 2 transfer select bit 3 */\r
+#define DMA2TSEL4_L (0x0010u) /* DMA channel 2 transfer select bit 4 */\r
+\r
+/* DMACTL4 Control Bits */\r
+#define ENNMI (0x0001u) /* Enable NMI interruption of DMA */\r
+#define ROUNDROBIN (0x0002u) /* Round-Robin DMA channel priorities */\r
+#define DMARMWDIS (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */\r
+\r
+/* DMACTL4 Control Bits */\r
+#define ENNMI_L (0x0001u) /* Enable NMI interruption of DMA */\r
+#define ROUNDROBIN_L (0x0002u) /* Round-Robin DMA channel priorities */\r
+#define DMARMWDIS_L (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */\r
+\r
+/* DMAxCTL Control Bits */\r
+#define DMAREQ (0x0001u) /* Initiate DMA transfer with DMATSEL */\r
+#define DMAABORT (0x0002u) /* DMA transfer aborted by NMI */\r
+#define DMAIE (0x0004u) /* DMA interrupt enable */\r
+#define DMAIFG (0x0008u) /* DMA interrupt flag */\r
+#define DMAEN (0x0010u) /* DMA enable */\r
+#define DMALEVEL (0x0020u) /* DMA level sensitive trigger select */\r
+#define DMASRCBYTE (0x0040u) /* DMA source byte */\r
+#define DMADSTBYTE (0x0080u) /* DMA destination byte */\r
+#define DMASRCINCR0 (0x0100u) /* DMA source increment bit 0 */\r
+#define DMASRCINCR1 (0x0200u) /* DMA source increment bit 1 */\r
+#define DMADSTINCR0 (0x0400u) /* DMA destination increment bit 0 */\r
+#define DMADSTINCR1 (0x0800u) /* DMA destination increment bit 1 */\r
+#define DMADT0 (0x1000u) /* DMA transfer mode bit 0 */\r
+#define DMADT1 (0x2000u) /* DMA transfer mode bit 1 */\r
+#define DMADT2 (0x4000u) /* DMA transfer mode bit 2 */\r
+\r
+/* DMAxCTL Control Bits */\r
+#define DMAREQ_L (0x0001u) /* Initiate DMA transfer with DMATSEL */\r
+#define DMAABORT_L (0x0002u) /* DMA transfer aborted by NMI */\r
+#define DMAIE_L (0x0004u) /* DMA interrupt enable */\r
+#define DMAIFG_L (0x0008u) /* DMA interrupt flag */\r
+#define DMAEN_L (0x0010u) /* DMA enable */\r
+#define DMALEVEL_L (0x0020u) /* DMA level sensitive trigger select */\r
+#define DMASRCBYTE_L (0x0040u) /* DMA source byte */\r
+#define DMADSTBYTE_L (0x0080u) /* DMA destination byte */\r
+\r
+/* DMAxCTL Control Bits */\r
+#define DMASRCINCR0_H (0x0001u) /* DMA source increment bit 0 */\r
+#define DMASRCINCR1_H (0x0002u) /* DMA source increment bit 1 */\r
+#define DMADSTINCR0_H (0x0004u) /* DMA destination increment bit 0 */\r
+#define DMADSTINCR1_H (0x0008u) /* DMA destination increment bit 1 */\r
+#define DMADT0_H (0x0010u) /* DMA transfer mode bit 0 */\r
+#define DMADT1_H (0x0020u) /* DMA transfer mode bit 1 */\r
+#define DMADT2_H (0x0040u) /* DMA transfer mode bit 2 */\r
+\r
+#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */\r
+#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */\r
+#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */\r
+#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */\r
+\r
+#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */\r
+#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */\r
+#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */\r
+#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */\r
+\r
+#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */\r
+#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */\r
+#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */\r
+#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */\r
+\r
+#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */\r
+#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */\r
+#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */\r
+#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */\r
+#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */\r
+#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */\r
+#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */\r
+#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */\r
+\r
+/* DMAIV Definitions */\r
+#define DMAIV_NONE (0x0000u) /* No Interrupt pending */\r
+#define DMAIV_DMA0IFG (0x0002u) /* DMA0IFG*/\r
+#define DMAIV_DMA1IFG (0x0004u) /* DMA1IFG*/\r
+#define DMAIV_DMA2IFG (0x0006u) /* DMA2IFG*/\r
+\r
+#endif\r
+/************************************************************\r
+* EXTENDED SCAN INTERFACE\r
+************************************************************/\r
+#ifdef __MSP430_HAS_ESI__ /* Definition to show that Module is available */\r
+\r
+#define OFS_ESIDEBUG1 (0x0000u) /* ESI debug register 1 */\r
+#define OFS_ESIDEBUG1_L OFS_ESIDEBUG1\r
+#define OFS_ESIDEBUG1_H OFS_ESIDEBUG1+1\r
+#define OFS_ESIDEBUG2 (0x0002u) /* ESI debug register 2 */\r
+#define OFS_ESIDEBUG2_L OFS_ESIDEBUG2\r
+#define OFS_ESIDEBUG2_H OFS_ESIDEBUG2+1\r
+#define OFS_ESIDEBUG3 (0x0004u) /* ESI debug register 3 */\r
+#define OFS_ESIDEBUG3_L OFS_ESIDEBUG3\r
+#define OFS_ESIDEBUG3_H OFS_ESIDEBUG3+1\r
+#define OFS_ESIDEBUG4 (0x0006u) /* ESI debug register 4 */\r
+#define OFS_ESIDEBUG4_L OFS_ESIDEBUG4\r
+#define OFS_ESIDEBUG4_H OFS_ESIDEBUG4+1\r
+#define OFS_ESIDEBUG5 (0x0008u) /* ESI debug register 5 */\r
+#define OFS_ESIDEBUG5_L OFS_ESIDEBUG5\r
+#define OFS_ESIDEBUG5_H OFS_ESIDEBUG5+1\r
+#define OFS_ESICNT0 (0x0010u) /* ESI PSM counter 0 */\r
+#define OFS_ESICNT0_L OFS_ESICNT0\r
+#define OFS_ESICNT0_H OFS_ESICNT0+1\r
+#define OFS_ESICNT1 (0x0012u) /* ESI PSM counter 1 */\r
+#define OFS_ESICNT1_L OFS_ESICNT1\r
+#define OFS_ESICNT1_H OFS_ESICNT1+1\r
+#define OFS_ESICNT2 (0x0014u) /* ESI PSM counter 2 */\r
+#define OFS_ESICNT2_L OFS_ESICNT2\r
+#define OFS_ESICNT2_H OFS_ESICNT2+1\r
+#define OFS_ESICNT3 (0x0016u) /* ESI oscillator counter register */\r
+#define OFS_ESICNT3_L OFS_ESICNT3\r
+#define OFS_ESICNT3_H OFS_ESICNT3+1\r
+#define OFS_ESIIV (0x001Au) /* ESI interrupt vector */\r
+#define OFS_ESIIV_L OFS_ESIIV\r
+#define OFS_ESIIV_H OFS_ESIIV+1\r
+#define OFS_ESIINT1 (0x001Cu) /* ESI interrupt register 1 */\r
+#define OFS_ESIINT1_L OFS_ESIINT1\r
+#define OFS_ESIINT1_H OFS_ESIINT1+1\r
+#define OFS_ESIINT2 (0x001Eu) /* ESI interrupt register 2 */\r
+#define OFS_ESIINT2_L OFS_ESIINT2\r
+#define OFS_ESIINT2_H OFS_ESIINT2+1\r
+#define OFS_ESIAFE (0x0020u) /* ESI AFE control register */\r
+#define OFS_ESIAFE_L OFS_ESIAFE\r
+#define OFS_ESIAFE_H OFS_ESIAFE+1\r
+#define OFS_ESIPPU (0x0022u) /* ESI PPU control register */\r
+#define OFS_ESIPPU_L OFS_ESIPPU\r
+#define OFS_ESIPPU_H OFS_ESIPPU+1\r
+#define OFS_ESITSM (0x0024u) /* ESI TSM control register */\r
+#define OFS_ESITSM_L OFS_ESITSM\r
+#define OFS_ESITSM_H OFS_ESITSM+1\r
+#define OFS_ESIPSM (0x0026u) /* ESI PSM control register */\r
+#define OFS_ESIPSM_L OFS_ESIPSM\r
+#define OFS_ESIPSM_H OFS_ESIPSM+1\r
+#define OFS_ESIOSC (0x0028u) /* ESI oscillator control register*/\r
+#define OFS_ESIOSC_L OFS_ESIOSC\r
+#define OFS_ESIOSC_H OFS_ESIOSC+1\r
+#define OFS_ESICTL (0x002Au) /* ESI control register */\r
+#define OFS_ESICTL_L OFS_ESICTL\r
+#define OFS_ESICTL_H OFS_ESICTL+1\r
+#define OFS_ESITHR1 (0x002Cu) /* ESI PSM Counter Threshold 1 register */\r
+#define OFS_ESITHR1_L OFS_ESITHR1\r
+#define OFS_ESITHR1_H OFS_ESITHR1+1\r
+#define OFS_ESITHR2 (0x002Eu) /* ESI PSM Counter Threshold 2 register */\r
+#define OFS_ESITHR2_L OFS_ESITHR2\r
+#define OFS_ESITHR2_H OFS_ESITHR2+1\r
+#define OFS_ESIDAC1R0 (0x0040u) /* ESI DAC1 register 0 */\r
+#define OFS_ESIDAC1R0_L OFS_ESIDAC1R0\r
+#define OFS_ESIDAC1R0_H OFS_ESIDAC1R0+1\r
+#define OFS_ESIDAC1R1 (0x0042u) /* ESI DAC1 register 1 */\r
+#define OFS_ESIDAC1R1_L OFS_ESIDAC1R1\r
+#define OFS_ESIDAC1R1_H OFS_ESIDAC1R1+1\r
+#define OFS_ESIDAC1R2 (0x0044u) /* ESI DAC1 register 2 */\r
+#define OFS_ESIDAC1R2_L OFS_ESIDAC1R2\r
+#define OFS_ESIDAC1R2_H OFS_ESIDAC1R2+1\r
+#define OFS_ESIDAC1R3 (0x0046u) /* ESI DAC1 register 3 */\r
+#define OFS_ESIDAC1R3_L OFS_ESIDAC1R3\r
+#define OFS_ESIDAC1R3_H OFS_ESIDAC1R3+1\r
+#define OFS_ESIDAC1R4 (0x0048u) /* ESI DAC1 register 4 */\r
+#define OFS_ESIDAC1R4_L OFS_ESIDAC1R4\r
+#define OFS_ESIDAC1R4_H OFS_ESIDAC1R4+1\r
+#define OFS_ESIDAC1R5 (0x004Au) /* ESI DAC1 register 5 */\r
+#define OFS_ESIDAC1R5_L OFS_ESIDAC1R5\r
+#define OFS_ESIDAC1R5_H OFS_ESIDAC1R5+1\r
+#define OFS_ESIDAC1R6 (0x004Cu) /* ESI DAC1 register 6 */\r
+#define OFS_ESIDAC1R6_L OFS_ESIDAC1R6\r
+#define OFS_ESIDAC1R6_H OFS_ESIDAC1R6+1\r
+#define OFS_ESIDAC1R7 (0x004Eu) /* ESI DAC1 register 7 */\r
+#define OFS_ESIDAC1R7_L OFS_ESIDAC1R7\r
+#define OFS_ESIDAC1R7_H OFS_ESIDAC1R7+1\r
+#define OFS_ESIDAC2R0 (0x0050u) /* ESI DAC2 register 0 */\r
+#define OFS_ESIDAC2R0_L OFS_ESIDAC2R0\r
+#define OFS_ESIDAC2R0_H OFS_ESIDAC2R0+1\r
+#define OFS_ESIDAC2R1 (0x0052u) /* ESI DAC2 register 1 */\r
+#define OFS_ESIDAC2R1_L OFS_ESIDAC2R1\r
+#define OFS_ESIDAC2R1_H OFS_ESIDAC2R1+1\r
+#define OFS_ESIDAC2R2 (0x0054u) /* ESI DAC2 register 2 */\r
+#define OFS_ESIDAC2R2_L OFS_ESIDAC2R2\r
+#define OFS_ESIDAC2R2_H OFS_ESIDAC2R2+1\r
+#define OFS_ESIDAC2R3 (0x0056u) /* ESI DAC2 register 3 */\r
+#define OFS_ESIDAC2R3_L OFS_ESIDAC2R3\r
+#define OFS_ESIDAC2R3_H OFS_ESIDAC2R3+1\r
+#define OFS_ESIDAC2R4 (0x0058u) /* ESI DAC2 register 4 */\r
+#define OFS_ESIDAC2R4_L OFS_ESIDAC2R4\r
+#define OFS_ESIDAC2R4_H OFS_ESIDAC2R4+1\r
+#define OFS_ESIDAC2R5 (0x005Au) /* ESI DAC2 register 5 */\r
+#define OFS_ESIDAC2R5_L OFS_ESIDAC2R5\r
+#define OFS_ESIDAC2R5_H OFS_ESIDAC2R5+1\r
+#define OFS_ESIDAC2R6 (0x005Cu) /* ESI DAC2 register 6 */\r
+#define OFS_ESIDAC2R6_L OFS_ESIDAC2R6\r
+#define OFS_ESIDAC2R6_H OFS_ESIDAC2R6+1\r
+#define OFS_ESIDAC2R7 (0x005Eu) /* ESI DAC2 register 7 */\r
+#define OFS_ESIDAC2R7_L OFS_ESIDAC2R7\r
+#define OFS_ESIDAC2R7_H OFS_ESIDAC2R7+1\r
+#define OFS_ESITSM0 (0x0060u) /* ESI TSM 0 */\r
+#define OFS_ESITSM0_L OFS_ESITSM0\r
+#define OFS_ESITSM0_H OFS_ESITSM0+1\r
+#define OFS_ESITSM1 (0x0062u) /* ESI TSM 1 */\r
+#define OFS_ESITSM1_L OFS_ESITSM1\r
+#define OFS_ESITSM1_H OFS_ESITSM1+1\r
+#define OFS_ESITSM2 (0x0064u) /* ESI TSM 2 */\r
+#define OFS_ESITSM2_L OFS_ESITSM2\r
+#define OFS_ESITSM2_H OFS_ESITSM2+1\r
+#define OFS_ESITSM3 (0x0066u) /* ESI TSM 3 */\r
+#define OFS_ESITSM3_L OFS_ESITSM3\r
+#define OFS_ESITSM3_H OFS_ESITSM3+1\r
+#define OFS_ESITSM4 (0x0068u) /* ESI TSM 4 */\r
+#define OFS_ESITSM4_L OFS_ESITSM4\r
+#define OFS_ESITSM4_H OFS_ESITSM4+1\r
+#define OFS_ESITSM5 (0x006Au) /* ESI TSM 5 */\r
+#define OFS_ESITSM5_L OFS_ESITSM5\r
+#define OFS_ESITSM5_H OFS_ESITSM5+1\r
+#define OFS_ESITSM6 (0x006Cu) /* ESI TSM 6 */\r
+#define OFS_ESITSM6_L OFS_ESITSM6\r
+#define OFS_ESITSM6_H OFS_ESITSM6+1\r
+#define OFS_ESITSM7 (0x006Eu) /* ESI TSM 7 */\r
+#define OFS_ESITSM7_L OFS_ESITSM7\r
+#define OFS_ESITSM7_H OFS_ESITSM7+1\r
+#define OFS_ESITSM8 (0x0070u) /* ESI TSM 8 */\r
+#define OFS_ESITSM8_L OFS_ESITSM8\r
+#define OFS_ESITSM8_H OFS_ESITSM8+1\r
+#define OFS_ESITSM9 (0x0072u) /* ESI TSM 9 */\r
+#define OFS_ESITSM9_L OFS_ESITSM9\r
+#define OFS_ESITSM9_H OFS_ESITSM9+1\r
+#define OFS_ESITSM10 (0x0074u) /* ESI TSM 10 */\r
+#define OFS_ESITSM10_L OFS_ESITSM10\r
+#define OFS_ESITSM10_H OFS_ESITSM10+1\r
+#define OFS_ESITSM11 (0x0076u) /* ESI TSM 11 */\r
+#define OFS_ESITSM11_L OFS_ESITSM11\r
+#define OFS_ESITSM11_H OFS_ESITSM11+1\r
+#define OFS_ESITSM12 (0x0078u) /* ESI TSM 12 */\r
+#define OFS_ESITSM12_L OFS_ESITSM12\r
+#define OFS_ESITSM12_H OFS_ESITSM12+1\r
+#define OFS_ESITSM13 (0x007Au) /* ESI TSM 13 */\r
+#define OFS_ESITSM13_L OFS_ESITSM13\r
+#define OFS_ESITSM13_H OFS_ESITSM13+1\r
+#define OFS_ESITSM14 (0x007Cu) /* ESI TSM 14 */\r
+#define OFS_ESITSM14_L OFS_ESITSM14\r
+#define OFS_ESITSM14_H OFS_ESITSM14+1\r
+#define OFS_ESITSM15 (0x007Eu) /* ESI TSM 15 */\r
+#define OFS_ESITSM15_L OFS_ESITSM15\r
+#define OFS_ESITSM15_H OFS_ESITSM15+1\r
+#define OFS_ESITSM16 (0x0080u) /* ESI TSM 16 */\r
+#define OFS_ESITSM16_L OFS_ESITSM16\r
+#define OFS_ESITSM16_H OFS_ESITSM16+1\r
+#define OFS_ESITSM17 (0x0082u) /* ESI TSM 17 */\r
+#define OFS_ESITSM17_L OFS_ESITSM17\r
+#define OFS_ESITSM17_H OFS_ESITSM17+1\r
+#define OFS_ESITSM18 (0x0084u) /* ESI TSM 18 */\r
+#define OFS_ESITSM18_L OFS_ESITSM18\r
+#define OFS_ESITSM18_H OFS_ESITSM18+1\r
+#define OFS_ESITSM19 (0x0086u) /* ESI TSM 19 */\r
+#define OFS_ESITSM19_L OFS_ESITSM19\r
+#define OFS_ESITSM19_H OFS_ESITSM19+1\r
+#define OFS_ESITSM20 (0x0088u) /* ESI TSM 20 */\r
+#define OFS_ESITSM20_L OFS_ESITSM20\r
+#define OFS_ESITSM20_H OFS_ESITSM20+1\r
+#define OFS_ESITSM21 (0x008Au) /* ESI TSM 21 */\r
+#define OFS_ESITSM21_L OFS_ESITSM21\r
+#define OFS_ESITSM21_H OFS_ESITSM21+1\r
+#define OFS_ESITSM22 (0x008Cu) /* ESI TSM 22 */\r
+#define OFS_ESITSM22_L OFS_ESITSM22\r
+#define OFS_ESITSM22_H OFS_ESITSM22+1\r
+#define OFS_ESITSM23 (0x008Eu) /* ESI TSM 23 */\r
+#define OFS_ESITSM23_L OFS_ESITSM23\r
+#define OFS_ESITSM23_H OFS_ESITSM23+1\r
+#define OFS_ESITSM24 (0x0090u) /* ESI TSM 24 */\r
+#define OFS_ESITSM24_L OFS_ESITSM24\r
+#define OFS_ESITSM24_H OFS_ESITSM24+1\r
+#define OFS_ESITSM25 (0x0092u) /* ESI TSM 25 */\r
+#define OFS_ESITSM25_L OFS_ESITSM25\r
+#define OFS_ESITSM25_H OFS_ESITSM25+1\r
+#define OFS_ESITSM26 (0x0094u) /* ESI TSM 26 */\r
+#define OFS_ESITSM26_L OFS_ESITSM26\r
+#define OFS_ESITSM26_H OFS_ESITSM26+1\r
+#define OFS_ESITSM27 (0x0096u) /* ESI TSM 27 */\r
+#define OFS_ESITSM27_L OFS_ESITSM27\r
+#define OFS_ESITSM27_H OFS_ESITSM27+1\r
+#define OFS_ESITSM28 (0x0098u) /* ESI TSM 28 */\r
+#define OFS_ESITSM28_L OFS_ESITSM28\r
+#define OFS_ESITSM28_H OFS_ESITSM28+1\r
+#define OFS_ESITSM29 (0x009Au) /* ESI TSM 29 */\r
+#define OFS_ESITSM29_L OFS_ESITSM29\r
+#define OFS_ESITSM29_H OFS_ESITSM29+1\r
+#define OFS_ESITSM30 (0x009Cu) /* ESI TSM 30 */\r
+#define OFS_ESITSM30_L OFS_ESITSM30\r
+#define OFS_ESITSM30_H OFS_ESITSM30+1\r
+#define OFS_ESITSM31 (0x009Eu) /* ESI TSM 31 */\r
+#define OFS_ESITSM31_L OFS_ESITSM31\r
+#define OFS_ESITSM31_H OFS_ESITSM31+1\r
+\r
+/* ESIIV Control Bits */\r
+\r
+#define ESIIV_NONE (0x0000u) /* No ESI Interrupt Pending */\r
+#define ESIIV_ESIIFG1 (0x0002u) /* rising edge of the ESISTOP(tsm) */\r
+#define ESIIV_ESIIFG0 (0x0004u) /* ESIOUT0 to ESIOUT3 conditions selected by ESIIFGSETx bits */\r
+#define ESIIV_ESIIFG8 (0x0006u) /* ESIOUT4 to ESIOUT7 conditions selected by ESIIFGSET2x bits */\r
+#define ESIIV_ESIIFG3 (0x0008u) /* ESICNT1 counter conditions selected with the ESITHR1 and ESITHR2 registers */\r
+#define ESIIV_ESIIFG6 (0x000Au) /* PSM transitions to a state with a Q7 bit */\r
+#define ESIIV_ESIIFG5 (0x000Cu) /* PSM transitions to a state with a Q6 bit */\r
+#define ESIIV_ESIIFG4 (0x000Eu) /* ESICNT2 counter conditions selected with the ESIIS2x bits */\r
+#define ESIIV_ESIIFG7 (0x0010u) /* ESICNT0 counter conditions selected with the ESIIS0x bits */\r
+#define ESIIV_ESIIFG2 (0x0012u) /* start of a TSM sequence */\r
+\r
+/* ESIINT1 Control Bits */\r
+#define ESIIFGSET22 (0x8000u) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET21 (0x4000u) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET20 (0x2000u) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET12 (0x1000u) /* ESIIFG0 interrupt flag source */\r
+#define ESIIFGSET11 (0x0800u) /* ESIIFG0 interrupt flag source */\r
+#define ESIIFGSET10 (0x0400u) /* ESIIFG0 interrupt flag source */\r
+#define ESIIE8 (0x0100u) /* Interrupt enable */\r
+#define ESIIE7 (0x0080u) /* Interrupt enable */\r
+#define ESIIE6 (0x0040u) /* Interrupt enable */\r
+#define ESIIE5 (0x0020u) /* Interrupt enable */\r
+#define ESIIE4 (0x0010u) /* Interrupt enable */\r
+#define ESIIE3 (0x0008u) /* Interrupt enable */\r
+#define ESIIE2 (0x0004u) /* Interrupt enable */\r
+#define ESIIE1 (0x0002u) /* Interrupt enable */\r
+#define ESIIE0 (0x0001u) /* Interrupt enable */\r
+\r
+/* ESIINT1 Control Bits */\r
+#define ESIIE7_L (0x0080u) /* Interrupt enable */\r
+#define ESIIE6_L (0x0040u) /* Interrupt enable */\r
+#define ESIIE5_L (0x0020u) /* Interrupt enable */\r
+#define ESIIE4_L (0x0010u) /* Interrupt enable */\r
+#define ESIIE3_L (0x0008u) /* Interrupt enable */\r
+#define ESIIE2_L (0x0004u) /* Interrupt enable */\r
+#define ESIIE1_L (0x0002u) /* Interrupt enable */\r
+#define ESIIE0_L (0x0001u) /* Interrupt enable */\r
+\r
+/* ESIINT1 Control Bits */\r
+#define ESIIFGSET22_H (0x0080u) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET21_H (0x0040u) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET20_H (0x0020u) /* ESIIFG8 interrupt flag source */\r
+#define ESIIFGSET12_H (0x0010u) /* ESIIFG0 interrupt flag source */\r
+#define ESIIFGSET11_H (0x0008u) /* ESIIFG0 interrupt flag source */\r
+#define ESIIFGSET10_H (0x0004u) /* ESIIFG0 interrupt flag source */\r
+#define ESIIE8_H (0x0001u) /* Interrupt enable */\r
+\r
+#define ESIIFGSET2_0 (0x0000u) /* ESIIFG8 is set when ESIOUT4 is set */\r
+#define ESIIFGSET2_1 (0x2000u) /* ESIIFG8 is set when ESIOUT4 is reset */\r
+#define ESIIFGSET2_2 (0x4000u) /* ESIIFG8 is set when ESIOUT5 is set */\r
+#define ESIIFGSET2_3 (0x6000u) /* ESIIFG8 is set when ESIOUT5 is reset */\r
+#define ESIIFGSET2_4 (0x8000u) /* ESIIFG8 is set when ESIOUT6 is set */\r
+#define ESIIFGSET2_5 (0xA000u) /* ESIIFG8 is set when ESIOUT6 is reset */\r
+#define ESIIFGSET2_6 (0xC000u) /* ESIIFG8 is set when ESIOUT7 is set */\r
+#define ESIIFGSET2_7 (0xE000u) /* ESIIFG8 is set when ESIOUT7 is reset */\r
+#define ESIIFGSET1_0 (0x0000u) /* ESIIFG0 is set when ESIOUT0 is set */\r
+#define ESIIFGSET1_1 (0x0400u) /* ESIIFG0 is set when ESIOUT0 is reset */\r
+#define ESIIFGSET1_2 (0x0800u) /* ESIIFG0 is set when ESIOUT1 is set */\r
+#define ESIIFGSET1_3 (0x0C00u) /* ESIIFG0 is set when ESIOUT1 is reset */\r
+#define ESIIFGSET1_4 (0x1000u) /* ESIIFG0 is set when ESIOUT2 is set */\r
+#define ESIIFGSET1_5 (0x1400u) /* ESIIFG0 is set when ESIOUT2 is reset */\r
+#define ESIIFGSET1_6 (0x1800u) /* ESIIFG0 is set when ESIOUT3 is set */\r
+#define ESIIFGSET1_7 (0x1C00u) /* ESIIFG0 is set when ESIOUT3 is reset */\r
+\r
+/* ESIINT2 Control Bits */\r
+#define ESIIS21 (0x4000u) /* SIFIFG4 interrupt flag source */\r
+#define ESIIS20 (0x2000u) /* SIFIFG4 interrupt flag source */\r
+#define ESIIS01 (0x0800u) /* SIFIFG7 interrupt flag source */\r
+#define ESIIS00 (0x0400u) /* SIFIFG7 interrupt flag source */\r
+#define ESIIFG8 (0x0100u) /* ESIIFG8 interrupt pending */\r
+#define ESIIFG7 (0x0080u) /* ESIIFG7 interrupt pending */\r
+#define ESIIFG6 (0x0040u) /* ESIIFG6 interrupt pending */\r
+#define ESIIFG5 (0x0020u) /* ESIIFG5 interrupt pending */\r
+#define ESIIFG4 (0x0010u) /* ESIIFG4 interrupt pending */\r
+#define ESIIFG3 (0x0008u) /* ESIIFG3 interrupt pending */\r
+#define ESIIFG2 (0x0004u) /* ESIIFG2 interrupt pending */\r
+#define ESIIFG1 (0x0002u) /* ESIIFG1 interrupt pending */\r
+#define ESIIFG0 (0x0001u) /* ESIIFG0 interrupt pending */\r
+\r
+/* ESIINT2 Control Bits */\r
+#define ESIIFG7_L (0x0080u) /* ESIIFG7 interrupt pending */\r
+#define ESIIFG6_L (0x0040u) /* ESIIFG6 interrupt pending */\r
+#define ESIIFG5_L (0x0020u) /* ESIIFG5 interrupt pending */\r
+#define ESIIFG4_L (0x0010u) /* ESIIFG4 interrupt pending */\r
+#define ESIIFG3_L (0x0008u) /* ESIIFG3 interrupt pending */\r
+#define ESIIFG2_L (0x0004u) /* ESIIFG2 interrupt pending */\r
+#define ESIIFG1_L (0x0002u) /* ESIIFG1 interrupt pending */\r
+#define ESIIFG0_L (0x0001u) /* ESIIFG0 interrupt pending */\r
+\r
+/* ESIINT2 Control Bits */\r
+#define ESIIS21_H (0x0040u) /* SIFIFG4 interrupt flag source */\r
+#define ESIIS20_H (0x0020u) /* SIFIFG4 interrupt flag source */\r
+#define ESIIS01_H (0x0008u) /* SIFIFG7 interrupt flag source */\r
+#define ESIIS00_H (0x0004u) /* SIFIFG7 interrupt flag source */\r
+#define ESIIFG8_H (0x0001u) /* ESIIFG8 interrupt pending */\r
+\r
+#define ESIIS2_0 (0x0000u) /* SIFIFG4 interrupt flag source: SIFCNT2 */\r
+#define ESIIS2_1 (0x2000u) /* SIFIFG4 interrupt flag source: SIFCNT2 MOD 4 */\r
+#define ESIIS2_2 (0x4000u) /* SIFIFG4 interrupt flag source: SIFCNT2 MOD 256 */\r
+#define ESIIS2_3 (0x6000u) /* SIFIFG4 interrupt flag source: SIFCNT2 decrements from 01h to 00h */\r
+#define ESIIS0_0 (0x0000u) /* SIFIFG7 interrupt flag source: SIFCNT0 */\r
+#define ESIIS0_1 (0x0400u) /* SIFIFG7 interrupt flag source: SIFCNT0 MOD 4 */\r
+#define ESIIS0_2 (0x0800u) /* SIFIFG7 interrupt flag source: SIFCNT0 MOD 256 */\r
+#define ESIIS0_3 (0x0C00u) /* SIFIFG7 interrupt flag source: SIFCNT0 increments from FFFFh to 00h */\r
+\r
+/* ESIAFE Control Bits */\r
+#define ESIDAC2EN (0x0800u) /* Enable ESIDAC(tsm) control for DAC in AFE2 */\r
+#define ESICA2EN (0x0400u) /* Enable ESICA(tsm) control for comparator in AFE2 */\r
+#define ESICA2INV (0x0200u) /* Invert AFE2's comparator output */\r
+#define ESICA1INV (0x0100u) /* Invert AFE1's comparator output */\r
+#define ESICA2X (0x0080u) /* AFE2's comparator input select */\r
+#define ESICA1X (0x0040u) /* AFE1's comparator input select */\r
+#define ESICISEL (0x0020u) /* Comparator input select for AFE1 only */\r
+#define ESICACI3 (0x0010u) /* Comparator input select for AFE1 only */\r
+#define ESIVSS (0x0008u) /* Sample-and-hold ESIVSS select */\r
+#define ESIVCC2 (0x0004u) /* Mid-voltage generator */\r
+#define ESISH (0x0002u) /* Sample-and-hold enable */\r
+#define ESITEN (0x0001u) /* Excitation enable */\r
+\r
+/* ESIAFE Control Bits */\r
+#define ESICA2X_L (0x0080u) /* AFE2's comparator input select */\r
+#define ESICA1X_L (0x0040u) /* AFE1's comparator input select */\r
+#define ESICISEL_L (0x0020u) /* Comparator input select for AFE1 only */\r
+#define ESICACI3_L (0x0010u) /* Comparator input select for AFE1 only */\r
+#define ESIVSS_L (0x0008u) /* Sample-and-hold ESIVSS select */\r
+#define ESIVCC2_L (0x0004u) /* Mid-voltage generator */\r
+#define ESISH_L (0x0002u) /* Sample-and-hold enable */\r
+#define ESITEN_L (0x0001u) /* Excitation enable */\r
+\r
+/* ESIAFE Control Bits */\r
+#define ESIDAC2EN_H (0x0008u) /* Enable ESIDAC(tsm) control for DAC in AFE2 */\r
+#define ESICA2EN_H (0x0004u) /* Enable ESICA(tsm) control for comparator in AFE2 */\r
+#define ESICA2INV_H (0x0002u) /* Invert AFE2's comparator output */\r
+#define ESICA1INV_H (0x0001u) /* Invert AFE1's comparator output */\r
+\r
+/* ESIPPU Control Bits */\r
+#define ESITCHOUT1 (0x0200u) /* Latched AFE1 comparator output for test channel 1 */\r
+#define ESITCHOUT0 (0x0100u) /* Lachted AFE1 comparator output for test channel 0 */\r
+#define ESIOUT7 (0x0080u) /* Latched AFE2 comparator output when ESICH3 input is selected */\r
+#define ESIOUT6 (0x0040u) /* Latched AFE2 comparator output when ESICH2 input is selected */\r
+#define ESIOUT5 (0x0020u) /* Latched AFE2 comparator output when ESICH1 input is selected */\r
+#define ESIOUT4 (0x0010u) /* Latched AFE2 comparator output when ESICH0 input is selected */\r
+#define ESIOUT3 (0x0008u) /* Latched AFE1 comparator output when ESICH3 input is selected */\r
+#define ESIOUT2 (0x0004u) /* Latched AFE1 comparator output when ESICH2 input is selected */\r
+#define ESIOUT1 (0x0002u) /* Latched AFE1 comparator output when ESICH1 input is selected */\r
+#define ESIOUT0 (0x0001u) /* Latched AFE1 comparator output when ESICH0 input is selected */\r
+\r
+/* ESIPPU Control Bits */\r
+#define ESIOUT7_L (0x0080u) /* Latched AFE2 comparator output when ESICH3 input is selected */\r
+#define ESIOUT6_L (0x0040u) /* Latched AFE2 comparator output when ESICH2 input is selected */\r
+#define ESIOUT5_L (0x0020u) /* Latched AFE2 comparator output when ESICH1 input is selected */\r
+#define ESIOUT4_L (0x0010u) /* Latched AFE2 comparator output when ESICH0 input is selected */\r
+#define ESIOUT3_L (0x0008u) /* Latched AFE1 comparator output when ESICH3 input is selected */\r
+#define ESIOUT2_L (0x0004u) /* Latched AFE1 comparator output when ESICH2 input is selected */\r
+#define ESIOUT1_L (0x0002u) /* Latched AFE1 comparator output when ESICH1 input is selected */\r
+#define ESIOUT0_L (0x0001u) /* Latched AFE1 comparator output when ESICH0 input is selected */\r
+\r
+/* ESIPPU Control Bits */\r
+#define ESITCHOUT1_H (0x0002u) /* Latched AFE1 comparator output for test channel 1 */\r
+#define ESITCHOUT0_H (0x0001u) /* Lachted AFE1 comparator output for test channel 0 */\r
+\r
+/* ESITSM Control Bits */\r
+#define ESICLKAZSEL (0x4000u) /* Functionality selection of ESITSMx bit5 */\r
+#define ESITSMTRG1 (0x2000u) /* TSM start trigger selection */\r
+#define ESITSMTRG0 (0x1000u) /* TSM start trigger selection */\r
+#define ESISTART (0x0800u) /* TSM software start trigger */\r
+#define ESITSMRP (0x0400u) /* TSM repeat modee */\r
+#define ESIDIV3B2 (0x0200u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B1 (0x0100u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B0 (0x0080u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A2 (0x0040u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A1 (0x0020u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A0 (0x0010u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV21 (0x0008u) /* ACLK divider */\r
+#define ESIDIV20 (0x0004u) /* ACLK divider */\r
+#define ESIDIV11 (0x0002u) /* TSM SMCLK divider */\r
+#define ESIDIV10 (0x0001u) /* TSM SMCLK divider */\r
+\r
+/* ESITSM Control Bits */\r
+#define ESIDIV3B0_L (0x0080u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A2_L (0x0040u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A1_L (0x0020u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A0_L (0x0010u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV21_L (0x0008u) /* ACLK divider */\r
+#define ESIDIV20_L (0x0004u) /* ACLK divider */\r
+#define ESIDIV11_L (0x0002u) /* TSM SMCLK divider */\r
+#define ESIDIV10_L (0x0001u) /* TSM SMCLK divider */\r
+\r
+/* ESITSM Control Bits */\r
+#define ESICLKAZSEL_H (0x0040u) /* Functionality selection of ESITSMx bit5 */\r
+#define ESITSMTRG1_H (0x0020u) /* TSM start trigger selection */\r
+#define ESITSMTRG0_H (0x0010u) /* TSM start trigger selection */\r
+#define ESISTART_H (0x0008u) /* TSM software start trigger */\r
+#define ESITSMRP_H (0x0004u) /* TSM repeat modee */\r
+#define ESIDIV3B2_H (0x0002u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B1_H (0x0001u) /* TSM start trigger ACLK divider */\r
+\r
+#define ESITSMTRG_0 (0x0000u) /* Halt mode */\r
+#define ESITSMTRG_1 (0x1000u) /* TSM start trigger ACLK divider */\r
+#define ESITSMTRG_2 (0x2000u) /* Software trigger for TSM */\r
+#define ESITSMTRG_3 (0x3000u) /* Either the ACLK divider or the ESISTART biT */\r
+#define ESIDIV3B_0 (0x0000u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_1 (0x0080u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_2 (0x0100u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_3 (0x0180u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_4 (0x0200u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_5 (0x0280u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_6 (0x0300u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3B_7 (0x0380u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_0 (0x0000u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_1 (0x0010u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_2 (0x0020u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_3 (0x0030u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_4 (0x0040u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_5 (0x0050u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_6 (0x0060u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV3A_7 (0x0070u) /* TSM start trigger ACLK divider */\r
+#define ESIDIV2_0 (0x0000u) /* ACLK divider mode: 0 */\r
+#define ESIDIV2_1 (0x0004u) /* ACLK divider mode: 1 */\r
+#define ESIDIV2_2 (0x0008u) /* ACLK divider mode: 2 */\r
+#define ESIDIV2_3 (0x000Cu) /* ACLK divider mode: 3 */\r
+#define ESIDIV2__1 (0x0000u) /* ACLK divider = /1 */\r
+#define ESIDIV2__2 (0x0004u) /* ACLK divider = /2 */\r
+#define ESIDIV2__4 (0x0008u) /* ACLK divider = /4 */\r
+#define ESIDIV2__8 (0x000Cu) /* ACLK divider = /8 */\r
+#define ESIDIV1_0 (0x0000u) /* TSM SMCLK/ESIOSC divider mode: 0 */\r
+#define ESIDIV1_1 (0x0001u) /* TSM SMCLK/ESIOSC divider mode: 1 */\r
+#define ESIDIV1_2 (0x0002u) /* TSM SMCLK/ESIOSC divider mode: 2 */\r
+#define ESIDIV1_3 (0x0003u) /* TSM SMCLK/ESIOSC divider mode: 3 */\r
+#define ESIDIV1__1 (0x0000u) /* TSM SMCLK/ESIOSC divider = /1 */\r
+#define ESIDIV1__2 (0x0001u) /* TSM SMCLK/ESIOSC divider = /2 */\r
+#define ESIDIV1__4 (0x0002u) /* TSM SMCLK/ESIOSC divider = /4 */\r
+#define ESIDIV1__8 (0x0003u) /* TSM SMCLK/ESIOSC divider = /8 */\r
+\r
+/* ESIPSM Control Bits */\r
+#define ESICNT2RST (0x8000u) /* ESI Counter 2 reset */\r
+#define ESICNT1RST (0x4000u) /* ESI Counter 1 reset */\r
+#define ESICNT0RST (0x2000u) /* ESI Counter 0 reset */\r
+#define ESITEST4SEL1 (0x0200u) /* Output signal selection for SIFTEST4 pin */\r
+#define ESITEST4SEL0 (0x0100u) /* Output signal selection for SIFTEST4 pin */\r
+#define ESIV2SEL (0x0080u) /* Source Selection for V2 bit*/\r
+#define ESICNT2EN (0x0020u) /* ESICNT2 enable (down counter) */\r
+#define ESICNT1EN (0x0010u) /* ESICNT1 enable (up/down counter) */\r
+#define ESICNT0EN (0x0008u) /* ESICNT0 enable (up counter) */\r
+#define ESIQ7TRG (0x0004u) /* Enabling to use Q7 as trigger for a TSM sequence */\r
+#define ESIQ6EN (0x0001u) /* Q6 enable */\r
+\r
+/* ESIPSM Control Bits */\r
+#define ESIV2SEL_L (0x0080u) /* Source Selection for V2 bit*/\r
+#define ESICNT2EN_L (0x0020u) /* ESICNT2 enable (down counter) */\r
+#define ESICNT1EN_L (0x0010u) /* ESICNT1 enable (up/down counter) */\r
+#define ESICNT0EN_L (0x0008u) /* ESICNT0 enable (up counter) */\r
+#define ESIQ7TRG_L (0x0004u) /* Enabling to use Q7 as trigger for a TSM sequence */\r
+#define ESIQ6EN_L (0x0001u) /* Q6 enable */\r
+\r
+/* ESIPSM Control Bits */\r
+#define ESICNT2RST_H (0x0080u) /* ESI Counter 2 reset */\r
+#define ESICNT1RST_H (0x0040u) /* ESI Counter 1 reset */\r
+#define ESICNT0RST_H (0x0020u) /* ESI Counter 0 reset */\r
+#define ESITEST4SEL1_H (0x0002u) /* Output signal selection for SIFTEST4 pin */\r
+#define ESITEST4SEL0_H (0x0001u) /* Output signal selection for SIFTEST4 pin */\r
+\r
+#define ESITEST4SEL_0 (0x0000u) /* Q1 signal from PSM table */\r
+#define ESITEST4SEL_1 (0x0100u) /* Q2 signal from PSM table */\r
+#define ESITEST4SEL_2 (0x0200u) /* TSM clock signal from Timing State Machine */\r
+#define ESITEST4SEL_3 (0x0300u) /* AFE1's comparator output signal Comp1Out */\r
+\r
+/* ESIOSC Control Bits */\r
+#define ESICLKFQ5 (0x2000u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ4 (0x1000u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ3 (0x0800u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ2 (0x0400u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ1 (0x0200u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ0 (0x0100u) /* Internal oscillator frequency adjust */\r
+#define ESICLKGON (0x0002u) /* Internal oscillator control */\r
+#define ESIHFSEL (0x0001u) /* Internal oscillator enable */\r
+\r
+/* ESIOSC Control Bits */\r
+#define ESICLKGON_L (0x0002u) /* Internal oscillator control */\r
+#define ESIHFSEL_L (0x0001u) /* Internal oscillator enable */\r
+\r
+/* ESIOSC Control Bits */\r
+#define ESICLKFQ5_H (0x0020u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ4_H (0x0010u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ3_H (0x0008u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ2_H (0x0004u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ1_H (0x0002u) /* Internal oscillator frequency adjust */\r
+#define ESICLKFQ0_H (0x0001u) /* Internal oscillator frequency adjust */\r
+\r
+/* ESICTL Control Bits */\r
+#define ESIS3SEL2 (0x8000u) /* PPUS3 source select */\r
+#define ESIS3SEL1 (0x4000u) /* PPUS3 source select */\r
+#define ESIS3SEL0 (0x2000u) /* PPUS3 source select */\r
+#define ESIS2SEL2 (0x1000u) /* PPUS2 source select */\r
+#define ESIS2SEL1 (0x0800u) /* PPUS2 source select */\r
+#define ESIS2SEL0 (0x0400u) /* PPUS2 source select */\r
+#define ESIS1SEL2 (0x0200u) /* PPUS1 source select */\r
+#define ESIS1SEL1 (0x0100u) /* PPUS1 source select */\r
+#define ESIS1SEL0 (0x0080u) /* PPUS1 source select */\r
+#define ESITCH11 (0x0040u) /* select the comparator input for test channel 1 */\r
+#define ESITCH10 (0x0020u) /* select the comparator input for test channel 1 */\r
+#define ESITCH01 (0x0010u) /* select the comparator input for test channel 0 */\r
+#define ESITCH00 (0x0008u) /* select the comparator input for test channel 0 */\r
+#define ESICS (0x0004u) /* Comparator output/Timer_A input selection */\r
+#define ESITESTD (0x0002u) /* Test cycle insertion */\r
+#define ESIEN (0x0001u) /* Extended Scan interface enable */\r
+\r
+/* ESICTL Control Bits */\r
+#define ESIS1SEL0_L (0x0080u) /* PPUS1 source select */\r
+#define ESITCH11_L (0x0040u) /* select the comparator input for test channel 1 */\r
+#define ESITCH10_L (0x0020u) /* select the comparator input for test channel 1 */\r
+#define ESITCH01_L (0x0010u) /* select the comparator input for test channel 0 */\r
+#define ESITCH00_L (0x0008u) /* select the comparator input for test channel 0 */\r
+#define ESICS_L (0x0004u) /* Comparator output/Timer_A input selection */\r
+#define ESITESTD_L (0x0002u) /* Test cycle insertion */\r
+#define ESIEN_L (0x0001u) /* Extended Scan interface enable */\r
+\r
+/* ESICTL Control Bits */\r
+#define ESIS3SEL2_H (0x0080u) /* PPUS3 source select */\r
+#define ESIS3SEL1_H (0x0040u) /* PPUS3 source select */\r
+#define ESIS3SEL0_H (0x0020u) /* PPUS3 source select */\r
+#define ESIS2SEL2_H (0x0010u) /* PPUS2 source select */\r
+#define ESIS2SEL1_H (0x0008u) /* PPUS2 source select */\r
+#define ESIS2SEL0_H (0x0004u) /* PPUS2 source select */\r
+#define ESIS1SEL2_H (0x0002u) /* PPUS1 source select */\r
+#define ESIS1SEL1_H (0x0001u) /* PPUS1 source select */\r
+\r
+#define ESIS3SEL_0 (0x0000u) /* ESIOUT0 is the PPUS3 source */\r
+#define ESIS3SEL_1 (0x2000u) /* ESIOUT1 is the PPUS3 source */\r
+#define ESIS3SEL_2 (0x4000u) /* ESIOUT2 is the PPUS3 source */\r
+#define ESIS3SEL_3 (0x6000u) /* ESIOUT3 is the PPUS3 source */\r
+#define ESIS3SEL_4 (0x8000u) /* ESIOUT4 is the PPUS3 source */\r
+#define ESIS3SEL_5 (0xA000u) /* ESIOUT5 is the PPUS3 source */\r
+#define ESIS3SEL_6 (0xC000u) /* ESIOUT6 is the PPUS3 source */\r
+#define ESIS3SEL_7 (0xE000u) /* ESIOUT7 is the PPUS3 source */\r
+#define ESIS2SEL_0 (0x0000u) /* ESIOUT0 is the PPUS2 source */\r
+#define ESIS2SEL_1 (0x0400u) /* ESIOUT1 is the PPUS2 source */\r
+#define ESIS2SEL_2 (0x0800u) /* ESIOUT2 is the PPUS2 source */\r
+#define ESIS2SEL_3 (0x0C00u) /* ESIOUT3 is the PPUS2 source */\r
+#define ESIS2SEL_4 (0x1000u) /* ESIOUT4 is the PPUS2 source */\r
+#define ESIS2SEL_5 (0x1400u) /* ESIOUT5 is the PPUS2 source */\r
+#define ESIS2SEL_6 (0x1800u) /* ESIOUT6 is the PPUS2 source */\r
+#define ESIS2SEL_7 (0x1C00u) /* ESIOUT7 is the PPUS2 source */\r
+#define ESIS1SEL_0 (0x0000u) /* ESIOUT0 is the PPUS1 source */\r
+#define ESIS1SEL_1 (0x0080u) /* ESIOUT1 is the PPUS1 source */\r
+#define ESIS1SEL_2 (0x0100u) /* ESIOUT2 is the PPUS1 source */\r
+#define ESIS1SEL_3 (0x0180u) /* ESIOUT3 is the PPUS1 source */\r
+#define ESIS1SEL_4 (0x0200u) /* ESIOUT4 is the PPUS1 source */\r
+#define ESIS1SEL_5 (0x0280u) /* ESIOUT5 is the PPUS1 source */\r
+#define ESIS1SEL_6 (0x0300u) /* ESIOUT6 is the PPUS1 source */\r
+#define ESIS1SEL_7 (0x0380u) /* ESIOUT7 is the PPUS1 source */\r
+#define ESITCH1_0 (0x0000u) /* Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1 */\r
+#define ESITCH1_1 (0x0400u) /* Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1 */\r
+#define ESITCH1_2 (0x0800u) /* Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 */\r
+#define ESITCH1_3 (0x0C00u) /* Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 */\r
+#define ESITCH0_0 (0x0000u) /* Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1 */\r
+#define ESITCH0_1 (0x0008u) /* Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1 */\r
+#define ESITCH0_2 (0x0010u) /* Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 */\r
+#define ESITCH0_3 (0x0018u) /* Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 */\r
+\r
+/* Timing State Machine Control Bits */\r
+#define ESIREPEAT4 (0x8000u) /* These bits together with the ESICLK bit configure the duration of this state */\r
+#define ESIREPEAT3 (0x4000u) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */\r
+#define ESIREPEAT2 (0x2000u) /* */\r
+#define ESIREPEAT1 (0x1000u) /* */\r
+#define ESIREPEAT0 (0x0800u) /* */\r
+#define ESICLK (0x0400u) /* This bit selects the clock source for the TSM */\r
+#define ESISTOP (0x0200u) /* This bit indicates the end of the TSM sequence */\r
+#define ESIDAC (0x0100u) /* TSM DAC on */\r
+#define ESITESTS1 (0x0080u) /* TSM test cycle control */\r
+#define ESIRSON (0x0040u) /* Internal output latches enabled */\r
+#define ESICLKON (0x0020u) /* High-frequency clock on */\r
+#define ESICA (0x0010u) /* TSM comparator on */\r
+#define ESIEX (0x0008u) /* Excitation and sample-and-hold */\r
+#define ESILCEN (0x0004u) /* LC enable */\r
+#define ESICH1 (0x0002u) /* Input channel select */\r
+#define ESICH0 (0x0001u) /* Input channel select */\r
+\r
+/* Timing State Machine Control Bits */\r
+#define ESITESTS1_L (0x0080u) /* TSM test cycle control */\r
+#define ESIRSON_L (0x0040u) /* Internal output latches enabled */\r
+#define ESICLKON_L (0x0020u) /* High-frequency clock on */\r
+#define ESICA_L (0x0010u) /* TSM comparator on */\r
+#define ESIEX_L (0x0008u) /* Excitation and sample-and-hold */\r
+#define ESILCEN_L (0x0004u) /* LC enable */\r
+#define ESICH1_L (0x0002u) /* Input channel select */\r
+#define ESICH0_L (0x0001u) /* Input channel select */\r
+\r
+/* Timing State Machine Control Bits */\r
+#define ESIREPEAT4_H (0x0080u) /* These bits together with the ESICLK bit configure the duration of this state */\r
+#define ESIREPEAT3_H (0x0040u) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */\r
+#define ESIREPEAT2_H (0x0020u) /* */\r
+#define ESIREPEAT1_H (0x0010u) /* */\r
+#define ESIREPEAT0_H (0x0008u) /* */\r
+#define ESICLK_H (0x0004u) /* This bit selects the clock source for the TSM */\r
+#define ESISTOP_H (0x0002u) /* This bit indicates the end of the TSM sequence */\r
+#define ESIDAC_H (0x0001u) /* TSM DAC on */\r
+\r
+#define ESICAAZ (0x0020u) /* Comparator Offset calibration annulation */\r
+\r
+#define ESIREPEAT_0 (0x0000u) /* These bits configure the duration of this state */\r
+#define ESIREPEAT_1 (0x0800u) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */\r
+#define ESIREPEAT_2 (0x1000u)\r
+#define ESIREPEAT_3 (0x1800u)\r
+#define ESIREPEAT_4 (0x2000u)\r
+#define ESIREPEAT_5 (0x2800u)\r
+#define ESIREPEAT_6 (0x3000u)\r
+#define ESIREPEAT_7 (0x3800u)\r
+#define ESIREPEAT_8 (0x4000u)\r
+#define ESIREPEAT_9 (0x4800u)\r
+#define ESIREPEAT_10 (0x5000u)\r
+#define ESIREPEAT_11 (0x5800u)\r
+#define ESIREPEAT_12 (0x6000u)\r
+#define ESIREPEAT_13 (0x6800u)\r
+#define ESIREPEAT_14 (0x7000u)\r
+#define ESIREPEAT_15 (0x7800u)\r
+#define ESIREPEAT_16 (0x8000u)\r
+#define ESIREPEAT_17 (0x8800u)\r
+#define ESIREPEAT_18 (0x9000u)\r
+#define ESIREPEAT_19 (0x9800u)\r
+#define ESIREPEAT_20 (0xA000u)\r
+#define ESIREPEAT_21 (0xA800u)\r
+#define ESIREPEAT_22 (0xB000u)\r
+#define ESIREPEAT_23 (0xB800u)\r
+#define ESIREPEAT_24 (0xC000u)\r
+#define ESIREPEAT_25 (0xC800u)\r
+#define ESIREPEAT_26 (0xD000u)\r
+#define ESIREPEAT_27 (0xD800u)\r
+#define ESIREPEAT_28 (0xE000u)\r
+#define ESIREPEAT_29 (0xE800u)\r
+#define ESIREPEAT_30 (0xF000u)\r
+#define ESIREPEAT_31 (0xF800u)\r
+#define ESICH_0 (0x0000u) /* Input channel select: ESICH0 */\r
+#define ESICH_1 (0x0001u) /* Input channel select: ESICH1 */\r
+#define ESICH_2 (0x0002u) /* Input channel select: ESICH2 */\r
+#define ESICH_3 (0x0003u) /* Input channel select: ESICH3 */\r
+#endif\r
+/************************************************************\r
+* EXTENDED SCAN INTERFACE RAM\r
+************************************************************/\r
+#ifdef __MSP430_HAS_ESI_RAM__ /* Definition to show that Module is available */\r
+\r
+#define OFS_ESIRAM0 (0x0000u) /* ESI RAM 0 */\r
+#define OFS_ESIRAM1 (0x0001u) /* ESI RAM 1 */\r
+#define OFS_ESIRAM2 (0x0002u) /* ESI RAM 2 */\r
+#define OFS_ESIRAM3 (0x0003u) /* ESI RAM 3 */\r
+#define OFS_ESIRAM4 (0x0004u) /* ESI RAM 4 */\r
+#define OFS_ESIRAM5 (0x0005u) /* ESI RAM 5 */\r
+#define OFS_ESIRAM6 (0x0006u) /* ESI RAM 6 */\r
+#define OFS_ESIRAM7 (0x0007u) /* ESI RAM 7 */\r
+#define OFS_ESIRAM8 (0x0008u) /* ESI RAM 8 */\r
+#define OFS_ESIRAM9 (0x0009u) /* ESI RAM 9 */\r
+#define OFS_ESIRAM10 (0x000Au) /* ESI RAM 10 */\r
+#define OFS_ESIRAM11 (0x000Bu) /* ESI RAM 11 */\r
+#define OFS_ESIRAM12 (0x000Cu) /* ESI RAM 12 */\r
+#define OFS_ESIRAM13 (0x000Du) /* ESI RAM 13 */\r
+#define OFS_ESIRAM14 (0x000Eu) /* ESI RAM 14 */\r
+#define OFS_ESIRAM15 (0x000Fu) /* ESI RAM 15 */\r
+#define OFS_ESIRAM16 (0x0010u) /* ESI RAM 16 */\r
+#define OFS_ESIRAM17 (0x0011u) /* ESI RAM 17 */\r
+#define OFS_ESIRAM18 (0x0012u) /* ESI RAM 18 */\r
+#define OFS_ESIRAM19 (0x0013u) /* ESI RAM 19 */\r
+#define OFS_ESIRAM20 (0x0014u) /* ESI RAM 20 */\r
+#define OFS_ESIRAM21 (0x0015u) /* ESI RAM 21 */\r
+#define OFS_ESIRAM22 (0x0016u) /* ESI RAM 22 */\r
+#define OFS_ESIRAM23 (0x0017u) /* ESI RAM 23 */\r
+#define OFS_ESIRAM24 (0x0018u) /* ESI RAM 24 */\r
+#define OFS_ESIRAM25 (0x0019u) /* ESI RAM 25 */\r
+#define OFS_ESIRAM26 (0x001Au) /* ESI RAM 26 */\r
+#define OFS_ESIRAM27 (0x001Bu) /* ESI RAM 27 */\r
+#define OFS_ESIRAM28 (0x001Cu) /* ESI RAM 28 */\r
+#define OFS_ESIRAM29 (0x001Du) /* ESI RAM 29 */\r
+#define OFS_ESIRAM30 (0x001Eu) /* ESI RAM 30 */\r
+#define OFS_ESIRAM31 (0x001Fu) /* ESI RAM 31 */\r
+#define OFS_ESIRAM32 (0x0020u) /* ESI RAM 32 */\r
+#define OFS_ESIRAM33 (0x0021u) /* ESI RAM 33 */\r
+#define OFS_ESIRAM34 (0x0022u) /* ESI RAM 34 */\r
+#define OFS_ESIRAM35 (0x0023u) /* ESI RAM 35 */\r
+#define OFS_ESIRAM36 (0x0024u) /* ESI RAM 36 */\r
+#define OFS_ESIRAM37 (0x0025u) /* ESI RAM 37 */\r
+#define OFS_ESIRAM38 (0x0026u) /* ESI RAM 38 */\r
+#define OFS_ESIRAM39 (0x0027u) /* ESI RAM 39 */\r
+#define OFS_ESIRAM40 (0x0028u) /* ESI RAM 40 */\r
+#define OFS_ESIRAM41 (0x0029u) /* ESI RAM 41 */\r
+#define OFS_ESIRAM42 (0x002Au) /* ESI RAM 42 */\r
+#define OFS_ESIRAM43 (0x002Bu) /* ESI RAM 43 */\r
+#define OFS_ESIRAM44 (0x002Cu) /* ESI RAM 44 */\r
+#define OFS_ESIRAM45 (0x002Du) /* ESI RAM 45 */\r
+#define OFS_ESIRAM46 (0x002Eu) /* ESI RAM 46 */\r
+#define OFS_ESIRAM47 (0x002Fu) /* ESI RAM 47 */\r
+#define OFS_ESIRAM48 (0x0030u) /* ESI RAM 48 */\r
+#define OFS_ESIRAM49 (0x0031u) /* ESI RAM 49 */\r
+#define OFS_ESIRAM50 (0x0032u) /* ESI RAM 50 */\r
+#define OFS_ESIRAM51 (0x0033u) /* ESI RAM 51 */\r
+#define OFS_ESIRAM52 (0x0034u) /* ESI RAM 52 */\r
+#define OFS_ESIRAM53 (0x0035u) /* ESI RAM 53 */\r
+#define OFS_ESIRAM54 (0x0036u) /* ESI RAM 54 */\r
+#define OFS_ESIRAM55 (0x0037u) /* ESI RAM 55 */\r
+#define OFS_ESIRAM56 (0x0038u) /* ESI RAM 56 */\r
+#define OFS_ESIRAM57 (0x0039u) /* ESI RAM 57 */\r
+#define OFS_ESIRAM58 (0x003Au) /* ESI RAM 58 */\r
+#define OFS_ESIRAM59 (0x003Bu) /* ESI RAM 59 */\r
+#define OFS_ESIRAM60 (0x003Cu) /* ESI RAM 60 */\r
+#define OFS_ESIRAM61 (0x003Du) /* ESI RAM 61 */\r
+#define OFS_ESIRAM62 (0x003Eu) /* ESI RAM 62 */\r
+#define OFS_ESIRAM63 (0x003Fu) /* ESI RAM 63 */\r
+#define OFS_ESIRAM64 (0x0040u) /* ESI RAM 64 */\r
+#define OFS_ESIRAM65 (0x0041u) /* ESI RAM 65 */\r
+#define OFS_ESIRAM66 (0x0042u) /* ESI RAM 66 */\r
+#define OFS_ESIRAM67 (0x0043u) /* ESI RAM 67 */\r
+#define OFS_ESIRAM68 (0x0044u) /* ESI RAM 68 */\r
+#define OFS_ESIRAM69 (0x0045u) /* ESI RAM 69 */\r
+#define OFS_ESIRAM70 (0x0046u) /* ESI RAM 70 */\r
+#define OFS_ESIRAM71 (0x0047u) /* ESI RAM 71 */\r
+#define OFS_ESIRAM72 (0x0048u) /* ESI RAM 72 */\r
+#define OFS_ESIRAM73 (0x0049u) /* ESI RAM 73 */\r
+#define OFS_ESIRAM74 (0x004Au) /* ESI RAM 74 */\r
+#define OFS_ESIRAM75 (0x004Bu) /* ESI RAM 75 */\r
+#define OFS_ESIRAM76 (0x004Cu) /* ESI RAM 76 */\r
+#define OFS_ESIRAM77 (0x004Du) /* ESI RAM 77 */\r
+#define OFS_ESIRAM78 (0x004Eu) /* ESI RAM 78 */\r
+#define OFS_ESIRAM79 (0x004Fu) /* ESI RAM 79 */\r
+#define OFS_ESIRAM80 (0x0050u) /* ESI RAM 80 */\r
+#define OFS_ESIRAM81 (0x0051u) /* ESI RAM 81 */\r
+#define OFS_ESIRAM82 (0x0052u) /* ESI RAM 82 */\r
+#define OFS_ESIRAM83 (0x0053u) /* ESI RAM 83 */\r
+#define OFS_ESIRAM84 (0x0054u) /* ESI RAM 84 */\r
+#define OFS_ESIRAM85 (0x0055u) /* ESI RAM 85 */\r
+#define OFS_ESIRAM86 (0x0056u) /* ESI RAM 86 */\r
+#define OFS_ESIRAM87 (0x0057u) /* ESI RAM 87 */\r
+#define OFS_ESIRAM88 (0x0058u) /* ESI RAM 88 */\r
+#define OFS_ESIRAM89 (0x0059u) /* ESI RAM 89 */\r
+#define OFS_ESIRAM90 (0x005Au) /* ESI RAM 90 */\r
+#define OFS_ESIRAM91 (0x005Bu) /* ESI RAM 91 */\r
+#define OFS_ESIRAM92 (0x005Cu) /* ESI RAM 92 */\r
+#define OFS_ESIRAM93 (0x005Du) /* ESI RAM 93 */\r
+#define OFS_ESIRAM94 (0x005Eu) /* ESI RAM 94 */\r
+#define OFS_ESIRAM95 (0x005Fu) /* ESI RAM 95 */\r
+#define OFS_ESIRAM96 (0x0060u) /* ESI RAM 96 */\r
+#define OFS_ESIRAM97 (0x0061u) /* ESI RAM 97 */\r
+#define OFS_ESIRAM98 (0x0062u) /* ESI RAM 98 */\r
+#define OFS_ESIRAM99 (0x0063u) /* ESI RAM 99 */\r
+#define OFS_ESIRAM100 (0x0064u) /* ESI RAM 100 */\r
+#define OFS_ESIRAM101 (0x0065u) /* ESI RAM 101 */\r
+#define OFS_ESIRAM102 (0x0066u) /* ESI RAM 102 */\r
+#define OFS_ESIRAM103 (0x0067u) /* ESI RAM 103 */\r
+#define OFS_ESIRAM104 (0x0068u) /* ESI RAM 104 */\r
+#define OFS_ESIRAM105 (0x0069u) /* ESI RAM 105 */\r
+#define OFS_ESIRAM106 (0x006Au) /* ESI RAM 106 */\r
+#define OFS_ESIRAM107 (0x006Bu) /* ESI RAM 107 */\r
+#define OFS_ESIRAM108 (0x006Cu) /* ESI RAM 108 */\r
+#define OFS_ESIRAM109 (0x006Du) /* ESI RAM 109 */\r
+#define OFS_ESIRAM110 (0x006Eu) /* ESI RAM 110 */\r
+#define OFS_ESIRAM111 (0x006Fu) /* ESI RAM 111 */\r
+#define OFS_ESIRAM112 (0x0070u) /* ESI RAM 112 */\r
+#define OFS_ESIRAM113 (0x0071u) /* ESI RAM 113 */\r
+#define OFS_ESIRAM114 (0x0072u) /* ESI RAM 114 */\r
+#define OFS_ESIRAM115 (0x0073u) /* ESI RAM 115 */\r
+#define OFS_ESIRAM116 (0x0074u) /* ESI RAM 116 */\r
+#define OFS_ESIRAM117 (0x0075u) /* ESI RAM 117 */\r
+#define OFS_ESIRAM118 (0x0076u) /* ESI RAM 118 */\r
+#define OFS_ESIRAM119 (0x0077u) /* ESI RAM 119 */\r
+#define OFS_ESIRAM120 (0x0078u) /* ESI RAM 120 */\r
+#define OFS_ESIRAM121 (0x0079u) /* ESI RAM 121 */\r
+#define OFS_ESIRAM122 (0x007Au) /* ESI RAM 122 */\r
+#define OFS_ESIRAM123 (0x007Bu) /* ESI RAM 123 */\r
+#define OFS_ESIRAM124 (0x007Cu) /* ESI RAM 124 */\r
+#define OFS_ESIRAM125 (0x007Du) /* ESI RAM 125 */\r
+#define OFS_ESIRAM126 (0x007Eu) /* ESI RAM 126 */\r
+#define OFS_ESIRAM127 (0x007Fu) /* ESI RAM 127 */\r
+#endif\r
+/*************************************************************\r
+* FRAM Memory\r
+*************************************************************/\r
+#ifdef __MSP430_HAS_FRAM__ /* Definition to show that Module is available */\r
+\r
+#define OFS_FRCTL0 (0x0000u) /* FRAM Controller Control 0 */\r
+#define OFS_FRCTL0_L OFS_FRCTL0\r
+#define OFS_FRCTL0_H OFS_FRCTL0+1\r
+#define OFS_GCCTL0 (0x0004u) /* General Control 0 */\r
+#define OFS_GCCTL0_L OFS_GCCTL0\r
+#define OFS_GCCTL0_H OFS_GCCTL0+1\r
+#define OFS_GCCTL1 (0x0006u) /* General Control 1 */\r
+#define OFS_GCCTL1_L OFS_GCCTL1\r
+#define OFS_GCCTL1_H OFS_GCCTL1+1\r
+\r
+#define FRCTLPW (0xA500u) /* FRAM password for write */\r
+#define FRPW (0x9600u) /* FRAM password returned by read */\r
+#define FWPW (0xA500u) /* FRAM password for write */\r
+#define FXPW (0x3300u) /* for use with XOR instruction */\r
+\r
+/* FRCTL0 Control Bits */\r
+//#define RESERVED (0x0001u) /* RESERVED */\r
+//#define RESERVED (0x0002u) /* RESERVED */\r
+//#define RESERVED (0x0004u) /* RESERVED */\r
+#define NWAITS0 (0x0010u) /* FRAM Wait state control Bit: 0 */\r
+#define NWAITS1 (0x0020u) /* FRAM Wait state control Bit: 1 */\r
+#define NWAITS2 (0x0040u) /* FRAM Wait state control Bit: 2 */\r
+//#define RESERVED (0x0080u) /* RESERVED */\r
+\r
+/* FRCTL0 Control Bits */\r
+//#define RESERVED (0x0001u) /* RESERVED */\r
+//#define RESERVED (0x0002u) /* RESERVED */\r
+//#define RESERVED (0x0004u) /* RESERVED */\r
+#define NWAITS0_L (0x0010u) /* FRAM Wait state control Bit: 0 */\r
+#define NWAITS1_L (0x0020u) /* FRAM Wait state control Bit: 1 */\r
+#define NWAITS2_L (0x0040u) /* FRAM Wait state control Bit: 2 */\r
+//#define RESERVED (0x0080u) /* RESERVED */\r
+\r
+#define NWAITS_0 (0x0000u) /* FRAM Wait state control: 0 */\r
+#define NWAITS_1 (0x0010u) /* FRAM Wait state control: 1 */\r
+#define NWAITS_2 (0x0020u) /* FRAM Wait state control: 2 */\r
+#define NWAITS_3 (0x0030u) /* FRAM Wait state control: 3 */\r
+#define NWAITS_4 (0x0040u) /* FRAM Wait state control: 4 */\r
+#define NWAITS_5 (0x0050u) /* FRAM Wait state control: 5 */\r
+#define NWAITS_6 (0x0060u) /* FRAM Wait state control: 6 */\r
+#define NWAITS_7 (0x0070u) /* FRAM Wait state control: 7 */\r
+\r
+/* Legacy Defines */\r
+#define NAUTO (0x0008u) /* FRAM Disables the wait state generator (obsolete on Rev.E and later)*/\r
+#define NACCESS0 (0x0010u) /* FRAM Wait state Generator Access Time control Bit: 0 */\r
+#define NACCESS1 (0x0020u) /* FRAM Wait state Generator Access Time control Bit: 1 */\r
+#define NACCESS2 (0x0040u) /* FRAM Wait state Generator Access Time control Bit: 2 */\r
+#define NACCESS_0 (0x0000u) /* FRAM Wait state Generator Access Time control: 0 */\r
+#define NACCESS_1 (0x0010u) /* FRAM Wait state Generator Access Time control: 1 */\r
+#define NACCESS_2 (0x0020u) /* FRAM Wait state Generator Access Time control: 2 */\r
+#define NACCESS_3 (0x0030u) /* FRAM Wait state Generator Access Time control: 3 */\r
+#define NACCESS_4 (0x0040u) /* FRAM Wait state Generator Access Time control: 4 */\r
+#define NACCESS_5 (0x0050u) /* FRAM Wait state Generator Access Time control: 5 */\r
+#define NACCESS_6 (0x0060u) /* FRAM Wait state Generator Access Time control: 6 */\r
+#define NACCESS_7 (0x0070u) /* FRAM Wait state Generator Access Time control: 7 */\r
+\r
+/* GCCTL0 Control Bits */\r
+//#define RESERVED (0x0001u) /* RESERVED */\r
+#define FRLPMPWR (0x0002u) /* FRAM Enable FRAM auto power up after LPM */\r
+#define FRPWR (0x0004u) /* FRAM Power Control */\r
+#define ACCTEIE (0x0008u) /* Enable NMI event if Access time error occurs */\r
+//#define RESERVED (0x0010u) /* RESERVED */\r
+#define CBDIE (0x0020u) /* Enable NMI event if correctable bit error detected */\r
+#define UBDIE (0x0040u) /* Enable NMI event if uncorrectable bit error detected */\r
+#define UBDRSTEN (0x0080u) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */\r
+\r
+/* GCCTL0 Control Bits */\r
+//#define RESERVED (0x0001u) /* RESERVED */\r
+#define FRLPMPWR_L (0x0002u) /* FRAM Enable FRAM auto power up after LPM */\r
+#define FRPWR_L (0x0004u) /* FRAM Power Control */\r
+#define ACCTEIE_L (0x0008u) /* Enable NMI event if Access time error occurs */\r
+//#define RESERVED (0x0010u) /* RESERVED */\r
+#define CBDIE_L (0x0020u) /* Enable NMI event if correctable bit error detected */\r
+#define UBDIE_L (0x0040u) /* Enable NMI event if uncorrectable bit error detected */\r
+#define UBDRSTEN_L (0x0080u) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */\r
+\r
+/* GCCTL1 Control Bits */\r
+//#define RESERVED (0x0001u) /* RESERVED */\r
+#define CBDIFG (0x0002u) /* FRAM correctable bit error flag */\r
+#define UBDIFG (0x0004u) /* FRAM uncorrectable bit error flag */\r
+#define ACCTEIFG (0x0008u) /* Access time error flag */\r
+\r
+/* GCCTL1 Control Bits */\r
+//#define RESERVED (0x0001u) /* RESERVED */\r
+#define CBDIFG_L (0x0002u) /* FRAM correctable bit error flag */\r
+#define UBDIFG_L (0x0004u) /* FRAM uncorrectable bit error flag */\r
+#define ACCTEIFG_L (0x0008u) /* Access time error flag */\r
+\r
+#endif\r
+/************************************************************\r
+* LCD_C\r
+************************************************************/\r
+#ifdef __MSP430_HAS_LCD_C__ /* Definition to show that Module is available */\r
+\r
+#define OFS_LCDCCTL0 (0x0000u) /* LCD_C Control Register 0 */\r
+#define OFS_LCDCCTL0_L OFS_LCDCCTL0\r
+#define OFS_LCDCCTL0_H OFS_LCDCCTL0+1\r
+#define OFS_LCDCCTL1 (0x0002u) /* LCD_C Control Register 1 */\r
+#define OFS_LCDCCTL1_L OFS_LCDCCTL1\r
+#define OFS_LCDCCTL1_H OFS_LCDCCTL1+1\r
+#define OFS_LCDCBLKCTL (0x0004u) /* LCD_C blinking control register */\r
+#define OFS_LCDCBLKCTL_L OFS_LCDCBLKCTL\r
+#define OFS_LCDCBLKCTL_H OFS_LCDCBLKCTL+1\r
+#define OFS_LCDCMEMCTL (0x0006u) /* LCD_C memory control register */\r
+#define OFS_LCDCMEMCTL_L OFS_LCDCMEMCTL\r
+#define OFS_LCDCMEMCTL_H OFS_LCDCMEMCTL+1\r
+#define OFS_LCDCVCTL (0x0008u) /* LCD_C Voltage Control Register */\r
+#define OFS_LCDCVCTL_L OFS_LCDCVCTL\r
+#define OFS_LCDCVCTL_H OFS_LCDCVCTL+1\r
+#define OFS_LCDCPCTL0 (0x000Au) /* LCD_C Port Control Register 0 */\r
+#define OFS_LCDCPCTL0_L OFS_LCDCPCTL0\r
+#define OFS_LCDCPCTL0_H OFS_LCDCPCTL0+1\r
+#define OFS_LCDCPCTL1 (0x000Cu) /* LCD_C Port Control Register 1 */\r
+#define OFS_LCDCPCTL1_L OFS_LCDCPCTL1\r
+#define OFS_LCDCPCTL1_H OFS_LCDCPCTL1+1\r
+#define OFS_LCDCPCTL2 (0x000Eu) /* LCD_C Port Control Register 2 */\r
+#define OFS_LCDCPCTL2_L OFS_LCDCPCTL2\r
+#define OFS_LCDCPCTL2_H OFS_LCDCPCTL2+1\r
+#define OFS_LCDCPCTL3 (0x0010u) /* LCD_C Port Control Register 3 */\r
+#define OFS_LCDCPCTL3_L OFS_LCDCPCTL3\r
+#define OFS_LCDCPCTL3_H OFS_LCDCPCTL3+1\r
+#define OFS_LCDCCPCTL (0x0012u) /* LCD_C Charge Pump Control Register 3 */\r
+#define OFS_LCDCCPCTL_L OFS_LCDCCPCTL\r
+#define OFS_LCDCCPCTL_H OFS_LCDCCPCTL+1\r
+#define OFS_LCDCIV (0x001Eu) /* LCD_C Interrupt Vector Register */\r
+\r
+// LCDCCTL0\r
+#define LCDON (0x0001u) /* LCD_C LCD On */\r
+#define LCDLP (0x0002u) /* LCD_C Low Power Waveform */\r
+#define LCDSON (0x0004u) /* LCD_C LCD Segments On */\r
+#define LCDMX0 (0x0008u) /* LCD_C Mux Rate Bit: 0 */\r
+#define LCDMX1 (0x0010u) /* LCD_C Mux Rate Bit: 1 */\r
+#define LCDMX2 (0x0020u) /* LCD_C Mux Rate Bit: 2 */\r
+//#define RESERVED (0x0040u) /* LCD_C RESERVED */\r
+#define LCDSSEL (0x0080u) /* LCD_C Clock Select */\r
+#define LCDPRE0 (0x0100u) /* LCD_C LCD frequency pre-scaler Bit: 0 */\r
+#define LCDPRE1 (0x0200u) /* LCD_C LCD frequency pre-scaler Bit: 1 */\r
+#define LCDPRE2 (0x0400u) /* LCD_C LCD frequency pre-scaler Bit: 2 */\r
+#define LCDDIV0 (0x0800u) /* LCD_C LCD frequency divider Bit: 0 */\r
+#define LCDDIV1 (0x1000u) /* LCD_C LCD frequency divider Bit: 1 */\r
+#define LCDDIV2 (0x2000u) /* LCD_C LCD frequency divider Bit: 2 */\r
+#define LCDDIV3 (0x4000u) /* LCD_C LCD frequency divider Bit: 3 */\r
+#define LCDDIV4 (0x8000u) /* LCD_C LCD frequency divider Bit: 4 */\r
+\r
+// LCDCCTL0\r
+#define LCDON_L (0x0001u) /* LCD_C LCD On */\r
+#define LCDLP_L (0x0002u) /* LCD_C Low Power Waveform */\r
+#define LCDSON_L (0x0004u) /* LCD_C LCD Segments On */\r
+#define LCDMX0_L (0x0008u) /* LCD_C Mux Rate Bit: 0 */\r
+#define LCDMX1_L (0x0010u) /* LCD_C Mux Rate Bit: 1 */\r
+#define LCDMX2_L (0x0020u) /* LCD_C Mux Rate Bit: 2 */\r
+//#define RESERVED (0x0040u) /* LCD_C RESERVED */\r
+#define LCDSSEL_L (0x0080u) /* LCD_C Clock Select */\r
+\r
+// LCDCCTL0\r
+//#define RESERVED (0x0040u) /* LCD_C RESERVED */\r
+#define LCDPRE0_H (0x0001u) /* LCD_C LCD frequency pre-scaler Bit: 0 */\r
+#define LCDPRE1_H (0x0002u) /* LCD_C LCD frequency pre-scaler Bit: 1 */\r
+#define LCDPRE2_H (0x0004u) /* LCD_C LCD frequency pre-scaler Bit: 2 */\r
+#define LCDDIV0_H (0x0008u) /* LCD_C LCD frequency divider Bit: 0 */\r
+#define LCDDIV1_H (0x0010u) /* LCD_C LCD frequency divider Bit: 1 */\r
+#define LCDDIV2_H (0x0020u) /* LCD_C LCD frequency divider Bit: 2 */\r
+#define LCDDIV3_H (0x0040u) /* LCD_C LCD frequency divider Bit: 3 */\r
+#define LCDDIV4_H (0x0080u) /* LCD_C LCD frequency divider Bit: 4 */\r
+\r
+#define LCDPRE_0 (0x0000u) /* LCD_C LCD frequency pre-scaler: /1 */\r
+#define LCDPRE_1 (0x0100u) /* LCD_C LCD frequency pre-scaler: /2 */\r
+#define LCDPRE_2 (0x0200u) /* LCD_C LCD frequency pre-scaler: /4 */\r
+#define LCDPRE_3 (0x0300u) /* LCD_C LCD frequency pre-scaler: /8 */\r
+#define LCDPRE_4 (0x0400u) /* LCD_C LCD frequency pre-scaler: /16 */\r
+#define LCDPRE_5 (0x0500u) /* LCD_C LCD frequency pre-scaler: /32 */\r
+#define LCDPRE__1 (0x0000u) /* LCD_C LCD frequency pre-scaler: /1 */\r
+#define LCDPRE__2 (0x0100u) /* LCD_C LCD frequency pre-scaler: /2 */\r
+#define LCDPRE__4 (0x0200u) /* LCD_C LCD frequency pre-scaler: /4 */\r
+#define LCDPRE__8 (0x0300u) /* LCD_C LCD frequency pre-scaler: /8 */\r
+#define LCDPRE__16 (0x0400u) /* LCD_C LCD frequency pre-scaler: /16 */\r
+#define LCDPRE__32 (0x0500u) /* LCD_C LCD frequency pre-scaler: /32 */\r
+\r
+#define LCDDIV_0 (0x0000u) /* LCD_C LCD frequency divider: /1 */\r
+#define LCDDIV_1 (0x0800u) /* LCD_C LCD frequency divider: /2 */\r
+#define LCDDIV_2 (0x1000u) /* LCD_C LCD frequency divider: /3 */\r
+#define LCDDIV_3 (0x1800u) /* LCD_C LCD frequency divider: /4 */\r
+#define LCDDIV_4 (0x2000u) /* LCD_C LCD frequency divider: /5 */\r
+#define LCDDIV_5 (0x2800u) /* LCD_C LCD frequency divider: /6 */\r
+#define LCDDIV_6 (0x3000u) /* LCD_C LCD frequency divider: /7 */\r
+#define LCDDIV_7 (0x3800u) /* LCD_C LCD frequency divider: /8 */\r
+#define LCDDIV_8 (0x4000u) /* LCD_C LCD frequency divider: /9 */\r
+#define LCDDIV_9 (0x4800u) /* LCD_C LCD frequency divider: /10 */\r
+#define LCDDIV_10 (0x5000u) /* LCD_C LCD frequency divider: /11 */\r
+#define LCDDIV_11 (0x5800u) /* LCD_C LCD frequency divider: /12 */\r
+#define LCDDIV_12 (0x6000u) /* LCD_C LCD frequency divider: /13 */\r
+#define LCDDIV_13 (0x6800u) /* LCD_C LCD frequency divider: /14 */\r
+#define LCDDIV_14 (0x7000u) /* LCD_C LCD frequency divider: /15 */\r
+#define LCDDIV_15 (0x7800u) /* LCD_C LCD frequency divider: /16 */\r
+#define LCDDIV_16 (0x8000u) /* LCD_C LCD frequency divider: /17 */\r
+#define LCDDIV_17 (0x8800u) /* LCD_C LCD frequency divider: /18 */\r
+#define LCDDIV_18 (0x9000u) /* LCD_C LCD frequency divider: /19 */\r
+#define LCDDIV_19 (0x9800u) /* LCD_C LCD frequency divider: /20 */\r
+#define LCDDIV_20 (0xA000u) /* LCD_C LCD frequency divider: /21 */\r
+#define LCDDIV_21 (0xA800u) /* LCD_C LCD frequency divider: /22 */\r
+#define LCDDIV_22 (0xB000u) /* LCD_C LCD frequency divider: /23 */\r
+#define LCDDIV_23 (0xB800u) /* LCD_C LCD frequency divider: /24 */\r
+#define LCDDIV_24 (0xC000u) /* LCD_C LCD frequency divider: /25 */\r
+#define LCDDIV_25 (0xC800u) /* LCD_C LCD frequency divider: /26 */\r
+#define LCDDIV_26 (0xD000u) /* LCD_C LCD frequency divider: /27 */\r
+#define LCDDIV_27 (0xD800u) /* LCD_C LCD frequency divider: /28 */\r
+#define LCDDIV_28 (0xE000u) /* LCD_C LCD frequency divider: /29 */\r
+#define LCDDIV_29 (0xE800u) /* LCD_C LCD frequency divider: /30 */\r
+#define LCDDIV_30 (0xF000u) /* LCD_C LCD frequency divider: /31 */\r
+#define LCDDIV_31 (0xF800u) /* LCD_C LCD frequency divider: /32 */\r
+#define LCDDIV__1 (0x0000u) /* LCD_C LCD frequency divider: /1 */\r
+#define LCDDIV__2 (0x0800u) /* LCD_C LCD frequency divider: /2 */\r
+#define LCDDIV__3 (0x1000u) /* LCD_C LCD frequency divider: /3 */\r
+#define LCDDIV__4 (0x1800u) /* LCD_C LCD frequency divider: /4 */\r
+#define LCDDIV__5 (0x2000u) /* LCD_C LCD frequency divider: /5 */\r
+#define LCDDIV__6 (0x2800u) /* LCD_C LCD frequency divider: /6 */\r
+#define LCDDIV__7 (0x3000u) /* LCD_C LCD frequency divider: /7 */\r
+#define LCDDIV__8 (0x3800u) /* LCD_C LCD frequency divider: /8 */\r
+#define LCDDIV__9 (0x4000u) /* LCD_C LCD frequency divider: /9 */\r
+#define LCDDIV__10 (0x4800u) /* LCD_C LCD frequency divider: /10 */\r
+#define LCDDIV__11 (0x5000u) /* LCD_C LCD frequency divider: /11 */\r
+#define LCDDIV__12 (0x5800u) /* LCD_C LCD frequency divider: /12 */\r
+#define LCDDIV__13 (0x6000u) /* LCD_C LCD frequency divider: /13 */\r
+#define LCDDIV__14 (0x6800u) /* LCD_C LCD frequency divider: /14 */\r
+#define LCDDIV__15 (0x7000u) /* LCD_C LCD frequency divider: /15 */\r
+#define LCDDIV__16 (0x7800u) /* LCD_C LCD frequency divider: /16 */\r
+#define LCDDIV__17 (0x8000u) /* LCD_C LCD frequency divider: /17 */\r
+#define LCDDIV__18 (0x8800u) /* LCD_C LCD frequency divider: /18 */\r
+#define LCDDIV__19 (0x9000u) /* LCD_C LCD frequency divider: /19 */\r
+#define LCDDIV__20 (0x9800u) /* LCD_C LCD frequency divider: /20 */\r
+#define LCDDIV__21 (0xA000u) /* LCD_C LCD frequency divider: /21 */\r
+#define LCDDIV__22 (0xA800u) /* LCD_C LCD frequency divider: /22 */\r
+#define LCDDIV__23 (0xB000u) /* LCD_C LCD frequency divider: /23 */\r
+#define LCDDIV__24 (0xB800u) /* LCD_C LCD frequency divider: /24 */\r
+#define LCDDIV__25 (0xC000u) /* LCD_C LCD frequency divider: /25 */\r
+#define LCDDIV__26 (0xC800u) /* LCD_C LCD frequency divider: /26 */\r
+#define LCDDIV__27 (0xD000u) /* LCD_C LCD frequency divider: /27 */\r
+#define LCDDIV__28 (0xD800u) /* LCD_C LCD frequency divider: /28 */\r
+#define LCDDIV__29 (0xE000u) /* LCD_C LCD frequency divider: /29 */\r
+#define LCDDIV__30 (0xE800u) /* LCD_C LCD frequency divider: /30 */\r
+#define LCDDIV__31 (0xF000u) /* LCD_C LCD frequency divider: /31 */\r
+#define LCDDIV__32 (0xF800u) /* LCD_C LCD frequency divider: /32 */\r
+\r
+/* Display modes coded with Bits 2-4 */\r
+#define LCDSTATIC (LCDSON)\r
+#define LCD2MUX (LCDMX0+LCDSON)\r
+#define LCD3MUX (LCDMX1+LCDSON)\r
+#define LCD4MUX (LCDMX1+LCDMX0+LCDSON)\r
+#define LCD5MUX (LCDMX2+LCDSON)\r
+#define LCD6MUX (LCDMX2+LCDMX0+LCDSON)\r
+#define LCD7MUX (LCDMX2+LCDMX1+LCDSON)\r
+#define LCD8MUX (LCDMX2+LCDMX1+LCDMX0+LCDSON)\r
+\r
+// LCDCCTL1\r
+#define LCDFRMIFG (0x0001u) /* LCD_C LCD frame interrupt flag */\r
+#define LCDBLKOFFIFG (0x0002u) /* LCD_C LCD blinking off interrupt flag, */\r
+#define LCDBLKONIFG (0x0004u) /* LCD_C LCD blinking on interrupt flag, */\r
+#define LCDNOCAPIFG (0x0008u) /* LCD_C No cpacitance connected interrupt flag */\r
+#define LCDFRMIE (0x0100u) /* LCD_C LCD frame interrupt enable */\r
+#define LCDBLKOFFIE (0x0200u) /* LCD_C LCD blinking off interrupt flag, */\r
+#define LCDBLKONIE (0x0400u) /* LCD_C LCD blinking on interrupt flag, */\r
+#define LCDNOCAPIE (0x0800u) /* LCD_C No cpacitance connected interrupt enable */\r
+\r
+// LCDCCTL1\r
+#define LCDFRMIFG_L (0x0001u) /* LCD_C LCD frame interrupt flag */\r
+#define LCDBLKOFFIFG_L (0x0002u) /* LCD_C LCD blinking off interrupt flag, */\r
+#define LCDBLKONIFG_L (0x0004u) /* LCD_C LCD blinking on interrupt flag, */\r
+#define LCDNOCAPIFG_L (0x0008u) /* LCD_C No cpacitance connected interrupt flag */\r
+\r
+// LCDCCTL1\r
+#define LCDFRMIE_H (0x0001u) /* LCD_C LCD frame interrupt enable */\r
+#define LCDBLKOFFIE_H (0x0002u) /* LCD_C LCD blinking off interrupt flag, */\r
+#define LCDBLKONIE_H (0x0004u) /* LCD_C LCD blinking on interrupt flag, */\r
+#define LCDNOCAPIE_H (0x0008u) /* LCD_C No cpacitance connected interrupt enable */\r
+\r
+// LCDCBLKCTL\r
+#define LCDBLKMOD0 (0x0001u) /* LCD_C Blinking mode Bit: 0 */\r
+#define LCDBLKMOD1 (0x0002u) /* LCD_C Blinking mode Bit: 1 */\r
+#define LCDBLKPRE0 (0x0004u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */\r
+#define LCDBLKPRE1 (0x0008u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */\r
+#define LCDBLKPRE2 (0x0010u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */\r
+#define LCDBLKDIV0 (0x0020u) /* LCD_C Clock divider for blinking frequency Bit: 0 */\r
+#define LCDBLKDIV1 (0x0040u) /* LCD_C Clock divider for blinking frequency Bit: 1 */\r
+#define LCDBLKDIV2 (0x0080u) /* LCD_C Clock divider for blinking frequency Bit: 2 */\r
+\r
+// LCDCBLKCTL\r
+#define LCDBLKMOD0_L (0x0001u) /* LCD_C Blinking mode Bit: 0 */\r
+#define LCDBLKMOD1_L (0x0002u) /* LCD_C Blinking mode Bit: 1 */\r
+#define LCDBLKPRE0_L (0x0004u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */\r
+#define LCDBLKPRE1_L (0x0008u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */\r
+#define LCDBLKPRE2_L (0x0010u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */\r
+#define LCDBLKDIV0_L (0x0020u) /* LCD_C Clock divider for blinking frequency Bit: 0 */\r
+#define LCDBLKDIV1_L (0x0040u) /* LCD_C Clock divider for blinking frequency Bit: 1 */\r
+#define LCDBLKDIV2_L (0x0080u) /* LCD_C Clock divider for blinking frequency Bit: 2 */\r
+\r
+#define LCDBLKMOD_0 (0x0000u) /* LCD_C Blinking mode: Off */\r
+#define LCDBLKMOD_1 (0x0001u) /* LCD_C Blinking mode: Individual */\r
+#define LCDBLKMOD_2 (0x0002u) /* LCD_C Blinking mode: All */\r
+#define LCDBLKMOD_3 (0x0003u) /* LCD_C Blinking mode: Switching */\r
+\r
+// LCDCMEMCTL\r
+#define LCDDISP (0x0001u) /* LCD_C LCD memory registers for display */\r
+#define LCDCLRM (0x0002u) /* LCD_C Clear LCD memory */\r
+#define LCDCLRBM (0x0004u) /* LCD_C Clear LCD blinking memory */\r
+\r
+// LCDCMEMCTL\r
+#define LCDDISP_L (0x0001u) /* LCD_C LCD memory registers for display */\r
+#define LCDCLRM_L (0x0002u) /* LCD_C Clear LCD memory */\r
+#define LCDCLRBM_L (0x0004u) /* LCD_C Clear LCD blinking memory */\r
+\r
+// LCDCVCTL\r
+#define LCD2B (0x0001u) /* Selects 1/2 bias. */\r
+#define VLCDREF0 (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */\r
+#define VLCDREF1 (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */\r
+#define LCDCPEN (0x0008u) /* LCD Voltage Charge Pump Enable. */\r
+#define VLCDEXT (0x0010u) /* Select external source for VLCD. */\r
+#define LCDEXTBIAS (0x0020u) /* V2 - V4 voltage select. */\r
+#define R03EXT (0x0040u) /* Selects external connections for LCD mid voltages. */\r
+#define LCDREXT (0x0080u) /* Selects external connection for lowest LCD voltage. */\r
+#define VLCD0 (0x0200u) /* VLCD select: 0 */\r
+#define VLCD1 (0x0400u) /* VLCD select: 1 */\r
+#define VLCD2 (0x0800u) /* VLCD select: 2 */\r
+#define VLCD3 (0x1000u) /* VLCD select: 3 */\r
+#define VLCD4 (0x2000u) /* VLCD select: 4 */\r
+#define VLCD5 (0x4000u) /* VLCD select: 5 */\r
+\r
+// LCDCVCTL\r
+#define LCD2B_L (0x0001u) /* Selects 1/2 bias. */\r
+#define VLCDREF0_L (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */\r
+#define VLCDREF1_L (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */\r
+#define LCDCPEN_L (0x0008u) /* LCD Voltage Charge Pump Enable. */\r
+#define VLCDEXT_L (0x0010u) /* Select external source for VLCD. */\r
+#define LCDEXTBIAS_L (0x0020u) /* V2 - V4 voltage select. */\r
+#define R03EXT_L (0x0040u) /* Selects external connections for LCD mid voltages. */\r
+#define LCDREXT_L (0x0080u) /* Selects external connection for lowest LCD voltage. */\r
+\r
+// LCDCVCTL\r
+#define VLCD0_H (0x0002u) /* VLCD select: 0 */\r
+#define VLCD1_H (0x0004u) /* VLCD select: 1 */\r
+#define VLCD2_H (0x0008u) /* VLCD select: 2 */\r
+#define VLCD3_H (0x0010u) /* VLCD select: 3 */\r
+#define VLCD4_H (0x0020u) /* VLCD select: 4 */\r
+#define VLCD5_H (0x0040u) /* VLCD select: 5 */\r
+\r
+/* Reference voltage source select for the regulated charge pump */\r
+#define VLCDREF_0 (0x0000u) /* Internal */\r
+#define VLCDREF_1 (0x0002u) /* External */\r
+#define VLCDREF_2 (0x0004u) /* Reserved */\r
+#define VLCDREF_3 (0x0006u) /* Reserved */\r
+\r
+/* Charge pump voltage selections */\r
+#define VLCD_0 (0x0000u) /* Charge pump disabled */\r
+#define VLCD_1 (0x0200u) /* VLCD = 2.60V */\r
+#define VLCD_2 (0x0400u) /* VLCD = 2.66V */\r
+#define VLCD_3 (0x0600u) /* VLCD = 2.72V */\r
+#define VLCD_4 (0x0800u) /* VLCD = 2.78V */\r
+#define VLCD_5 (0x0A00u) /* VLCD = 2.84V */\r
+#define VLCD_6 (0x0C00u) /* VLCD = 2.90V */\r
+#define VLCD_7 (0x0E00u) /* VLCD = 2.96V */\r
+#define VLCD_8 (0x1000u) /* VLCD = 3.02V */\r
+#define VLCD_9 (0x1200u) /* VLCD = 3.08V */\r
+#define VLCD_10 (0x1400u) /* VLCD = 3.14V */\r
+#define VLCD_11 (0x1600u) /* VLCD = 3.20V */\r
+#define VLCD_12 (0x1800u) /* VLCD = 3.26V */\r
+#define VLCD_13 (0x1A00u) /* VLCD = 3.32V */\r
+#define VLCD_14 (0x1C00u) /* VLCD = 3.38V */\r
+#define VLCD_15 (0x1E00u) /* VLCD = 3.44V */\r
+\r
+#define VLCD_DISABLED (0x0000u) /* Charge pump disabled */\r
+#define VLCD_2_60 (0x0200u) /* VLCD = 2.60V */\r
+#define VLCD_2_66 (0x0400u) /* VLCD = 2.66V */\r
+#define VLCD_2_72 (0x0600u) /* VLCD = 2.72V */\r
+#define VLCD_2_78 (0x0800u) /* VLCD = 2.78V */\r
+#define VLCD_2_84 (0x0A00u) /* VLCD = 2.84V */\r
+#define VLCD_2_90 (0x0C00u) /* VLCD = 2.90V */\r
+#define VLCD_2_96 (0x0E00u) /* VLCD = 2.96V */\r
+#define VLCD_3_02 (0x1000u) /* VLCD = 3.02V */\r
+#define VLCD_3_08 (0x1200u) /* VLCD = 3.08V */\r
+#define VLCD_3_14 (0x1400u) /* VLCD = 3.14V */\r
+#define VLCD_3_20 (0x1600u) /* VLCD = 3.20V */\r
+#define VLCD_3_26 (0x1800u) /* VLCD = 3.26V */\r
+#define VLCD_3_32 (0x1A00u) /* VLCD = 3.32V */\r
+#define VLCD_3_38 (0x1C00u) /* VLCD = 3.38V */\r
+#define VLCD_3_44 (0x1E00u) /* VLCD = 3.44V */\r
+\r
+// LCDCPCTL0\r
+#define LCDS0 (0x0001u) /* LCD Segment 0 enable. */\r
+#define LCDS1 (0x0002u) /* LCD Segment 1 enable. */\r
+#define LCDS2 (0x0004u) /* LCD Segment 2 enable. */\r
+#define LCDS3 (0x0008u) /* LCD Segment 3 enable. */\r
+#define LCDS4 (0x0010u) /* LCD Segment 4 enable. */\r
+#define LCDS5 (0x0020u) /* LCD Segment 5 enable. */\r
+#define LCDS6 (0x0040u) /* LCD Segment 6 enable. */\r
+#define LCDS7 (0x0080u) /* LCD Segment 7 enable. */\r
+#define LCDS8 (0x0100u) /* LCD Segment 8 enable. */\r
+#define LCDS9 (0x0200u) /* LCD Segment 9 enable. */\r
+#define LCDS10 (0x0400u) /* LCD Segment 10 enable. */\r
+#define LCDS11 (0x0800u) /* LCD Segment 11 enable. */\r
+#define LCDS12 (0x1000u) /* LCD Segment 12 enable. */\r
+#define LCDS13 (0x2000u) /* LCD Segment 13 enable. */\r
+#define LCDS14 (0x4000u) /* LCD Segment 14 enable. */\r
+#define LCDS15 (0x8000u) /* LCD Segment 15 enable. */\r
+\r
+// LCDCPCTL0\r
+#define LCDS0_L (0x0001u) /* LCD Segment 0 enable. */\r
+#define LCDS1_L (0x0002u) /* LCD Segment 1 enable. */\r
+#define LCDS2_L (0x0004u) /* LCD Segment 2 enable. */\r
+#define LCDS3_L (0x0008u) /* LCD Segment 3 enable. */\r
+#define LCDS4_L (0x0010u) /* LCD Segment 4 enable. */\r
+#define LCDS5_L (0x0020u) /* LCD Segment 5 enable. */\r
+#define LCDS6_L (0x0040u) /* LCD Segment 6 enable. */\r
+#define LCDS7_L (0x0080u) /* LCD Segment 7 enable. */\r
+\r
+// LCDCPCTL0\r
+#define LCDS8_H (0x0001u) /* LCD Segment 8 enable. */\r
+#define LCDS9_H (0x0002u) /* LCD Segment 9 enable. */\r
+#define LCDS10_H (0x0004u) /* LCD Segment 10 enable. */\r
+#define LCDS11_H (0x0008u) /* LCD Segment 11 enable. */\r
+#define LCDS12_H (0x0010u) /* LCD Segment 12 enable. */\r
+#define LCDS13_H (0x0020u) /* LCD Segment 13 enable. */\r
+#define LCDS14_H (0x0040u) /* LCD Segment 14 enable. */\r
+#define LCDS15_H (0x0080u) /* LCD Segment 15 enable. */\r
+\r
+// LCDCPCTL1\r
+#define LCDS16 (0x0001u) /* LCD Segment 16 enable. */\r
+#define LCDS17 (0x0002u) /* LCD Segment 17 enable. */\r
+#define LCDS18 (0x0004u) /* LCD Segment 18 enable. */\r
+#define LCDS19 (0x0008u) /* LCD Segment 19 enable. */\r
+#define LCDS20 (0x0010u) /* LCD Segment 20 enable. */\r
+#define LCDS21 (0x0020u) /* LCD Segment 21 enable. */\r
+#define LCDS22 (0x0040u) /* LCD Segment 22 enable. */\r
+#define LCDS23 (0x0080u) /* LCD Segment 23 enable. */\r
+#define LCDS24 (0x0100u) /* LCD Segment 24 enable. */\r
+#define LCDS25 (0x0200u) /* LCD Segment 25 enable. */\r
+#define LCDS26 (0x0400u) /* LCD Segment 26 enable. */\r
+#define LCDS27 (0x0800u) /* LCD Segment 27 enable. */\r
+#define LCDS28 (0x1000u) /* LCD Segment 28 enable. */\r
+#define LCDS29 (0x2000u) /* LCD Segment 29 enable. */\r
+#define LCDS30 (0x4000u) /* LCD Segment 30 enable. */\r
+#define LCDS31 (0x8000u) /* LCD Segment 31 enable. */\r
+\r
+// LCDCPCTL1\r
+#define LCDS16_L (0x0001u) /* LCD Segment 16 enable. */\r
+#define LCDS17_L (0x0002u) /* LCD Segment 17 enable. */\r
+#define LCDS18_L (0x0004u) /* LCD Segment 18 enable. */\r
+#define LCDS19_L (0x0008u) /* LCD Segment 19 enable. */\r
+#define LCDS20_L (0x0010u) /* LCD Segment 20 enable. */\r
+#define LCDS21_L (0x0020u) /* LCD Segment 21 enable. */\r
+#define LCDS22_L (0x0040u) /* LCD Segment 22 enable. */\r
+#define LCDS23_L (0x0080u) /* LCD Segment 23 enable. */\r
+\r
+// LCDCPCTL1\r
+#define LCDS24_H (0x0001u) /* LCD Segment 24 enable. */\r
+#define LCDS25_H (0x0002u) /* LCD Segment 25 enable. */\r
+#define LCDS26_H (0x0004u) /* LCD Segment 26 enable. */\r
+#define LCDS27_H (0x0008u) /* LCD Segment 27 enable. */\r
+#define LCDS28_H (0x0010u) /* LCD Segment 28 enable. */\r
+#define LCDS29_H (0x0020u) /* LCD Segment 29 enable. */\r
+#define LCDS30_H (0x0040u) /* LCD Segment 30 enable. */\r
+#define LCDS31_H (0x0080u) /* LCD Segment 31 enable. */\r
+\r
+// LCDCPCTL2\r
+#define LCDS32 (0x0001u) /* LCD Segment 32 enable. */\r
+#define LCDS33 (0x0002u) /* LCD Segment 33 enable. */\r
+#define LCDS34 (0x0004u) /* LCD Segment 34 enable. */\r
+#define LCDS35 (0x0008u) /* LCD Segment 35 enable. */\r
+#define LCDS36 (0x0010u) /* LCD Segment 36 enable. */\r
+#define LCDS37 (0x0020u) /* LCD Segment 37 enable. */\r
+#define LCDS38 (0x0040u) /* LCD Segment 38 enable. */\r
+#define LCDS39 (0x0080u) /* LCD Segment 39 enable. */\r
+#define LCDS40 (0x0100u) /* LCD Segment 40 enable. */\r
+#define LCDS41 (0x0200u) /* LCD Segment 41 enable. */\r
+#define LCDS42 (0x0400u) /* LCD Segment 42 enable. */\r
+#define LCDS43 (0x0800u) /* LCD Segment 43 enable. */\r
+#define LCDS44 (0x1000u) /* LCD Segment 44 enable. */\r
+#define LCDS45 (0x2000u) /* LCD Segment 45 enable. */\r
+#define LCDS46 (0x4000u) /* LCD Segment 46 enable. */\r
+#define LCDS47 (0x8000u) /* LCD Segment 47 enable. */\r
+\r
+// LCDCPCTL2\r
+#define LCDS32_L (0x0001u) /* LCD Segment 32 enable. */\r
+#define LCDS33_L (0x0002u) /* LCD Segment 33 enable. */\r
+#define LCDS34_L (0x0004u) /* LCD Segment 34 enable. */\r
+#define LCDS35_L (0x0008u) /* LCD Segment 35 enable. */\r
+#define LCDS36_L (0x0010u) /* LCD Segment 36 enable. */\r
+#define LCDS37_L (0x0020u) /* LCD Segment 37 enable. */\r
+#define LCDS38_L (0x0040u) /* LCD Segment 38 enable. */\r
+#define LCDS39_L (0x0080u) /* LCD Segment 39 enable. */\r
+\r
+// LCDCPCTL2\r
+#define LCDS40_H (0x0001u) /* LCD Segment 40 enable. */\r
+#define LCDS41_H (0x0002u) /* LCD Segment 41 enable. */\r
+#define LCDS42_H (0x0004u) /* LCD Segment 42 enable. */\r
+#define LCDS43_H (0x0008u) /* LCD Segment 43 enable. */\r
+#define LCDS44_H (0x0010u) /* LCD Segment 44 enable. */\r
+#define LCDS45_H (0x0020u) /* LCD Segment 45 enable. */\r
+#define LCDS46_H (0x0040u) /* LCD Segment 46 enable. */\r
+#define LCDS47_H (0x0080u) /* LCD Segment 47 enable. */\r
+\r
+// LCDCPCTL3\r
+#define LCDS48 (0x0001u) /* LCD Segment 48 enable. */\r
+#define LCDS49 (0x0002u) /* LCD Segment 49 enable. */\r
+#define LCDS50 (0x0004u) /* LCD Segment 50 enable. */\r
+#define LCDS51 (0x0008u) /* LCD Segment 51 enable. */\r
+#define LCDS52 (0x0010u) /* LCD Segment 52 enable. */\r
+#define LCDS53 (0x0020u) /* LCD Segment 53 enable. */\r
+\r
+// LCDCPCTL3\r
+#define LCDS48_L (0x0001u) /* LCD Segment 48 enable. */\r
+#define LCDS49_L (0x0002u) /* LCD Segment 49 enable. */\r
+#define LCDS50_L (0x0004u) /* LCD Segment 50 enable. */\r
+#define LCDS51_L (0x0008u) /* LCD Segment 51 enable. */\r
+#define LCDS52_L (0x0010u) /* LCD Segment 52 enable. */\r
+#define LCDS53_L (0x0020u) /* LCD Segment 53 enable. */\r
+\r
+// LCDCCPCTL\r
+#define LCDCPDIS0 (0x0001u) /* LCD charge pump disable */\r
+#define LCDCPDIS1 (0x0002u) /* LCD charge pump disable */\r
+#define LCDCPDIS2 (0x0004u) /* LCD charge pump disable */\r
+#define LCDCPDIS3 (0x0008u) /* LCD charge pump disable */\r
+#define LCDCPDIS4 (0x0010u) /* LCD charge pump disable */\r
+#define LCDCPDIS5 (0x0020u) /* LCD charge pump disable */\r
+#define LCDCPDIS6 (0x0040u) /* LCD charge pump disable */\r
+#define LCDCPDIS7 (0x0080u) /* LCD charge pump disable */\r
+#define LCDCPCLKSYNC (0x8000u) /* LCD charge pump clock synchronization */\r
+\r
+// LCDCCPCTL\r
+#define LCDCPDIS0_L (0x0001u) /* LCD charge pump disable */\r
+#define LCDCPDIS1_L (0x0002u) /* LCD charge pump disable */\r
+#define LCDCPDIS2_L (0x0004u) /* LCD charge pump disable */\r
+#define LCDCPDIS3_L (0x0008u) /* LCD charge pump disable */\r
+#define LCDCPDIS4_L (0x0010u) /* LCD charge pump disable */\r
+#define LCDCPDIS5_L (0x0020u) /* LCD charge pump disable */\r
+#define LCDCPDIS6_L (0x0040u) /* LCD charge pump disable */\r
+#define LCDCPDIS7_L (0x0080u) /* LCD charge pump disable */\r
+\r
+// LCDCCPCTL\r
+#define LCDCPCLKSYNC_H (0x0080u) /* LCD charge pump clock synchronization */\r
+\r
+#define OFS_LCDM1 (0x0020u) /* LCD Memory 1 */\r
+#define LCDMEM_ LCDM1 /* LCD Memory */\r
+#ifndef __IAR_SYSTEMS_ICC__\r
+#define LCDMEM LCDM1 /* LCD Memory (for assembler) */\r
+#else\r
+#define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */\r
+#endif\r
+#define OFS_LCDM2 (0x0021u) /* LCD Memory 2 */\r
+#define OFS_LCDM3 (0x0022u) /* LCD Memory 3 */\r
+#define OFS_LCDM4 (0x0023u) /* LCD Memory 4 */\r
+#define OFS_LCDM5 (0x0024u) /* LCD Memory 5 */\r
+#define OFS_LCDM6 (0x0025u) /* LCD Memory 6 */\r
+#define OFS_LCDM7 (0x0026u) /* LCD Memory 7 */\r
+#define OFS_LCDM8 (0x0027u) /* LCD Memory 8 */\r
+#define OFS_LCDM9 (0x0028u) /* LCD Memory 9 */\r
+#define OFS_LCDM10 (0x0029u) /* LCD Memory 10 */\r
+#define OFS_LCDM11 (0x002Au) /* LCD Memory 11 */\r
+#define OFS_LCDM12 (0x002Bu) /* LCD Memory 12 */\r
+#define OFS_LCDM13 (0x002Cu) /* LCD Memory 13 */\r
+#define OFS_LCDM14 (0x002Du) /* LCD Memory 14 */\r
+#define OFS_LCDM15 (0x002Eu) /* LCD Memory 15 */\r
+#define OFS_LCDM16 (0x002Fu) /* LCD Memory 16 */\r
+#define OFS_LCDM17 (0x0030u) /* LCD Memory 17 */\r
+#define OFS_LCDM18 (0x0031u) /* LCD Memory 18 */\r
+#define OFS_LCDM19 (0x0032u) /* LCD Memory 19 */\r
+#define OFS_LCDM20 (0x0033u) /* LCD Memory 20 */\r
+#define OFS_LCDM21 (0x0034u) /* LCD Memory 21 */\r
+#define OFS_LCDM22 (0x0035u) /* LCD Memory 22 */\r
+#define OFS_LCDM23 (0x0036u) /* LCD Memory 23 */\r
+#define OFS_LCDM24 (0x0037u) /* LCD Memory 24 */\r
+#define OFS_LCDM25 (0x0038u) /* LCD Memory 25 */\r
+#define OFS_LCDM26 (0x0039u) /* LCD Memory 26 */\r
+#define OFS_LCDM27 (0x003Au) /* LCD Memory 27 */\r
+#define OFS_LCDM28 (0x003Bu) /* LCD Memory 28 */\r
+#define OFS_LCDM29 (0x003Cu) /* LCD Memory 29 */\r
+#define OFS_LCDM30 (0x003Du) /* LCD Memory 30 */\r
+#define OFS_LCDM31 (0x003Eu) /* LCD Memory 31 */\r
+#define OFS_LCDM32 (0x003Fu) /* LCD Memory 32 */\r
+#define OFS_LCDM33 (0x0040u) /* LCD Memory 33 */\r
+#define OFS_LCDM34 (0x0041u) /* LCD Memory 34 */\r
+#define OFS_LCDM35 (0x0042u) /* LCD Memory 35 */\r
+#define OFS_LCDM36 (0x0043u) /* LCD Memory 36 */\r
+#define OFS_LCDM37 (0x0044u) /* LCD Memory 37 */\r
+#define OFS_LCDM38 (0x0045u) /* LCD Memory 38 */\r
+#define OFS_LCDM39 (0x0046u) /* LCD Memory 39 */\r
+#define OFS_LCDM40 (0x0047u) /* LCD Memory 40 */\r
+\r
+#define OFS_LCDBM1 (0x0040u) /* LCD Blinking Memory 1 */\r
+#define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */\r
+#ifndef __IAR_SYSTEMS_ICC__\r
+#define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */\r
+#else\r
+#define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */\r
+#endif\r
+#define OFS_LCDBM2 (0x0041u) /* LCD Blinking Memory 2 */\r
+#define OFS_LCDBM3 (0x0042u) /* LCD Blinking Memory 3 */\r
+#define OFS_LCDBM4 (0x0043u) /* LCD Blinking Memory 4 */\r
+#define OFS_LCDBM5 (0x0044u) /* LCD Blinking Memory 5 */\r
+#define OFS_LCDBM6 (0x0045u) /* LCD Blinking Memory 6 */\r
+#define OFS_LCDBM7 (0x0046u) /* LCD Blinking Memory 7 */\r
+#define OFS_LCDBM8 (0x0047u) /* LCD Blinking Memory 8 */\r
+#define OFS_LCDBM9 (0x0048u) /* LCD Blinking Memory 9 */\r
+#define OFS_LCDBM10 (0x0049u) /* LCD Blinking Memory 10 */\r
+#define OFS_LCDBM11 (0x004Au) /* LCD Blinking Memory 11 */\r
+#define OFS_LCDBM12 (0x004Bu) /* LCD Blinking Memory 12 */\r
+#define OFS_LCDBM13 (0x004Cu) /* LCD Blinking Memory 13 */\r
+#define OFS_LCDBM14 (0x004Du) /* LCD Blinking Memory 14 */\r
+#define OFS_LCDBM15 (0x004Eu) /* LCD Blinking Memory 15 */\r
+#define OFS_LCDBM16 (0x004Fu) /* LCD Blinking Memory 16 */\r
+#define OFS_LCDBM17 (0x0050u) /* LCD Blinking Memory 17 */\r
+#define OFS_LCDBM18 (0x0051u) /* LCD Blinking Memory 18 */\r
+#define OFS_LCDBM19 (0x0052u) /* LCD Blinking Memory 19 */\r
+#define OFS_LCDBM20 (0x0053u) /* LCD Blinking Memory 20 */\r
+\r
+/* LCDCIV Definitions */\r
+#define LCDCIV_NONE (0x0000u) /* No Interrupt pending */\r
+#define LCDCIV_LCDNOCAPIFG (0x0002u) /* No capacitor connected */\r
+#define LCDCIV_LCDCLKOFFIFG (0x0004u) /* Blink, segments off */\r
+#define LCDCIV_LCDCLKONIFG (0x0006u) /* Blink, segments on */\r
+#define LCDCIV_LCDFRMIFG (0x0008u) /* Frame interrupt */\r
+\r
+#endif\r
+/************************************************************\r
+* Memory Protection Unit\r
+************************************************************/\r
+#ifdef __MSP430_HAS_MPU__ /* Definition to show that Module is available */\r
+\r
+#define OFS_MPUCTL0 (0x0000u) /* MPU Control Register 0 */\r
+#define OFS_MPUCTL0_L OFS_MPUCTL0\r
+#define OFS_MPUCTL0_H OFS_MPUCTL0+1\r
+#define OFS_MPUCTL1 (0x0002u) /* MPU Control Register 1 */\r
+#define OFS_MPUCTL1_L OFS_MPUCTL1\r
+#define OFS_MPUCTL1_H OFS_MPUCTL1+1\r
+#define OFS_MPUSEGB2 (0x0004u) /* MPU Segmentation Border 2 Register */\r
+#define OFS_MPUSEGB2_L OFS_MPUSEGB2\r
+#define OFS_MPUSEGB2_H OFS_MPUSEGB2+1\r
+#define OFS_MPUSEGB1 (0x0006u) /* MPU Segmentation Border 1 Register */\r
+#define OFS_MPUSEGB1_L OFS_MPUSEGB1\r
+#define OFS_MPUSEGB1_H OFS_MPUSEGB1+1\r
+#define OFS_MPUSAM (0x0008u) /* MPU Access Management Register */\r
+#define OFS_MPUSAM_L OFS_MPUSAM\r
+#define OFS_MPUSAM_H OFS_MPUSAM+1\r
+#define OFS_MPUIPC0 (0x000Au) /* MPU IP Control 0 Register */\r
+#define OFS_MPUIPC0_L OFS_MPUIPC0\r
+#define OFS_MPUIPC0_H OFS_MPUIPC0+1\r
+#define OFS_MPUIPSEGB2 (0x000Cu) /* MPU IP Segment Border 2 Register */\r
+#define OFS_MPUIPSEGB2_L OFS_MPUIPSEGB2\r
+#define OFS_MPUIPSEGB2_H OFS_MPUIPSEGB2+1\r
+#define OFS_MPUIPSEGB1 (0x000Eu) /* MPU IP Segment Border 1 Register */\r
+#define OFS_MPUIPSEGB1_L OFS_MPUIPSEGB1\r
+#define OFS_MPUIPSEGB1_H OFS_MPUIPSEGB1+1\r
+\r
+/* MPUCTL0 Control Bits */\r
+#define MPUENA (0x0001u) /* MPU Enable */\r
+#define MPULOCK (0x0002u) /* MPU Lock */\r
+#define MPUSEGIE (0x0010u) /* MPU Enable NMI on Segment violation */\r
+\r
+/* MPUCTL0 Control Bits */\r
+#define MPUENA_L (0x0001u) /* MPU Enable */\r
+#define MPULOCK_L (0x0002u) /* MPU Lock */\r
+#define MPUSEGIE_L (0x0010u) /* MPU Enable NMI on Segment violation */\r
+\r
+#define MPUPW (0xA500u) /* MPU Access Password */\r
+#define MPUPW_H (0xA5) /* MPU Access Password */\r
+\r
+/* MPUCTL1 Control Bits */\r
+#define MPUSEG1IFG (0x0001u) /* MPU Main Memory Segment 1 violation interupt flag */\r
+#define MPUSEG2IFG (0x0002u) /* MPU Main Memory Segment 2 violation interupt flag */\r
+#define MPUSEG3IFG (0x0004u) /* MPU Main Memory Segment 3 violation interupt flag */\r
+#define MPUSEGIIFG (0x0008u) /* MPU Info Memory Segment violation interupt flag */\r
+#define MPUSEGIPIFG (0x0010u) /* MPU IP Memory Segment violation interupt flag */\r
+\r
+/* MPUCTL1 Control Bits */\r
+#define MPUSEG1IFG_L (0x0001u) /* MPU Main Memory Segment 1 violation interupt flag */\r
+#define MPUSEG2IFG_L (0x0002u) /* MPU Main Memory Segment 2 violation interupt flag */\r
+#define MPUSEG3IFG_L (0x0004u) /* MPU Main Memory Segment 3 violation interupt flag */\r
+#define MPUSEGIIFG_L (0x0008u) /* MPU Info Memory Segment violation interupt flag */\r
+#define MPUSEGIPIFG_L (0x0010u) /* MPU IP Memory Segment violation interupt flag */\r
+\r
+/* MPUSEGB2 Control Bits */\r
+\r
+/* MPUSEGB2 Control Bits */\r
+\r
+/* MPUSEGB2 Control Bits */\r
+\r
+/* MPUSEGB1 Control Bits */\r
+\r
+/* MPUSEGB1 Control Bits */\r
+\r
+/* MPUSEGB1 Control Bits */\r
+\r
+/* MPUSAM Control Bits */\r
+#define MPUSEG1RE (0x0001u) /* MPU Main memory Segment 1 Read enable */\r
+#define MPUSEG1WE (0x0002u) /* MPU Main memory Segment 1 Write enable */\r
+#define MPUSEG1XE (0x0004u) /* MPU Main memory Segment 1 Execute enable */\r
+#define MPUSEG1VS (0x0008u) /* MPU Main memory Segment 1 Violation select */\r
+#define MPUSEG2RE (0x0010u) /* MPU Main memory Segment 2 Read enable */\r
+#define MPUSEG2WE (0x0020u) /* MPU Main memory Segment 2 Write enable */\r
+#define MPUSEG2XE (0x0040u) /* MPU Main memory Segment 2 Execute enable */\r
+#define MPUSEG2VS (0x0080u) /* MPU Main memory Segment 2 Violation select */\r
+#define MPUSEG3RE (0x0100u) /* MPU Main memory Segment 3 Read enable */\r
+#define MPUSEG3WE (0x0200u) /* MPU Main memory Segment 3 Write enable */\r
+#define MPUSEG3XE (0x0400u) /* MPU Main memory Segment 3 Execute enable */\r
+#define MPUSEG3VS (0x0800u) /* MPU Main memory Segment 3 Violation select */\r
+#define MPUSEGIRE (0x1000u) /* MPU Info memory Segment Read enable */\r
+#define MPUSEGIWE (0x2000u) /* MPU Info memory Segment Write enable */\r
+#define MPUSEGIXE (0x4000u) /* MPU Info memory Segment Execute enable */\r
+#define MPUSEGIVS (0x8000u) /* MPU Info memory Segment Violation select */\r
+\r
+/* MPUSAM Control Bits */\r
+#define MPUSEG1RE_L (0x0001u) /* MPU Main memory Segment 1 Read enable */\r
+#define MPUSEG1WE_L (0x0002u) /* MPU Main memory Segment 1 Write enable */\r
+#define MPUSEG1XE_L (0x0004u) /* MPU Main memory Segment 1 Execute enable */\r
+#define MPUSEG1VS_L (0x0008u) /* MPU Main memory Segment 1 Violation select */\r
+#define MPUSEG2RE_L (0x0010u) /* MPU Main memory Segment 2 Read enable */\r
+#define MPUSEG2WE_L (0x0020u) /* MPU Main memory Segment 2 Write enable */\r
+#define MPUSEG2XE_L (0x0040u) /* MPU Main memory Segment 2 Execute enable */\r
+#define MPUSEG2VS_L (0x0080u) /* MPU Main memory Segment 2 Violation select */\r
+\r
+/* MPUSAM Control Bits */\r
+#define MPUSEG3RE_H (0x0001u) /* MPU Main memory Segment 3 Read enable */\r
+#define MPUSEG3WE_H (0x0002u) /* MPU Main memory Segment 3 Write enable */\r
+#define MPUSEG3XE_H (0x0004u) /* MPU Main memory Segment 3 Execute enable */\r
+#define MPUSEG3VS_H (0x0008u) /* MPU Main memory Segment 3 Violation select */\r
+#define MPUSEGIRE_H (0x0010u) /* MPU Info memory Segment Read enable */\r
+#define MPUSEGIWE_H (0x0020u) /* MPU Info memory Segment Write enable */\r
+#define MPUSEGIXE_H (0x0040u) /* MPU Info memory Segment Execute enable */\r
+#define MPUSEGIVS_H (0x0080u) /* MPU Info memory Segment Violation select */\r
+\r
+/* MPUIPC0 Control Bits */\r
+#define MPUIPVS (0x0020u) /* MPU MPU IP protection segment Violation Select */\r
+#define MPUIPENA (0x0040u) /* MPU MPU IP Protection Enable */\r
+#define MPUIPLOCK (0x0080u) /* MPU IP Protection Lock */\r
+\r
+/* MPUIPC0 Control Bits */\r
+#define MPUIPVS_L (0x0020u) /* MPU MPU IP protection segment Violation Select */\r
+#define MPUIPENA_L (0x0040u) /* MPU MPU IP Protection Enable */\r
+#define MPUIPLOCK_L (0x0080u) /* MPU IP Protection Lock */\r
+\r
+/* MPUIPSEGB2 Control Bits */\r
+\r
+/* MPUIPSEGB2 Control Bits */\r
+\r
+/* MPUIPSEGB2 Control Bits */\r
+\r
+/* MPUIPSEGB1 Control Bits */\r
+\r
+/* MPUIPSEGB1 Control Bits */\r
+\r
+/* MPUIPSEGB1 Control Bits */\r
+\r
+#endif\r
+/************************************************************\r
+* HARDWARE MULTIPLIER 32Bit\r
+************************************************************/\r
+#ifdef __MSP430_HAS_MPY32__ /* Definition to show that Module is available */\r
+\r
+#define OFS_MPY (0x0000u) /* Multiply Unsigned/Operand 1 */\r
+#define OFS_MPY_L OFS_MPY\r
+#define OFS_MPY_H OFS_MPY+1\r
+#define OFS_MPYS (0x0002u) /* Multiply Signed/Operand 1 */\r
+#define OFS_MPYS_L OFS_MPYS\r
+#define OFS_MPYS_H OFS_MPYS+1\r
+#define OFS_MAC (0x0004u) /* Multiply Unsigned and Accumulate/Operand 1 */\r
+#define OFS_MAC_L OFS_MAC\r
+#define OFS_MAC_H OFS_MAC+1\r
+#define OFS_MACS (0x0006u) /* Multiply Signed and Accumulate/Operand 1 */\r
+#define OFS_MACS_L OFS_MACS\r
+#define OFS_MACS_H OFS_MACS+1\r
+#define OFS_OP2 (0x0008u) /* Operand 2 */\r
+#define OFS_OP2_L OFS_OP2\r
+#define OFS_OP2_H OFS_OP2+1\r
+#define OFS_RESLO (0x000Au) /* Result Low Word */\r
+#define OFS_RESLO_L OFS_RESLO\r
+#define OFS_RESLO_H OFS_RESLO+1\r
+#define OFS_RESHI (0x000Cu) /* Result High Word */\r
+#define OFS_RESHI_L OFS_RESHI\r
+#define OFS_RESHI_H OFS_RESHI+1\r
+#define OFS_SUMEXT (0x000Eu) /* Sum Extend */\r
+#define OFS_SUMEXT_L OFS_SUMEXT\r
+#define OFS_SUMEXT_H OFS_SUMEXT+1\r
+#define OFS_MPY32CTL0 (0x002Cu)\r
+#define OFS_MPY32CTL0_L OFS_MPY32CTL0\r
+#define OFS_MPY32CTL0_H OFS_MPY32CTL0+1\r
+\r
+#define OFS_MPY32L (0x0010u) /* 32-bit operand 1 - multiply - low word */\r
+#define OFS_MPY32L_L OFS_MPY32L\r
+#define OFS_MPY32L_H OFS_MPY32L+1\r
+#define OFS_MPY32H (0x0012u) /* 32-bit operand 1 - multiply - high word */\r
+#define OFS_MPY32H_L OFS_MPY32H\r
+#define OFS_MPY32H_H OFS_MPY32H+1\r
+#define OFS_MPYS32L (0x0014u) /* 32-bit operand 1 - signed multiply - low word */\r
+#define OFS_MPYS32L_L OFS_MPYS32L\r
+#define OFS_MPYS32L_H OFS_MPYS32L+1\r
+#define OFS_MPYS32H (0x0016u) /* 32-bit operand 1 - signed multiply - high word */\r
+#define OFS_MPYS32H_L OFS_MPYS32H\r
+#define OFS_MPYS32H_H OFS_MPYS32H+1\r
+#define OFS_MAC32L (0x0018u) /* 32-bit operand 1 - multiply accumulate - low word */\r
+#define OFS_MAC32L_L OFS_MAC32L\r
+#define OFS_MAC32L_H OFS_MAC32L+1\r
+#define OFS_MAC32H (0x001Au) /* 32-bit operand 1 - multiply accumulate - high word */\r
+#define OFS_MAC32H_L OFS_MAC32H\r
+#define OFS_MAC32H_H OFS_MAC32H+1\r
+#define OFS_MACS32L (0x001Cu) /* 32-bit operand 1 - signed multiply accumulate - low word */\r
+#define OFS_MACS32L_L OFS_MACS32L\r
+#define OFS_MACS32L_H OFS_MACS32L+1\r
+#define OFS_MACS32H (0x001Eu) /* 32-bit operand 1 - signed multiply accumulate - high word */\r
+#define OFS_MACS32H_L OFS_MACS32H\r
+#define OFS_MACS32H_H OFS_MACS32H+1\r
+#define OFS_OP2L (0x0020u) /* 32-bit operand 2 - low word */\r
+#define OFS_OP2L_L OFS_OP2L\r
+#define OFS_OP2L_H OFS_OP2L+1\r
+#define OFS_OP2H (0x0022u) /* 32-bit operand 2 - high word */\r
+#define OFS_OP2H_L OFS_OP2H\r
+#define OFS_OP2H_H OFS_OP2H+1\r
+#define OFS_RES0 (0x0024u) /* 32x32-bit result 0 - least significant word */\r
+#define OFS_RES0_L OFS_RES0\r
+#define OFS_RES0_H OFS_RES0+1\r
+#define OFS_RES1 (0x0026u) /* 32x32-bit result 1 */\r
+#define OFS_RES1_L OFS_RES1\r
+#define OFS_RES1_H OFS_RES1+1\r
+#define OFS_RES2 (0x0028u) /* 32x32-bit result 2 */\r
+#define OFS_RES2_L OFS_RES2\r
+#define OFS_RES2_H OFS_RES2+1\r
+#define OFS_RES3 (0x002Au) /* 32x32-bit result 3 - most significant word */\r
+#define OFS_RES3_L OFS_RES3\r
+#define OFS_RES3_H OFS_RES3+1\r
+#define OFS_SUMEXT (0x000Eu)\r
+#define OFS_SUMEXT_L OFS_SUMEXT\r
+#define OFS_SUMEXT_H OFS_SUMEXT+1\r
+#define OFS_MPY32CTL0 (0x002Cu) /* MPY32 Control Register 0 */\r
+#define OFS_MPY32CTL0_L OFS_MPY32CTL0\r
+#define OFS_MPY32CTL0_H OFS_MPY32CTL0+1\r
+\r
+#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */\r
+#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */\r
+#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */\r
+#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */\r
+#define OP2_B OP2_L /* Operand 2 (Byte Access) */\r
+#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */\r
+#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */\r
+#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */\r
+#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */\r
+#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */\r
+#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */\r
+#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */\r
+#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */\r
+#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */\r
+#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */\r
+\r
+/* MPY32CTL0 Control Bits */\r
+#define MPYC (0x0001u) /* Carry of the multiplier */\r
+//#define RESERVED (0x0002u) /* Reserved */\r
+#define MPYFRAC (0x0004u) /* Fractional mode */\r
+#define MPYSAT (0x0008u) /* Saturation mode */\r
+#define MPYM0 (0x0010u) /* Multiplier mode Bit:0 */\r
+#define MPYM1 (0x0020u) /* Multiplier mode Bit:1 */\r
+#define OP1_32 (0x0040u) /* Bit-width of operand 1 0:16Bit / 1:32Bit */\r
+#define OP2_32 (0x0080u) /* Bit-width of operand 2 0:16Bit / 1:32Bit */\r
+#define MPYDLYWRTEN (0x0100u) /* Delayed write enable */\r
+#define MPYDLY32 (0x0200u) /* Delayed write mode */\r
+\r
+/* MPY32CTL0 Control Bits */\r
+#define MPYC_L (0x0001u) /* Carry of the multiplier */\r
+//#define RESERVED (0x0002u) /* Reserved */\r
+#define MPYFRAC_L (0x0004u) /* Fractional mode */\r
+#define MPYSAT_L (0x0008u) /* Saturation mode */\r
+#define MPYM0_L (0x0010u) /* Multiplier mode Bit:0 */\r
+#define MPYM1_L (0x0020u) /* Multiplier mode Bit:1 */\r
+#define OP1_32_L (0x0040u) /* Bit-width of operand 1 0:16Bit / 1:32Bit */\r
+#define OP2_32_L (0x0080u) /* Bit-width of operand 2 0:16Bit / 1:32Bit */\r
+\r
+/* MPY32CTL0 Control Bits */\r
+//#define RESERVED (0x0002u) /* Reserved */\r
+#define MPYDLYWRTEN_H (0x0001u) /* Delayed write enable */\r
+#define MPYDLY32_H (0x0002u) /* Delayed write mode */\r
+\r
+#define MPYM_0 (0x0000u) /* Multiplier mode: MPY */\r
+#define MPYM_1 (0x0010u) /* Multiplier mode: MPYS */\r
+#define MPYM_2 (0x0020u) /* Multiplier mode: MAC */\r
+#define MPYM_3 (0x0030u) /* Multiplier mode: MACS */\r
+#define MPYM__MPY (0x0000u) /* Multiplier mode: MPY */\r
+#define MPYM__MPYS (0x0010u) /* Multiplier mode: MPYS */\r
+#define MPYM__MAC (0x0020u) /* Multiplier mode: MAC */\r
+#define MPYM__MACS (0x0030u) /* Multiplier mode: MACS */\r
+\r
+#endif\r
+/************************************************************\r
+* PMM - Power Management System for FRAM\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PMM_FRAM__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PMMCTL0 (0x0000u) /* PMM Control 0 */\r
+#define OFS_PMMCTL0_L OFS_PMMCTL0\r
+#define OFS_PMMCTL0_H OFS_PMMCTL0+1\r
+#define OFS_PMMCTL1 (0x0002u) /* PMM Control 1 */\r
+#define OFS_PMMIFG (0x000Au) /* PMM Interrupt Flag */\r
+#define OFS_PMMIFG_L OFS_PMMIFG\r
+#define OFS_PMMIFG_H OFS_PMMIFG+1\r
+#define OFS_PM5CTL0 (0x0010u) /* PMM Power Mode 5 Control Register 0 */\r
+#define OFS_PM5CTL0_L OFS_PM5CTL0\r
+#define OFS_PM5CTL0_H OFS_PM5CTL0+1\r
+\r
+#define PMMPW (0xA500u) /* PMM Register Write Password */\r
+#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */\r
+\r
+/* PMMCTL0 Control Bits */\r
+#define PMMSWBOR (0x0004u) /* PMM Software BOR */\r
+#define PMMSWPOR (0x0008u) /* PMM Software POR */\r
+#define PMMREGOFF (0x0010u) /* PMM Turn Regulator off */\r
+#define SVSHE (0x0040u) /* SVS high side enable */\r
+#define PMMLPRST (0x0080u) /* PMM Low-Power Reset Enable */\r
+\r
+/* PMMCTL0 Control Bits */\r
+#define PMMSWBOR_L (0x0004u) /* PMM Software BOR */\r
+#define PMMSWPOR_L (0x0008u) /* PMM Software POR */\r
+#define PMMREGOFF_L (0x0010u) /* PMM Turn Regulator off */\r
+#define SVSHE_L (0x0040u) /* SVS high side enable */\r
+#define PMMLPRST_L (0x0080u) /* PMM Low-Power Reset Enable */\r
+\r
+/* PMMCTL1 Control Bits */\r
+#define PMMLPSVEN (0x0002u) /* PMM Low-Power Supervision Enable */\r
+#define PMMLPRNG0 (0x0004u) /* PMM Load Range Control overwrite for LPM2, LPM3 and LPM4 Bit: 0 */\r
+#define PMMLPRNG1 (0x0008u) /* PMM Load Range Control overwrite for LPM2, LPM3 and LPM4 Bit: 1 */\r
+#define PMMAMRNG0 (0x0010u) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 0 */\r
+#define PMMAMRNG1 (0x0020u) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 1 */\r
+#define PMMAMRNG2 (0x0040u) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 2 */\r
+#define PMMAMRNG3 (0x0080u) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 3 */\r
+#define PMMCTL1KEY (0xCC00u) /* PMM PMMCTL1 Register Write Password */\r
+\r
+/* PMMIFG Control Bits */\r
+#define PMMBORIFG (0x0100u) /* PMM Software BOR interrupt flag */\r
+#define PMMRSTIFG (0x0200u) /* PMM RESET pin interrupt flag */\r
+#define PMMPORIFG (0x0400u) /* PMM Software POR interrupt flag */\r
+#define SVSHIFG (0x2000u) /* SVS low side interrupt flag */\r
+#define PMMLPM5IFG (0x8000u) /* LPM5 indication Flag */\r
+\r
+/* PMMIFG Control Bits */\r
+#define PMMBORIFG_H (0x0001u) /* PMM Software BOR interrupt flag */\r
+#define PMMRSTIFG_H (0x0002u) /* PMM RESET pin interrupt flag */\r
+#define PMMPORIFG_H (0x0004u) /* PMM Software POR interrupt flag */\r
+#define SVSHIFG_H (0x0020u) /* SVS low side interrupt flag */\r
+#define PMMLPM5IFG_H (0x0080u) /* LPM5 indication Flag */\r
+\r
+/* PM5CTL0 Power Mode 5 Control Bits */\r
+#define LOCKLPM5 (0x0001u) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */\r
+\r
+/* PM5CTL0 Power Mode 5 Control Bits */\r
+#define LOCKLPM5_L (0x0001u) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */\r
+\r
+\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port1/2 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PAIN (0x0000u) /* Port A Input */\r
+#define OFS_PAIN_L OFS_PAIN\r
+#define OFS_PAIN_H OFS_PAIN+1\r
+#define OFS_PAOUT (0x0002u) /* Port A Output */\r
+#define OFS_PAOUT_L OFS_PAOUT\r
+#define OFS_PAOUT_H OFS_PAOUT+1\r
+#define OFS_PADIR (0x0004u) /* Port A Direction */\r
+#define OFS_PADIR_L OFS_PADIR\r
+#define OFS_PADIR_H OFS_PADIR+1\r
+#define OFS_PAREN (0x0006u) /* Port A Resistor Enable */\r
+#define OFS_PAREN_L OFS_PAREN\r
+#define OFS_PAREN_H OFS_PAREN+1\r
+#define OFS_PASEL0 (0x000Au) /* Port A Selection 0 */\r
+#define OFS_PASEL0_L OFS_PASEL0\r
+#define OFS_PASEL0_H OFS_PASEL0+1\r
+#define OFS_PASEL1 (0x000Cu) /* Port A Selection 1 */\r
+#define OFS_PASEL1_L OFS_PASEL1\r
+#define OFS_PASEL1_H OFS_PASEL1+1\r
+#define OFS_PASELC (0x0016u) /* Port A Complement Selection */\r
+#define OFS_PASELC_L OFS_PASELC\r
+#define OFS_PASELC_H OFS_PASELC+1\r
+#define OFS_PAIES (0x0018u) /* Port A Interrupt Edge Select */\r
+#define OFS_PAIES_L OFS_PAIES\r
+#define OFS_PAIES_H OFS_PAIES+1\r
+#define OFS_PAIE (0x001Au) /* Port A Interrupt Enable */\r
+#define OFS_PAIE_L OFS_PAIE\r
+#define OFS_PAIE_H OFS_PAIE+1\r
+#define OFS_PAIFG (0x001Cu) /* Port A Interrupt Flag */\r
+#define OFS_PAIFG_L OFS_PAIFG\r
+#define OFS_PAIFG_H OFS_PAIFG+1\r
+\r
+\r
+#define OFS_P1IN (0x0000u)\r
+#define OFS_P1OUT (0x0002u)\r
+#define OFS_P1DIR (0x0004u)\r
+#define OFS_P1REN (0x0006u)\r
+#define OFS_P1SEL0 (0x000Au)\r
+#define OFS_P1SEL1 (0x000Cu)\r
+#define OFS_P1SELC (0x0016u)\r
+#define OFS_P1IV (0x000Eu) /* Port 1 Interrupt Vector Word */\r
+#define OFS_P1IES (0x0018u)\r
+#define OFS_P1IE (0x001Au)\r
+#define OFS_P1IFG (0x001Cu)\r
+#define OFS_P2IN (0x0001u)\r
+#define OFS_P2OUT (0x0003u)\r
+#define OFS_P2DIR (0x0005u)\r
+#define OFS_P2REN (0x0007u)\r
+#define OFS_P2SEL0 (0x000Bu)\r
+#define OFS_P2SEL1 (0x000Du)\r
+#define OFS_P2SELC (0x0017u)\r
+#define OFS_P2IV (0x001Eu) /* Port 2 Interrupt Vector Word */\r
+#define OFS_P2IES (0x0019u)\r
+#define OFS_P2IE (0x001Bu)\r
+#define OFS_P2IFG (0x001du)\r
+#define P1IN (PAIN_L) /* Port 1 Input */\r
+#define P1OUT (PAOUT_L) /* Port 1 Output */\r
+#define P1DIR (PADIR_L) /* Port 1 Direction */\r
+#define P1REN (PAREN_L) /* Port 1 Resistor Enable */\r
+#define P1SEL0 (PASEL0_L) /* Port 1 Selection 0 */\r
+#define P1SEL1 (PASEL1_L) /* Port 1 Selection 1 */\r
+#define P1SELC (PASELC_L) /* Port 1 Complement Selection */\r
+#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */\r
+#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */\r
+#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */\r
+\r
+//Definitions for P1IV\r
+#define P1IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P1IV_P1IFG0 (0x0002u) /* P1IV P1IFG.0 */\r
+#define P1IV_P1IFG1 (0x0004u) /* P1IV P1IFG.1 */\r
+#define P1IV_P1IFG2 (0x0006u) /* P1IV P1IFG.2 */\r
+#define P1IV_P1IFG3 (0x0008u) /* P1IV P1IFG.3 */\r
+#define P1IV_P1IFG4 (0x000Au) /* P1IV P1IFG.4 */\r
+#define P1IV_P1IFG5 (0x000Cu) /* P1IV P1IFG.5 */\r
+#define P1IV_P1IFG6 (0x000Eu) /* P1IV P1IFG.6 */\r
+#define P1IV_P1IFG7 (0x0010u) /* P1IV P1IFG.7 */\r
+\r
+#define P2IN (PAIN_H) /* Port 2 Input */\r
+#define P2OUT (PAOUT_H) /* Port 2 Output */\r
+#define P2DIR (PADIR_H) /* Port 2 Direction */\r
+#define P2REN (PAREN_H) /* Port 2 Resistor Enable */\r
+#define P2SEL0 (PASEL0_H) /* Port 2 Selection 0 */\r
+#define P2SEL1 (PASEL1_H) /* Port 2 Selection 1 */\r
+#define P2SELC (PASELC_H) /* Port 2 Complement Selection */\r
+#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */\r
+#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */\r
+#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */\r
+\r
+//Definitions for P2IV\r
+#define P2IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P2IV_P2IFG0 (0x0002u) /* P2IV P2IFG.0 */\r
+#define P2IV_P2IFG1 (0x0004u) /* P2IV P2IFG.1 */\r
+#define P2IV_P2IFG2 (0x0006u) /* P2IV P2IFG.2 */\r
+#define P2IV_P2IFG3 (0x0008u) /* P2IV P2IFG.3 */\r
+#define P2IV_P2IFG4 (0x000Au) /* P2IV P2IFG.4 */\r
+#define P2IV_P2IFG5 (0x000Cu) /* P2IV P2IFG.5 */\r
+#define P2IV_P2IFG6 (0x000Eu) /* P2IV P2IFG.6 */\r
+#define P2IV_P2IFG7 (0x0010u) /* P2IV P2IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port3/4 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PBIN (0x0000u) /* Port B Input */\r
+#define OFS_PBIN_L OFS_PBIN\r
+#define OFS_PBIN_H OFS_PBIN+1\r
+#define OFS_PBOUT (0x0002u) /* Port B Output */\r
+#define OFS_PBOUT_L OFS_PBOUT\r
+#define OFS_PBOUT_H OFS_PBOUT+1\r
+#define OFS_PBDIR (0x0004u) /* Port B Direction */\r
+#define OFS_PBDIR_L OFS_PBDIR\r
+#define OFS_PBDIR_H OFS_PBDIR+1\r
+#define OFS_PBREN (0x0006u) /* Port B Resistor Enable */\r
+#define OFS_PBREN_L OFS_PBREN\r
+#define OFS_PBREN_H OFS_PBREN+1\r
+#define OFS_PBSEL0 (0x000Au) /* Port B Selection 0 */\r
+#define OFS_PBSEL0_L OFS_PBSEL0\r
+#define OFS_PBSEL0_H OFS_PBSEL0+1\r
+#define OFS_PBSEL1 (0x000Cu) /* Port B Selection 1 */\r
+#define OFS_PBSEL1_L OFS_PBSEL1\r
+#define OFS_PBSEL1_H OFS_PBSEL1+1\r
+#define OFS_PBSELC (0x0016u) /* Port B Complement Selection */\r
+#define OFS_PBSELC_L OFS_PBSELC\r
+#define OFS_PBSELC_H OFS_PBSELC+1\r
+#define OFS_PBIES (0x0018u) /* Port B Interrupt Edge Select */\r
+#define OFS_PBIES_L OFS_PBIES\r
+#define OFS_PBIES_H OFS_PBIES+1\r
+#define OFS_PBIE (0x001Au) /* Port B Interrupt Enable */\r
+#define OFS_PBIE_L OFS_PBIE\r
+#define OFS_PBIE_H OFS_PBIE+1\r
+#define OFS_PBIFG (0x001Cu) /* Port B Interrupt Flag */\r
+#define OFS_PBIFG_L OFS_PBIFG\r
+#define OFS_PBIFG_H OFS_PBIFG+1\r
+\r
+\r
+#define OFS_P3IN (0x0000u)\r
+#define OFS_P3OUT (0x0002u)\r
+#define OFS_P3DIR (0x0004u)\r
+#define OFS_P3REN (0x0006u)\r
+#define OFS_P3SEL0 (0x000Au)\r
+#define OFS_P3SEL1 (0x000Cu)\r
+#define OFS_P3SELC (0x0016u)\r
+#define OFS_P3IV (0x000Eu) /* Port 3 Interrupt Vector Word */\r
+#define OFS_P3IES (0x0018u)\r
+#define OFS_P3IE (0x001Au)\r
+#define OFS_P3IFG (0x001Cu)\r
+#define OFS_P4IN (0x0001u)\r
+#define OFS_P4OUT (0x0003u)\r
+#define OFS_P4DIR (0x0005u)\r
+#define OFS_P4REN (0x0007u)\r
+#define OFS_P4SEL0 (0x000Bu)\r
+#define OFS_P4SEL1 (0x000Du)\r
+#define OFS_P4SELC (0x0017u)\r
+#define OFS_P4IV (0x001Eu) /* Port 4 Interrupt Vector Word */\r
+#define OFS_P4IES (0x0019u)\r
+#define OFS_P4IE (0x001Bu)\r
+#define OFS_P4IFG (0x001du)\r
+#define P3IN (PBIN_L) /* Port 3 Input */\r
+#define P3OUT (PBOUT_L) /* Port 3 Output */\r
+#define P3DIR (PBDIR_L) /* Port 3 Direction */\r
+#define P3REN (PBREN_L) /* Port 3 Resistor Enable */\r
+#define P3SEL0 (PBSEL0_L) /* Port 3 Selection 0 */\r
+#define P3SEL1 (PBSEL1_L) /* Port 3 Selection 1 */\r
+#define P3SELC (PBSELC_L) /* Port 3 Complement Selection */\r
+#define P3IES (PBIES_L) /* Port 3 Interrupt Edge Select */\r
+#define P3IE (PBIE_L) /* Port 3 Interrupt Enable */\r
+#define P3IFG (PBIFG_L) /* Port 3 Interrupt Flag */\r
+\r
+//Definitions for P3IV\r
+#define P3IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P3IV_P3IFG0 (0x0002u) /* P3IV P3IFG.0 */\r
+#define P3IV_P3IFG1 (0x0004u) /* P3IV P3IFG.1 */\r
+#define P3IV_P3IFG2 (0x0006u) /* P3IV P3IFG.2 */\r
+#define P3IV_P3IFG3 (0x0008u) /* P3IV P3IFG.3 */\r
+#define P3IV_P3IFG4 (0x000Au) /* P3IV P3IFG.4 */\r
+#define P3IV_P3IFG5 (0x000Cu) /* P3IV P3IFG.5 */\r
+#define P3IV_P3IFG6 (0x000Eu) /* P3IV P3IFG.6 */\r
+#define P3IV_P3IFG7 (0x0010u) /* P3IV P3IFG.7 */\r
+\r
+#define P4IN (PBIN_H) /* Port 4 Input */\r
+#define P4OUT (PBOUT_H) /* Port 4 Output */\r
+#define P4DIR (PBDIR_H) /* Port 4 Direction */\r
+#define P4REN (PBREN_H) /* Port 4 Resistor Enable */\r
+#define P4SEL0 (PBSEL0_H) /* Port 4 Selection 0 */\r
+#define P4SEL1 (PBSEL1_H) /* Port 4 Selection 1 */\r
+#define P4SELC (PBSELC_H) /* Port 4 Complement Selection */\r
+#define P4IES (PBIES_H) /* Port 4 Interrupt Edge Select */\r
+#define P4IE (PBIE_H) /* Port 4 Interrupt Enable */\r
+#define P4IFG (PBIFG_H) /* Port 4 Interrupt Flag */\r
+\r
+//Definitions for P4IV\r
+#define P4IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P4IV_P4IFG0 (0x0002u) /* P4IV P4IFG.0 */\r
+#define P4IV_P4IFG1 (0x0004u) /* P4IV P4IFG.1 */\r
+#define P4IV_P4IFG2 (0x0006u) /* P4IV P4IFG.2 */\r
+#define P4IV_P4IFG3 (0x0008u) /* P4IV P4IFG.3 */\r
+#define P4IV_P4IFG4 (0x000Au) /* P4IV P4IFG.4 */\r
+#define P4IV_P4IFG5 (0x000Cu) /* P4IV P4IFG.5 */\r
+#define P4IV_P4IFG6 (0x000Eu) /* P4IV P4IFG.6 */\r
+#define P4IV_P4IFG7 (0x0010u) /* P4IV P4IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port5/6 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PCIN (0x0000u) /* Port C Input */\r
+#define OFS_PCIN_L OFS_PCIN\r
+#define OFS_PCIN_H OFS_PCIN+1\r
+#define OFS_PCOUT (0x0002u) /* Port C Output */\r
+#define OFS_PCOUT_L OFS_PCOUT\r
+#define OFS_PCOUT_H OFS_PCOUT+1\r
+#define OFS_PCDIR (0x0004u) /* Port C Direction */\r
+#define OFS_PCDIR_L OFS_PCDIR\r
+#define OFS_PCDIR_H OFS_PCDIR+1\r
+#define OFS_PCREN (0x0006u) /* Port C Resistor Enable */\r
+#define OFS_PCREN_L OFS_PCREN\r
+#define OFS_PCREN_H OFS_PCREN+1\r
+#define OFS_PCSEL0 (0x000Au) /* Port C Selection 0 */\r
+#define OFS_PCSEL0_L OFS_PCSEL0\r
+#define OFS_PCSEL0_H OFS_PCSEL0+1\r
+#define OFS_PCSEL1 (0x000Cu) /* Port C Selection 1 */\r
+#define OFS_PCSEL1_L OFS_PCSEL1\r
+#define OFS_PCSEL1_H OFS_PCSEL1+1\r
+#define OFS_PCSELC (0x0016u) /* Port C Complement Selection */\r
+#define OFS_PCSELC_L OFS_PCSELC\r
+#define OFS_PCSELC_H OFS_PCSELC+1\r
+#define OFS_PCIES (0x0018u) /* Port C Interrupt Edge Select */\r
+#define OFS_PCIES_L OFS_PCIES\r
+#define OFS_PCIES_H OFS_PCIES+1\r
+#define OFS_PCIE (0x001Au) /* Port C Interrupt Enable */\r
+#define OFS_PCIE_L OFS_PCIE\r
+#define OFS_PCIE_H OFS_PCIE+1\r
+#define OFS_PCIFG (0x001Cu) /* Port C Interrupt Flag */\r
+#define OFS_PCIFG_L OFS_PCIFG\r
+#define OFS_PCIFG_H OFS_PCIFG+1\r
+\r
+\r
+#define OFS_P5IN (0x0000u)\r
+#define OFS_P5OUT (0x0002u)\r
+#define OFS_P5DIR (0x0004u)\r
+#define OFS_P5REN (0x0006u)\r
+#define OFS_P5SEL0 (0x000Au)\r
+#define OFS_P5SEL1 (0x000Cu)\r
+#define OFS_P5SELC (0x0016u)\r
+#define OFS_P5IV (0x000Eu) /* Port 5 Interrupt Vector Word */\r
+#define OFS_P5IES (0x0018u)\r
+#define OFS_P5IE (0x001Au)\r
+#define OFS_P5IFG (0x001Cu)\r
+#define OFS_P6IN (0x0001u)\r
+#define OFS_P6OUT (0x0003u)\r
+#define OFS_P6DIR (0x0005u)\r
+#define OFS_P6REN (0x0007u)\r
+#define OFS_P6SEL0 (0x000Bu)\r
+#define OFS_P6SEL1 (0x000Du)\r
+#define OFS_P6SELC (0x0017u)\r
+#define OFS_P6IV (0x001Eu) /* Port 6 Interrupt Vector Word */\r
+#define OFS_P6IES (0x0019u)\r
+#define OFS_P6IE (0x001Bu)\r
+#define OFS_P6IFG (0x001du)\r
+#define P5IN (PCIN_L) /* Port 5 Input */\r
+#define P5OUT (PCOUT_L) /* Port 5 Output */\r
+#define P5DIR (PCDIR_L) /* Port 5 Direction */\r
+#define P5REN (PCREN_L) /* Port 5 Resistor Enable */\r
+#define P5SEL0 (PCSEL0_L) /* Port 5 Selection 0 */\r
+#define P5SEL1 (PCSEL1_L) /* Port 5 Selection 1 */\r
+#define P5SELC (PCSELC_L) /* Port 5 Complement Selection */\r
+#define P5IES (PCIES_L) /* Port 5 Interrupt Edge Select */\r
+#define P5IE (PCIE_L) /* Port 5 Interrupt Enable */\r
+#define P5IFG (PCIFG_L) /* Port 5 Interrupt Flag */\r
+\r
+//Definitions for P5IV\r
+#define P5IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P5IV_P5IFG0 (0x0002u) /* P5IV P5IFG.0 */\r
+#define P5IV_P5IFG1 (0x0004u) /* P5IV P5IFG.1 */\r
+#define P5IV_P5IFG2 (0x0006u) /* P5IV P5IFG.2 */\r
+#define P5IV_P5IFG3 (0x0008u) /* P5IV P5IFG.3 */\r
+#define P5IV_P5IFG4 (0x000Au) /* P5IV P5IFG.4 */\r
+#define P5IV_P5IFG5 (0x000Cu) /* P5IV P5IFG.5 */\r
+#define P5IV_P5IFG6 (0x000Eu) /* P5IV P5IFG.6 */\r
+#define P5IV_P5IFG7 (0x0010u) /* P5IV P5IFG.7 */\r
+\r
+#define P6IN (PCIN_H) /* Port 6 Input */\r
+#define P6OUT (PCOUT_H) /* Port 6 Output */\r
+#define P6DIR (PCDIR_H) /* Port 6 Direction */\r
+#define P6REN (PCREN_H) /* Port 6 Resistor Enable */\r
+#define P6SEL0 (PCSEL0_H) /* Port 6 Selection 0 */\r
+#define P6SEL1 (PCSEL1_H) /* Port 6 Selection 1 */\r
+#define P6SELC (PCSELC_H) /* Port 6 Complement Selection */\r
+#define P6IES (PCIES_H) /* Port 6 Interrupt Edge Select */\r
+#define P6IE (PCIE_H) /* Port 6 Interrupt Enable */\r
+#define P6IFG (PCIFG_H) /* Port 6 Interrupt Flag */\r
+\r
+//Definitions for P6IV\r
+#define P6IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P6IV_P6IFG0 (0x0002u) /* P6IV P6IFG.0 */\r
+#define P6IV_P6IFG1 (0x0004u) /* P6IV P6IFG.1 */\r
+#define P6IV_P6IFG2 (0x0006u) /* P6IV P6IFG.2 */\r
+#define P6IV_P6IFG3 (0x0008u) /* P6IV P6IFG.3 */\r
+#define P6IV_P6IFG4 (0x000Au) /* P6IV P6IFG.4 */\r
+#define P6IV_P6IFG5 (0x000Cu) /* P6IV P6IFG.5 */\r
+#define P6IV_P6IFG6 (0x000Eu) /* P6IV P6IFG.6 */\r
+#define P6IV_P6IFG7 (0x0010u) /* P6IV P6IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port7/8 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PDIN (0x0000u) /* Port D Input */\r
+#define OFS_PDIN_L OFS_PDIN\r
+#define OFS_PDIN_H OFS_PDIN+1\r
+#define OFS_PDOUT (0x0002u) /* Port D Output */\r
+#define OFS_PDOUT_L OFS_PDOUT\r
+#define OFS_PDOUT_H OFS_PDOUT+1\r
+#define OFS_PDDIR (0x0004u) /* Port D Direction */\r
+#define OFS_PDDIR_L OFS_PDDIR\r
+#define OFS_PDDIR_H OFS_PDDIR+1\r
+#define OFS_PDREN (0x0006u) /* Port D Resistor Enable */\r
+#define OFS_PDREN_L OFS_PDREN\r
+#define OFS_PDREN_H OFS_PDREN+1\r
+#define OFS_PDSEL0 (0x000Au) /* Port D Selection 0 */\r
+#define OFS_PDSEL0_L OFS_PDSEL0\r
+#define OFS_PDSEL0_H OFS_PDSEL0+1\r
+#define OFS_PDSEL1 (0x000Cu) /* Port D Selection 1 */\r
+#define OFS_PDSEL1_L OFS_PDSEL1\r
+#define OFS_PDSEL1_H OFS_PDSEL1+1\r
+#define OFS_PDSELC (0x0016u) /* Port D Complement Selection */\r
+#define OFS_PDSELC_L OFS_PDSELC\r
+#define OFS_PDSELC_H OFS_PDSELC+1\r
+#define OFS_PDIES (0x0018u) /* Port D Interrupt Edge Select */\r
+#define OFS_PDIES_L OFS_PDIES\r
+#define OFS_PDIES_H OFS_PDIES+1\r
+#define OFS_PDIE (0x001Au) /* Port D Interrupt Enable */\r
+#define OFS_PDIE_L OFS_PDIE\r
+#define OFS_PDIE_H OFS_PDIE+1\r
+#define OFS_PDIFG (0x001Cu) /* Port D Interrupt Flag */\r
+#define OFS_PDIFG_L OFS_PDIFG\r
+#define OFS_PDIFG_H OFS_PDIFG+1\r
+\r
+\r
+#define OFS_P7IN (0x0000u)\r
+#define OFS_P7OUT (0x0002u)\r
+#define OFS_P7DIR (0x0004u)\r
+#define OFS_P7REN (0x0006u)\r
+#define OFS_P7SEL0 (0x000Au)\r
+#define OFS_P7SEL1 (0x000Cu)\r
+#define OFS_P7SELC (0x0016u)\r
+#define OFS_P7IV (0x000Eu) /* Port 7 Interrupt Vector Word */\r
+#define OFS_P7IES (0x0018u)\r
+#define OFS_P7IE (0x001Au)\r
+#define OFS_P7IFG (0x001Cu)\r
+#define OFS_P8IN (0x0001u)\r
+#define OFS_P8OUT (0x0003u)\r
+#define OFS_P8DIR (0x0005u)\r
+#define OFS_P8REN (0x0007u)\r
+#define OFS_P8SEL0 (0x000Bu)\r
+#define OFS_P8SEL1 (0x000Du)\r
+#define OFS_P8SELC (0x0017u)\r
+#define OFS_P8IV (0x001Eu) /* Port 8 Interrupt Vector Word */\r
+#define OFS_P8IES (0x0019u)\r
+#define OFS_P8IE (0x001Bu)\r
+#define OFS_P8IFG (0x001du)\r
+#define P7IN (PDIN_L) /* Port 7 Input */\r
+#define P7OUT (PDOUT_L) /* Port 7 Output */\r
+#define P7DIR (PDDIR_L) /* Port 7 Direction */\r
+#define P7REN (PDREN_L) /* Port 7 Resistor Enable */\r
+#define P7SEL0 (PDSEL0_L) /* Port 7 Selection 0 */\r
+#define P7SEL1 (PDSEL1_L) /* Port 7 Selection 1 */\r
+#define P7SELC (PDSELC_L) /* Port 7 Complement Selection */\r
+#define P7IES (PDIES_L) /* Port 7 Interrupt Edge Select */\r
+#define P7IE (PDIE_L) /* Port 7 Interrupt Enable */\r
+#define P7IFG (PDIFG_L) /* Port 7 Interrupt Flag */\r
+\r
+//Definitions for P7IV\r
+#define P7IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P7IV_P7IFG0 (0x0002u) /* P7IV P7IFG.0 */\r
+#define P7IV_P7IFG1 (0x0004u) /* P7IV P7IFG.1 */\r
+#define P7IV_P7IFG2 (0x0006u) /* P7IV P7IFG.2 */\r
+#define P7IV_P7IFG3 (0x0008u) /* P7IV P7IFG.3 */\r
+#define P7IV_P7IFG4 (0x000Au) /* P7IV P7IFG.4 */\r
+#define P7IV_P7IFG5 (0x000Cu) /* P7IV P7IFG.5 */\r
+#define P7IV_P7IFG6 (0x000Eu) /* P7IV P7IFG.6 */\r
+#define P7IV_P7IFG7 (0x0010u) /* P7IV P7IFG.7 */\r
+\r
+#define P8IN (PDIN_H) /* Port 8 Input */\r
+#define P8OUT (PDOUT_H) /* Port 8 Output */\r
+#define P8DIR (PDDIR_H) /* Port 8 Direction */\r
+#define P8REN (PDREN_H) /* Port 8 Resistor Enable */\r
+#define P8SEL0 (PDSEL0_H) /* Port 8 Selection 0 */\r
+#define P8SEL1 (PDSEL1_H) /* Port 8 Selection 1 */\r
+#define P8SELC (PDSELC_H) /* Port 8 Complement Selection */\r
+#define P8IES (PDIES_H) /* Port 8 Interrupt Edge Select */\r
+#define P8IE (PDIE_H) /* Port 8 Interrupt Enable */\r
+#define P8IFG (PDIFG_H) /* Port 8 Interrupt Flag */\r
+\r
+//Definitions for P8IV\r
+#define P8IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P8IV_P8IFG0 (0x0002u) /* P8IV P8IFG.0 */\r
+#define P8IV_P8IFG1 (0x0004u) /* P8IV P8IFG.1 */\r
+#define P8IV_P8IFG2 (0x0006u) /* P8IV P8IFG.2 */\r
+#define P8IV_P8IFG3 (0x0008u) /* P8IV P8IFG.3 */\r
+#define P8IV_P8IFG4 (0x000Au) /* P8IV P8IFG.4 */\r
+#define P8IV_P8IFG5 (0x000Cu) /* P8IV P8IFG.5 */\r
+#define P8IV_P8IFG6 (0x000Eu) /* P8IV P8IFG.6 */\r
+#define P8IV_P8IFG7 (0x0010u) /* P8IV P8IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port9/10 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT9_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORT10_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTE_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PEIN (0x0000u) /* Port E Input */\r
+#define OFS_PEIN_L OFS_PEIN\r
+#define OFS_PEIN_H OFS_PEIN+1\r
+#define OFS_PEOUT (0x0002u) /* Port E Output */\r
+#define OFS_PEOUT_L OFS_PEOUT\r
+#define OFS_PEOUT_H OFS_PEOUT+1\r
+#define OFS_PEDIR (0x0004u) /* Port E Direction */\r
+#define OFS_PEDIR_L OFS_PEDIR\r
+#define OFS_PEDIR_H OFS_PEDIR+1\r
+#define OFS_PEREN (0x0006u) /* Port E Resistor Enable */\r
+#define OFS_PEREN_L OFS_PEREN\r
+#define OFS_PEREN_H OFS_PEREN+1\r
+#define OFS_PESEL0 (0x000Au) /* Port E Selection 0 */\r
+#define OFS_PESEL0_L OFS_PESEL0\r
+#define OFS_PESEL0_H OFS_PESEL0+1\r
+#define OFS_PESEL1 (0x000Cu) /* Port E Selection 1 */\r
+#define OFS_PESEL1_L OFS_PESEL1\r
+#define OFS_PESEL1_H OFS_PESEL1+1\r
+#define OFS_PESELC (0x0016u) /* Port E Complement Selection */\r
+#define OFS_PESELC_L OFS_PESELC\r
+#define OFS_PESELC_H OFS_PESELC+1\r
+#define OFS_PEIES (0x0018u) /* Port E Interrupt Edge Select */\r
+#define OFS_PEIES_L OFS_PEIES\r
+#define OFS_PEIES_H OFS_PEIES+1\r
+#define OFS_PEIE (0x001Au) /* Port E Interrupt Enable */\r
+#define OFS_PEIE_L OFS_PEIE\r
+#define OFS_PEIE_H OFS_PEIE+1\r
+#define OFS_PEIFG (0x001Cu) /* Port E Interrupt Flag */\r
+#define OFS_PEIFG_L OFS_PEIFG\r
+#define OFS_PEIFG_H OFS_PEIFG+1\r
+\r
+\r
+#define OFS_P9IN (0x0000u)\r
+#define OFS_P9OUT (0x0002u)\r
+#define OFS_P9DIR (0x0004u)\r
+#define OFS_P9REN (0x0006u)\r
+#define OFS_P9SEL0 (0x000Au)\r
+#define OFS_P9SEL1 (0x000Cu)\r
+#define OFS_P9SELC (0x0016u)\r
+#define OFS_P9IV (0x000Eu) /* Port 9 Interrupt Vector Word */\r
+#define OFS_P9IES (0x0018u)\r
+#define OFS_P9IE (0x001Au)\r
+#define OFS_P9IFG (0x001Cu)\r
+#define OFS_P10IN (0x0001u)\r
+#define OFS_P10OUT (0x0003u)\r
+#define OFS_P10DIR (0x0005u)\r
+#define OFS_P10REN (0x0007u)\r
+#define OFS_P10SEL0 (0x000Bu)\r
+#define OFS_P10SEL1 (0x000Du)\r
+#define OFS_P10SELC (0x0017u)\r
+#define OFS_P10IV (0x001Eu) /* Port 10 Interrupt Vector Word */\r
+#define OFS_P10IES (0x0019u)\r
+#define OFS_P10IE (0x001Bu)\r
+#define OFS_P10IFG (0x001du)\r
+#define P9IN (PEIN_L) /* Port 9 Input */\r
+#define P9OUT (PEOUT_L) /* Port 9 Output */\r
+#define P9DIR (PEDIR_L) /* Port 9 Direction */\r
+#define P9REN (PEREN_L) /* Port 9 Resistor Enable */\r
+#define P9SEL0 (PESEL0_L) /* Port 9 Selection 0 */\r
+#define P9SEL1 (PESEL1_L) /* Port 9 Selection 1 */\r
+#define P9SELC (PESELC_L) /* Port 9 Complement Selection */\r
+#define P9IES (PEIES_L) /* Port 9 Interrupt Edge Select */\r
+#define P9IE (PEIE_L) /* Port 9 Interrupt Enable */\r
+#define P9IFG (PEIFG_L) /* Port 9 Interrupt Flag */\r
+\r
+//Definitions for P9IV\r
+#define P9IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P9IV_P9IFG0 (0x0002u) /* P9IV P9IFG.0 */\r
+#define P9IV_P9IFG1 (0x0004u) /* P9IV P9IFG.1 */\r
+#define P9IV_P9IFG2 (0x0006u) /* P9IV P9IFG.2 */\r
+#define P9IV_P9IFG3 (0x0008u) /* P9IV P9IFG.3 */\r
+#define P9IV_P9IFG4 (0x000Au) /* P9IV P9IFG.4 */\r
+#define P9IV_P9IFG5 (0x000Cu) /* P9IV P9IFG.5 */\r
+#define P9IV_P9IFG6 (0x000Eu) /* P9IV P9IFG.6 */\r
+#define P9IV_P9IFG7 (0x0010u) /* P9IV P9IFG.7 */\r
+\r
+#define P10IN (PEIN_H) /* Port 10 Input */\r
+#define P10OUT (PEOUT_H) /* Port 10 Output */\r
+#define P10DIR (PEDIR_H) /* Port 10 Direction */\r
+#define P10REN (PEREN_H) /* Port 10 Resistor Enable */\r
+#define P10SEL0 (PESEL0_H) /* Port 10 Selection 0 */\r
+#define P10SEL1 (PESEL1_H) /* Port 10 Selection 1 */\r
+#define P10SELC (PESELC_H) /* Port 10 Complement Selection */\r
+#define P10IES (PEIES_H) /* Port 10 Interrupt Edge Select */\r
+#define P10IE (PEIE_H) /* Port 10 Interrupt Enable */\r
+#define P10IFG (PEIFG_H) /* Port 10 Interrupt Flag */\r
+\r
+//Definitions for P10IV\r
+#define P10IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P10IV_P10IFG0 (0x0002u) /* P10IV P10IFG.0 */\r
+#define P10IV_P10IFG1 (0x0004u) /* P10IV P10IFG.1 */\r
+#define P10IV_P10IFG2 (0x0006u) /* P10IV P10IFG.2 */\r
+#define P10IV_P10IFG3 (0x0008u) /* P10IV P10IFG.3 */\r
+#define P10IV_P10IFG4 (0x000Au) /* P10IV P10IFG.4 */\r
+#define P10IV_P10IFG5 (0x000Cu) /* P10IV P10IFG.5 */\r
+#define P10IV_P10IFG6 (0x000Eu) /* P10IV P10IFG.6 */\r
+#define P10IV_P10IFG7 (0x0010u) /* P10IV P10IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O Port11 Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORT11_R__ /* Definition to show that Module is available */\r
+#ifdef __MSP430_HAS_PORTF_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PFIN (0x0000u) /* Port F Input */\r
+#define OFS_PFIN_L OFS_PFIN\r
+#define OFS_PFIN_H OFS_PFIN+1\r
+#define OFS_PFOUT (0x0002u) /* Port F Output */\r
+#define OFS_PFOUT_L OFS_PFOUT\r
+#define OFS_PFOUT_H OFS_PFOUT+1\r
+#define OFS_PFDIR (0x0004u) /* Port F Direction */\r
+#define OFS_PFDIR_L OFS_PFDIR\r
+#define OFS_PFDIR_H OFS_PFDIR+1\r
+#define OFS_PFREN (0x0006u) /* Port F Resistor Enable */\r
+#define OFS_PFREN_L OFS_PFREN\r
+#define OFS_PFREN_H OFS_PFREN+1\r
+#define OFS_PFSEL0 (0x000Au) /* Port F Selection 0 */\r
+#define OFS_PFSEL0_L OFS_PFSEL0\r
+#define OFS_PFSEL0_H OFS_PFSEL0+1\r
+#define OFS_PFSEL1 (0x000Cu) /* Port F Selection 1 */\r
+#define OFS_PFSEL1_L OFS_PFSEL1\r
+#define OFS_PFSEL1_H OFS_PFSEL1+1\r
+#define OFS_PFSELC (0x0016u) /* Port F Complement Selection */\r
+#define OFS_PFSELC_L OFS_PFSELC\r
+#define OFS_PFSELC_H OFS_PFSELC+1\r
+#define OFS_PFIES (0x0018u) /* Port F Interrupt Edge Select */\r
+#define OFS_PFIES_L OFS_PFIES\r
+#define OFS_PFIES_H OFS_PFIES+1\r
+#define OFS_PFIE (0x001Au) /* Port F Interrupt Enable */\r
+#define OFS_PFIE_L OFS_PFIE\r
+#define OFS_PFIE_H OFS_PFIE+1\r
+#define OFS_PFIFG (0x001Cu) /* Port F Interrupt Flag */\r
+#define OFS_PFIFG_L OFS_PFIFG\r
+#define OFS_PFIFG_H OFS_PFIFG+1\r
+\r
+\r
+#define OFS_P11IN (0x0000u)\r
+#define OFS_P11OUT (0x0002u)\r
+#define OFS_P11DIR (0x0004u)\r
+#define OFS_P11REN (0x0006u)\r
+#define OFS_P11SEL0 (0x000Au)\r
+#define OFS_P11SEL1 (0x000Cu)\r
+#define OFS_P11SELC (0x0016u)\r
+#define OFS_P11IV (0x000Eu) /* Port 11 Interrupt Vector Word */\r
+#define OFS_P11IES (0x0018u)\r
+#define OFS_P11IE (0x001Au)\r
+#define OFS_P11IFG (0x001Cu)\r
+#define P11IN (PFIN_L) /* Port 11 Input */\r
+#define P11OUT (PFOUT_L) /* Port 11 Output */\r
+#define P11DIR (PFDIR_L) /* Port 11 Direction */\r
+#define P11REN (PFREN_L) /* Port 11 Resistor Enable */\r
+#define P11SEL0 (PFSEL0_L) /* Port 11 Selection0 */\r
+#define P11SEL1 (PFSEL1_L) /* Port 11 Selection1 */\r
+#define OFS_P11SELC (0x0017u)\r
+\r
+#define P11IES (PFIES_L) /* Port 11 Interrupt Edge Select */\r
+#define P11IE (PFIE_L) /* Port 11 Interrupt Enable */\r
+#define P11IFG (PFIFG_L) /* Port 11 Interrupt Flag */\r
+\r
+//Definitions for P11IV\r
+#define P11IV_NONE (0x0000u) /* No Interrupt pending */\r
+#define P11IV_P11IFG0 (0x0002u) /* P11IV P11IFG.0 */\r
+#define P11IV_P11IFG1 (0x0004u) /* P11IV P11IFG.1 */\r
+#define P11IV_P11IFG2 (0x0006u) /* P11IV P11IFG.2 */\r
+#define P11IV_P11IFG3 (0x0008u) /* P11IV P11IFG.3 */\r
+#define P11IV_P11IFG4 (0x000Au) /* P11IV P11IFG.4 */\r
+#define P11IV_P11IFG5 (0x000Cu) /* P11IV P11IFG.5 */\r
+#define P11IV_P11IFG6 (0x000Eu) /* P11IV P11IFG.6 */\r
+#define P11IV_P11IFG7 (0x0010u) /* P11IV P11IFG.7 */\r
+\r
+\r
+#endif\r
+#endif\r
+/************************************************************\r
+* DIGITAL I/O PortJ Pull up / Pull down Resistors\r
+************************************************************/\r
+#ifdef __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */\r
+\r
+#define OFS_PJIN (0x0000u) /* Port J Input */\r
+#define OFS_PJIN_L OFS_PJIN\r
+#define OFS_PJIN_H OFS_PJIN+1\r
+#define OFS_PJOUT (0x0002u) /* Port J Output */\r
+#define OFS_PJOUT_L OFS_PJOUT\r
+#define OFS_PJOUT_H OFS_PJOUT+1\r
+#define OFS_PJDIR (0x0004u) /* Port J Direction */\r
+#define OFS_PJDIR_L OFS_PJDIR\r
+#define OFS_PJDIR_H OFS_PJDIR+1\r
+#define OFS_PJREN (0x0006u) /* Port J Resistor Enable */\r
+#define OFS_PJREN_L OFS_PJREN\r
+#define OFS_PJREN_H OFS_PJREN+1\r
+#define OFS_PJSEL0 (0x000Au) /* Port J Selection 0 */\r
+#define OFS_PJSEL0_L OFS_PJSEL0\r
+#define OFS_PJSEL0_H OFS_PJSEL0+1\r
+#define OFS_PJSEL1 (0x000Cu) /* Port J Selection 1 */\r
+#define OFS_PJSEL1_L OFS_PJSEL1\r
+#define OFS_PJSEL1_H OFS_PJSEL1+1\r
+#define OFS_PJSELC (0x0016u) /* Port J Complement Selection */\r
+#define OFS_PJSELC_L OFS_PJSELC\r
+#define OFS_PJSELC_H OFS_PJSELC+1\r
+\r
+#endif\r
+/*************************************************************\r
+* RAM Control Module for FRAM\r
+*************************************************************/\r
+#ifdef __MSP430_HAS_RC_FRAM__ /* Definition to show that Module is available */\r
+\r
+#define OFS_RCCTL0 (0x0000u) /* Ram Controller Control Register */\r
+#define OFS_RCCTL0_L OFS_RCCTL0\r
+#define OFS_RCCTL0_H OFS_RCCTL0+1\r
+\r
+/* RCCTL0 Control Bits */\r
+#define RCRS0OFF0 (0x0001u) /* RAM Controller RAM Sector 0 Off Bit: 0 */\r
+#define RCRS0OFF1 (0x0002u) /* RAM Controller RAM Sector 0 Off Bit: 1 */\r
+#define RCRS4OFF0 (0x0100u) /* RAM Controller RAM Sector 4 Off Bit: 0 */\r
+#define RCRS4OFF1 (0x0200u) /* RAM Controller RAM Sector 4 Off Bit: 1 */\r
+#define RCRS5OFF0 (0x0400u) /* RAM Controller RAM Sector 5 Off Bit: 0 */\r
+#define RCRS5OFF1 (0x0800u) /* RAM Controller RAM Sector 5 Off Bit: 1 */\r
+#define RCRS6OFF0 (0x1000u) /* RAM Controller RAM Sector 6 Off Bit: 0 */\r
+#define RCRS6OFF1 (0x2000u) /* RAM Controller RAM Sector 6 Off Bit: 1 */\r
+#define RCRS7OFF0 (0x4000u) /* RAM Controller RAM Sector 7 (USB) Off Bit: 0 */\r
+#define RCRS7OFF1 (0x8000u) /* RAM Controller RAM Sector 7 (USB) Off Bit: 1 */\r
+\r
+/* RCCTL0 Control Bits */\r
+#define RCRS0OFF0_L (0x0001u) /* RAM Controller RAM Sector 0 Off Bit: 0 */\r
+#define RCRS0OFF1_L (0x0002u) /* RAM Controller RAM Sector 0 Off Bit: 1 */\r
+\r
+/* RCCTL0 Control Bits */\r
+#define RCRS4OFF0_H (0x0001u) /* RAM Controller RAM Sector 4 Off Bit: 0 */\r
+#define RCRS4OFF1_H (0x0002u) /* RAM Controller RAM Sector 4 Off Bit: 1 */\r
+#define RCRS5OFF0_H (0x0004u) /* RAM Controller RAM Sector 5 Off Bit: 0 */\r
+#define RCRS5OFF1_H (0x0008u) /* RAM Controller RAM Sector 5 Off Bit: 1 */\r
+#define RCRS6OFF0_H (0x0010u) /* RAM Controller RAM Sector 6 Off Bit: 0 */\r
+#define RCRS6OFF1_H (0x0020u) /* RAM Controller RAM Sector 6 Off Bit: 1 */\r
+#define RCRS7OFF0_H (0x0040u) /* RAM Controller RAM Sector 7 (USB) Off Bit: 0 */\r
+#define RCRS7OFF1_H (0x0080u) /* RAM Controller RAM Sector 7 (USB) Off Bit: 1 */\r
+\r
+#define RCKEY (0x5A00u)\r
+\r
+#define RCRS0OFF_0 (0x0000u) /* RAM Controller RAM Sector 0 Off : 0 */\r
+#define RCRS0OFF_1 (0x0001u) /* RAM Controller RAM Sector 0 Off : 1 */\r
+#define RCRS0OFF_2 (0x0002u) /* RAM Controller RAM Sector 0 Off : 2 */\r
+#define RCRS0OFF_3 (0x0003u) /* RAM Controller RAM Sector 0 Off : 3 */\r
+#define RCRS4OFF_0 (0x0000u) /* RAM Controller RAM Sector 4 Off : 0 */\r
+#define RCRS4OFF_2 (0x0100u) /* RAM Controller RAM Sector 4 Off : 1 */\r
+#define RCRS4OFF_3 (0x0200u) /* RAM Controller RAM Sector 4 Off : 2 */\r
+#define RCRS4OFF_4 (0x0300u) /* RAM Controller RAM Sector 4 Off : 3 */\r
+#define RCRS5OFF_0 (0x0000u) /* RAM Controller RAM Sector 5 Off : 0 */\r
+#define RCRS5OFF_1 (0x0400u) /* RAM Controller RAM Sector 5 Off : 1 */\r
+#define RCRS5OFF_2 (0x0800u) /* RAM Controller RAM Sector 5 Off : 2 */\r
+#define RCRS5OFF_3 (0x0C00u) /* RAM Controller RAM Sector 5 Off : 3 */\r
+#define RCRS6OFF_0 (0x0000u) /* RAM Controller RAM Sector 6 Off : 0 */\r
+#define RCRS6OFF_1 (0x0100u) /* RAM Controller RAM Sector 6 Off : 1 */\r
+#define RCRS6OFF_2 (0x0200u) /* RAM Controller RAM Sector 6 Off : 2 */\r
+#define RCRS6OFF_3 (0x0300u) /* RAM Controller RAM Sector 6 Off : 3 */\r
+#define RCRS7OFF_0 (0x0000u) /* RAM Controller RAM Sector 7 Off : 0 */\r
+#define RCRS7OFF_1 (0x4000u) /* RAM Controller RAM Sector 7 Off : 1 */\r
+#define RCRS7OFF_2 (0x8000u) /* RAM Controller RAM Sector 7 Off : 2*/\r
+#define RCRS7OFF_3 (0xC000u) /* RAM Controller RAM Sector 7 Off : 3*/\r
+\r
+#endif\r
+/************************************************************\r
+* Shared Reference\r
+************************************************************/\r
+#ifdef __MSP430_HAS_REF_A__ /* Definition to show that Module is available */\r
+\r
+#define OFS_REFCTL0 (0x0000u) /* REF Shared Reference control register 0 */\r
+#define OFS_REFCTL0_L OFS_REFCTL0\r
+#define OFS_REFCTL0_H OFS_REFCTL0+1\r
+\r
+/* REFCTL0 Control Bits */\r
+#define REFON (0x0001u) /* REF Reference On */\r
+#define REFOUT (0x0002u) /* REF Reference output Buffer On */\r
+//#define RESERVED (0x0004u) /* Reserved */\r
+#define REFTCOFF (0x0008u) /* REF Temp.Sensor off */\r
+#define REFVSEL0 (0x0010u) /* REF Reference Voltage Level Select Bit:0 */\r
+#define REFVSEL1 (0x0020u) /* REF Reference Voltage Level Select Bit:1 */\r
+#define REFGENOT (0x0040u) /* REF Reference generator one-time trigger */\r
+#define REFBGOT (0x0080u) /* REF Bandgap and bandgap buffer one-time trigger */\r
+#define REFGENACT (0x0100u) /* REF Reference generator active */\r
+#define REFBGACT (0x0200u) /* REF Reference bandgap active */\r
+#define REFGENBUSY (0x0400u) /* REF Reference generator busy */\r
+#define BGMODE (0x0800u) /* REF Bandgap mode */\r
+#define REFGENRDY (0x1000u) /* REF Reference generator ready */\r
+#define REFBGRDY (0x2000u) /* REF Reference bandgap ready */\r
+//#define RESERVED (0x4000u) /* Reserved */\r
+//#define RESERVED (0x8000u) /* Reserved */\r
+\r
+/* REFCTL0 Control Bits */\r
+#define REFON_L (0x0001u) /* REF Reference On */\r
+#define REFOUT_L (0x0002u) /* REF Reference output Buffer On */\r
+//#define RESERVED (0x0004u) /* Reserved */\r
+#define REFTCOFF_L (0x0008u) /* REF Temp.Sensor off */\r
+#define REFVSEL0_L (0x0010u) /* REF Reference Voltage Level Select Bit:0 */\r
+#define REFVSEL1_L (0x0020u) /* REF Reference Voltage Level Select Bit:1 */\r
+#define REFGENOT_L (0x0040u) /* REF Reference generator one-time trigger */\r
+#define REFBGOT_L (0x0080u) /* REF Bandgap and bandgap buffer one-time trigger */\r
+//#define RESERVED (0x4000u) /* Reserved */\r
+//#define RESERVED (0x8000u) /* Reserved */\r
+\r
+/* REFCTL0 Control Bits */\r
+//#define RESERVED (0x0004u) /* Reserved */\r
+#define REFGENACT_H (0x0001u) /* REF Reference generator active */\r
+#define REFBGACT_H (0x0002u) /* REF Reference bandgap active */\r
+#define REFGENBUSY_H (0x0004u) /* REF Reference generator busy */\r
+#define BGMODE_H (0x0008u) /* REF Bandgap mode */\r
+#define REFGENRDY_H (0x0010u) /* REF Reference generator ready */\r
+#define REFBGRDY_H (0x0020u) /* REF Reference bandgap ready */\r
+//#define RESERVED (0x4000u) /* Reserved */\r
+//#define RESERVED (0x8000u) /* Reserved */\r
+\r
+#define REFVSEL_0 (0x0000u) /* REF Reference Voltage Level Select 1.2V */\r
+#define REFVSEL_1 (0x0010u) /* REF Reference Voltage Level Select 2.0V */\r
+#define REFVSEL_2 (0x0020u) /* REF Reference Voltage Level Select 2.5V */\r
+#define REFVSEL_3 (0x0030u) /* REF Reference Voltage Level Select 2.5V */\r
+\r
+#endif\r
+/************************************************************\r
+* Real Time Clock\r
+************************************************************/\r
+#ifdef __MSP430_HAS_RTC_B__ /* Definition to show that Module is available */\r
+\r
+#define OFS_RTCCTL01 (0x0000u) /* Real Timer Control 0/1 */\r
+#define OFS_RTCCTL01_L OFS_RTCCTL01\r
+#define OFS_RTCCTL01_H OFS_RTCCTL01+1\r
+#define OFS_RTCCTL23 (0x0002u) /* Real Timer Control 2/3 */\r
+#define OFS_RTCCTL23_L OFS_RTCCTL23\r
+#define OFS_RTCCTL23_H OFS_RTCCTL23+1\r
+#define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */\r
+#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL\r
+#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1\r
+#define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */\r
+#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL\r
+#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1\r
+#define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */\r
+#define OFS_RTCPS_L OFS_RTCPS\r
+#define OFS_RTCPS_H OFS_RTCPS+1\r
+#define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */\r
+#define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */\r
+#define OFS_RTCTIM0_L OFS_RTCTIM0\r
+#define OFS_RTCTIM0_H OFS_RTCTIM0+1\r
+#define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */\r
+#define OFS_RTCTIM1_L OFS_RTCTIM1\r
+#define OFS_RTCTIM1_H OFS_RTCTIM1+1\r
+#define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */\r
+#define OFS_RTCDATE_L OFS_RTCDATE\r
+#define OFS_RTCDATE_H OFS_RTCDATE+1\r
+#define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */\r
+#define OFS_RTCYEAR_L OFS_RTCYEAR\r
+#define OFS_RTCYEAR_H OFS_RTCYEAR+1\r
+#define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */\r
+#define OFS_RTCAMINHR_L OFS_RTCAMINHR\r
+#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1\r
+#define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */\r
+#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY\r
+#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1\r
+#define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */\r
+#define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */\r
+#define OFS_RTCSEC (0x0010u)\r
+#define OFS_RTCMIN (0x0011u)\r
+#define OFS_RTCHOUR (0x0012u)\r
+#define OFS_RTCDOW (0x0013u)\r
+#define OFS_RTCDAY (0x0014u)\r
+#define OFS_RTCMON (0x0015u)\r
+#define OFS_RTCAMIN (0x0018u)\r
+#define OFS_RTCAHOUR (0x0019u)\r
+#define OFS_RTCADOW (0x001Au)\r
+#define OFS_RTCADAY (0x001Bu)\r
+\r
+#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */\r
+#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */\r
+#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */\r
+#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */\r
+#define RTCNT12 RTCTIM0\r
+#define RTCNT34 RTCTIM1\r
+#define RTCNT1 RTCTIM0_L\r
+#define RTCNT2 RTCTIM0_H\r
+#define RTCNT3 RTCTIM1_L\r
+#define RTCNT4 RTCTIM1_H\r
+#define RTCSEC RTCTIM0_L\r
+#define RTCMIN RTCTIM0_H\r
+#define RTCHOUR RTCTIM1_L\r
+#define RTCDOW RTCTIM1_H\r
+#define RTCDAY RTCDATE_L\r
+#define RTCMON RTCDATE_H\r
+#define RTCYEARL RTCYEAR_L\r
+#define RTCYEARH RTCYEAR_H\r
+#define RT0PS RTCPS_L\r
+#define RT1PS RTCPS_H\r
+#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */\r
+#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */\r
+#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */\r
+#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */\r
+\r
+/* RTCCTL01 Control Bits */\r
+#define RTCBCD (0x8000u) /* RTC BCD 0:Binary / 1:BCD */\r
+#define RTCHOLD (0x4000u) /* RTC Hold */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+#define RTCRDY (0x1000u) /* RTC Ready */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+#define RTCTEV1 (0x0200u) /* RTC Time Event 1 */\r
+#define RTCTEV0 (0x0100u) /* RTC Time Event 0 */\r
+#define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
+#define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */\r
+#define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */\r
+#define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */\r
+#define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
+#define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */\r
+#define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */\r
+#define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */\r
+\r
+/* RTCCTL01 Control Bits */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+#define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
+#define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */\r
+#define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */\r
+#define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */\r
+#define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
+#define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */\r
+#define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */\r
+#define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */\r
+\r
+/* RTCCTL01 Control Bits */\r
+#define RTCBCD_H (0x0080u) /* RTC BCD 0:Binary / 1:BCD */\r
+#define RTCHOLD_H (0x0040u) /* RTC Hold */\r
+//#define RESERVED (0x2000u) /* RESERVED */\r
+#define RTCRDY_H (0x0010u) /* RTC Ready */\r
+//#define RESERVED (0x0800u) /* RESERVED */\r
+//#define RESERVED (0x0400u) /* RESERVED */\r
+#define RTCTEV1_H (0x0002u) /* RTC Time Event 1 */\r
+#define RTCTEV0_H (0x0001u) /* RTC Time Event 0 */\r
+\r
+#define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */\r
+#define RTCTEV_1 (0x0100u) /* RTC Time Event: 1 (Hour changed) */\r
+#define RTCTEV_2 (0x0200u) /* RTC Time Event: 2 (12:00 changed) */\r
+#define RTCTEV_3 (0x0300u) /* RTC Time Event: 3 (00:00 changed) */\r
+#define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */\r
+#define RTCTEV__HOUR (0x0100u) /* RTC Time Event: 1 (Hour changed) */\r
+#define RTCTEV__0000 (0x0200u) /* RTC Time Event: 2 (00:00 changed) */\r
+#define RTCTEV__1200 (0x0300u) /* RTC Time Event: 3 (12:00 changed) */\r
+\r
+/* RTCCTL23 Control Bits */\r
+#define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */\r
+#define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */\r
+#define RTCCALS (0x0080u) /* RTC Calibration Sign */\r
+//#define Reserved (0x0040u)\r
+#define RTCCAL5 (0x0020u) /* RTC Calibration Bit 5 */\r
+#define RTCCAL4 (0x0010u) /* RTC Calibration Bit 4 */\r
+#define RTCCAL3 (0x0008u) /* RTC Calibration Bit 3 */\r
+#define RTCCAL2 (0x0004u) /* RTC Calibration Bit 2 */\r
+#define RTCCAL1 (0x0002u) /* RTC Calibration Bit 1 */\r
+#define RTCCAL0 (0x0001u) /* RTC Calibration Bit 0 */\r
+\r
+/* RTCCTL23 Control Bits */\r
+#define RTCCALS_L (0x0080u) /* RTC Calibration Sign */\r
+//#define Reserved (0x0040u)\r
+#define RTCCAL5_L (0x0020u) /* RTC Calibration Bit 5 */\r
+#define RTCCAL4_L (0x0010u) /* RTC Calibration Bit 4 */\r
+#define RTCCAL3_L (0x0008u) /* RTC Calibration Bit 3 */\r
+#define RTCCAL2_L (0x0004u) /* RTC Calibration Bit 2 */\r
+#define RTCCAL1_L (0x0002u) /* RTC Calibration Bit 1 */\r
+#define RTCCAL0_L (0x0001u) /* RTC Calibration Bit 0 */\r
+\r
+/* RTCCTL23 Control Bits */\r
+#define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */\r
+#define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */\r
+//#define Reserved (0x0040u)\r
+\r
+#define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */\r
+#define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */\r
+#define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */\r
+#define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */\r
+\r
+#define RTCAE (0x80) /* Real Time Clock Alarm enable */\r
+\r
+/* RTCPS0CTL Control Bits */\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+#define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
+#define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
+#define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
+#define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
+#define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */\r
+\r
+/* RTCPS0CTL Control Bits */\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+#define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
+#define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
+#define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
+#define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
+#define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */\r
+\r
+#define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */\r
+#define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */\r
+#define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */\r
+#define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */\r
+#define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */\r
+#define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */\r
+#define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */\r
+#define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */\r
+\r
+#define RT0IP__2 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */\r
+#define RT0IP__4 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */\r
+#define RT0IP__8 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */\r
+#define RT0IP__16 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */\r
+#define RT0IP__32 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */\r
+#define RT0IP__64 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */\r
+#define RT0IP__128 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */\r
+#define RT0IP__256 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */\r
+\r
+/* RTCPS1CTL Control Bits */\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+#define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
+#define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
+#define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
+#define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
+#define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */\r
+\r
+/* RTCPS1CTL Control Bits */\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+#define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
+#define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
+#define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
+#define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
+#define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */\r
+\r
+#define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */\r
+#define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */\r
+#define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */\r
+#define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */\r
+#define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */\r
+#define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */\r
+#define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */\r
+#define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */\r
+\r
+#define RT1IP__2 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */\r
+#define RT1IP__4 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */\r
+#define RT1IP__8 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */\r
+#define RT1IP__16 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */\r
+#define RT1IP__32 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */\r
+#define RT1IP__64 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */\r
+#define RT1IP__128 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */\r
+#define RT1IP__256 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */\r
+\r
+/* RTC Definitions */\r
+#define RTCIV_NONE (0x0000u) /* No Interrupt pending */\r
+#define RTCIV_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */\r
+#define RTCIV_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */\r
+#define RTCIV_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */\r
+#define RTCIV_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */\r
+#define RTCIV_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */\r
+#define RTCIV_RTCOFIFG (0x000Cu) /* RTC Oscillator fault */\r
+\r
+/* Legacy Definitions */\r
+#define RTC_NONE (0x0000u) /* No Interrupt pending */\r
+#define RTC_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */\r
+#define RTC_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */\r
+#define RTC_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */\r
+#define RTC_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */\r
+#define RTC_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */\r
+#define RTC_RTCOFIFG (0x000Cu) /* RTC Oscillator fault */\r
+\r
+#endif\r
+/************************************************************\r
+* Real Time Clock\r
+************************************************************/\r
+#ifdef __MSP430_HAS_RTC_C__ /* Definition to show that Module is available */\r
+\r
+#define OFS_RTCCTL0 (0x0000u) /* Real Timer Clock Control 0/Key */\r
+#define OFS_RTCCTL0_L OFS_RTCCTL0\r
+#define OFS_RTCCTL0_H OFS_RTCCTL0+1\r
+#define OFS_RTCCTL13 (0x0002u) /* Real Timer Clock Control 1/3 */\r
+#define OFS_RTCCTL13_L OFS_RTCCTL13\r
+#define OFS_RTCCTL13_H OFS_RTCCTL13+1\r
+#define RTCCTL1 RTCCTL13_L\r
+#define RTCCTL3 RTCCTL13_H\r
+#define OFS_RTCOCAL (0x0004u) /* Real Timer Clock Offset Calibartion */\r
+#define OFS_RTCOCAL_L OFS_RTCOCAL\r
+#define OFS_RTCOCAL_H OFS_RTCOCAL+1\r
+#define OFS_RTCTCMP (0x0006u) /* Real Timer Temperature Compensation */\r
+#define OFS_RTCTCMP_L OFS_RTCTCMP\r
+#define OFS_RTCTCMP_H OFS_RTCTCMP+1\r
+#define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */\r
+#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL\r
+#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1\r
+#define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */\r
+#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL\r
+#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1\r
+#define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */\r
+#define OFS_RTCPS_L OFS_RTCPS\r
+#define OFS_RTCPS_H OFS_RTCPS+1\r
+#define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */\r
+#define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */\r
+#define OFS_RTCTIM0_L OFS_RTCTIM0\r
+#define OFS_RTCTIM0_H OFS_RTCTIM0+1\r
+#define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */\r
+#define OFS_RTCTIM1_L OFS_RTCTIM1\r
+#define OFS_RTCTIM1_H OFS_RTCTIM1+1\r
+#define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */\r
+#define OFS_RTCDATE_L OFS_RTCDATE\r
+#define OFS_RTCDATE_H OFS_RTCDATE+1\r
+#define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */\r
+#define OFS_RTCYEAR_L OFS_RTCYEAR\r
+#define OFS_RTCYEAR_H OFS_RTCYEAR+1\r
+#define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */\r
+#define OFS_RTCAMINHR_L OFS_RTCAMINHR\r
+#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1\r
+#define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */\r
+#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY\r
+#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1\r
+#define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */\r
+#define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */\r
+#define OFS_RTCSEC (0x0010u)\r
+#define OFS_RTCMIN (0x0011u)\r
+#define OFS_RTCHOUR (0x0012u)\r
+#define OFS_RTCDOW (0x0013u)\r
+#define OFS_RTCDAY (0x0014u)\r
+#define OFS_RTCMON (0x0015u)\r
+#define OFS_RTCAMIN (0x0018u)\r
+#define OFS_RTCAHOUR (0x0019u)\r
+#define OFS_RTCADOW (0x001Au)\r
+#define OFS_RTCADAY (0x001Bu)\r
+\r
+#define RTCSEC RTCTIM0_L\r
+#define RTCMIN RTCTIM0_H\r
+#define RTCHOUR RTCTIM1_L\r
+#define RTCDOW RTCTIM1_H\r
+#define RTCDAY RTCDATE_L\r
+#define RTCMON RTCDATE_H\r
+#define RTCYEARL RTCYEAR_L\r
+#define RT0PS RTCPS_L\r
+#define RT1PS RTCPS_H\r
+#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */\r
+#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */\r
+#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */\r
+#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */\r
+\r
+/* RTCCTL0 Control Bits */\r
+#define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
+#define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */\r
+#define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */\r
+#define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */\r
+#define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
+#define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */\r
+#define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */\r
+#define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */\r
+\r
+/* RTCCTL0 Control Bits */\r
+#define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */\r
+#define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */\r
+#define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */\r
+#define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */\r
+#define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */\r
+#define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */\r
+#define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */\r
+#define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */\r
+\r
+#define RTCKEY (0xA500u) /* RTC Key for RTC write access */\r
+#define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */\r
+\r
+/* RTCCTL13 Control Bits */\r
+#define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */\r
+#define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */\r
+#define RTCBCD (0x0080u) /* RTC BCD 0:Binary / 1:BCD */\r
+#define RTCHOLD (0x0040u) /* RTC Hold */\r
+#define RTCMODE (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */\r
+#define RTCRDY (0x0010u) /* RTC Ready */\r
+#define RTCSSEL1 (0x0008u) /* RTC Source Select 1 */\r
+#define RTCSSEL0 (0x0004u) /* RTC Source Select 0 */\r
+#define RTCTEV1 (0x0002u) /* RTC Time Event 1 */\r
+#define RTCTEV0 (0x0001u) /* RTC Time Event 0 */\r
+\r
+/* RTCCTL13 Control Bits */\r
+#define RTCBCD_L (0x0080u) /* RTC BCD 0:Binary / 1:BCD */\r
+#define RTCHOLD_L (0x0040u) /* RTC Hold */\r
+#define RTCMODE_L (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */\r
+#define RTCRDY_L (0x0010u) /* RTC Ready */\r
+#define RTCSSEL1_L (0x0008u) /* RTC Source Select 1 */\r
+#define RTCSSEL0_L (0x0004u) /* RTC Source Select 0 */\r
+#define RTCTEV1_L (0x0002u) /* RTC Time Event 1 */\r
+#define RTCTEV0_L (0x0001u) /* RTC Time Event 0 */\r
+\r
+/* RTCCTL13 Control Bits */\r
+#define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */\r
+#define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */\r
+\r
+#define RTCSSEL_0 (0x0000u) /* RTC Source Select ACLK */\r
+#define RTCSSEL_1 (0x0004u) /* RTC Source Select SMCLK */\r
+#define RTCSSEL_2 (0x0008u) /* RTC Source Select RT1PS */\r
+#define RTCSSEL_3 (0x000Cu) /* RTC Source Select RT1PS */\r
+#define RTCSSEL__ACLK (0x0000u) /* RTC Source Select ACLK */\r
+#define RTCSSEL__SMCLK (0x0004u) /* RTC Source Select SMCLK */\r
+#define RTCSSEL__RT1PS (0x0008u) /* RTC Source Select RT1PS */\r
+\r
+#define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */\r
+#define RTCTEV_1 (0x0001u) /* RTC Time Event: 1 (Hour changed) */\r
+#define RTCTEV_2 (0x0002u) /* RTC Time Event: 2 (12:00 changed) */\r
+#define RTCTEV_3 (0x0003u) /* RTC Time Event: 3 (00:00 changed) */\r
+#define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */\r
+#define RTCTEV__HOUR (0x0001u) /* RTC Time Event: 1 (Hour changed) */\r
+#define RTCTEV__0000 (0x0002u) /* RTC Time Event: 2 (00:00 changed) */\r
+#define RTCTEV__1200 (0x0003u) /* RTC Time Event: 3 (12:00 changed) */\r
+\r
+#define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */\r
+#define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */\r
+#define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */\r
+#define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */\r
+\r
+/* RTCOCAL Control Bits */\r
+#define RTCOCALS (0x8000u) /* RTC Offset Calibration Sign */\r
+#define RTCOCAL7 (0x0080u) /* RTC Offset Calibration Bit 7 */\r
+#define RTCOCAL6 (0x0040u) /* RTC Offset Calibration Bit 6 */\r
+#define RTCOCAL5 (0x0020u) /* RTC Offset Calibration Bit 5 */\r
+#define RTCOCAL4 (0x0010u) /* RTC Offset Calibration Bit 4 */\r
+#define RTCOCAL3 (0x0008u) /* RTC Offset Calibration Bit 3 */\r
+#define RTCOCAL2 (0x0004u) /* RTC Offset Calibration Bit 2 */\r
+#define RTCOCAL1 (0x0002u) /* RTC Offset Calibration Bit 1 */\r
+#define RTCOCAL0 (0x0001u) /* RTC Offset Calibration Bit 0 */\r
+\r
+/* RTCOCAL Control Bits */\r
+#define RTCOCAL7_L (0x0080u) /* RTC Offset Calibration Bit 7 */\r
+#define RTCOCAL6_L (0x0040u) /* RTC Offset Calibration Bit 6 */\r
+#define RTCOCAL5_L (0x0020u) /* RTC Offset Calibration Bit 5 */\r
+#define RTCOCAL4_L (0x0010u) /* RTC Offset Calibration Bit 4 */\r
+#define RTCOCAL3_L (0x0008u) /* RTC Offset Calibration Bit 3 */\r
+#define RTCOCAL2_L (0x0004u) /* RTC Offset Calibration Bit 2 */\r
+#define RTCOCAL1_L (0x0002u) /* RTC Offset Calibration Bit 1 */\r
+#define RTCOCAL0_L (0x0001u) /* RTC Offset Calibration Bit 0 */\r
+\r
+/* RTCOCAL Control Bits */\r
+#define RTCOCALS_H (0x0080u) /* RTC Offset Calibration Sign */\r
+\r
+/* RTCTCMP Control Bits */\r
+#define RTCTCMPS (0x8000u) /* RTC Temperature Compensation Sign */\r
+#define RTCTCRDY (0x4000u) /* RTC Temperature compensation ready */\r
+#define RTCTCOK (0x2000u) /* RTC Temperature compensation write OK */\r
+#define RTCTCMP7 (0x0080u) /* RTC Temperature Compensation Bit 7 */\r
+#define RTCTCMP6 (0x0040u) /* RTC Temperature Compensation Bit 6 */\r
+#define RTCTCMP5 (0x0020u) /* RTC Temperature Compensation Bit 5 */\r
+#define RTCTCMP4 (0x0010u) /* RTC Temperature Compensation Bit 4 */\r
+#define RTCTCMP3 (0x0008u) /* RTC Temperature Compensation Bit 3 */\r
+#define RTCTCMP2 (0x0004u) /* RTC Temperature Compensation Bit 2 */\r
+#define RTCTCMP1 (0x0002u) /* RTC Temperature Compensation Bit 1 */\r
+#define RTCTCMP0 (0x0001u) /* RTC Temperature Compensation Bit 0 */\r
+\r
+/* RTCTCMP Control Bits */\r
+#define RTCTCMP7_L (0x0080u) /* RTC Temperature Compensation Bit 7 */\r
+#define RTCTCMP6_L (0x0040u) /* RTC Temperature Compensation Bit 6 */\r
+#define RTCTCMP5_L (0x0020u) /* RTC Temperature Compensation Bit 5 */\r
+#define RTCTCMP4_L (0x0010u) /* RTC Temperature Compensation Bit 4 */\r
+#define RTCTCMP3_L (0x0008u) /* RTC Temperature Compensation Bit 3 */\r
+#define RTCTCMP2_L (0x0004u) /* RTC Temperature Compensation Bit 2 */\r
+#define RTCTCMP1_L (0x0002u) /* RTC Temperature Compensation Bit 1 */\r
+#define RTCTCMP0_L (0x0001u) /* RTC Temperature Compensation Bit 0 */\r
+\r
+/* RTCTCMP Control Bits */\r
+#define RTCTCMPS_H (0x0080u) /* RTC Temperature Compensation Sign */\r
+#define RTCTCRDY_H (0x0040u) /* RTC Temperature compensation ready */\r
+#define RTCTCOK_H (0x0020u) /* RTC Temperature compensation write OK */\r
+\r
+#define RTCAE (0x80) /* Real Time Clock Alarm enable */\r
+\r
+/* RTCPS0CTL Control Bits */\r
+//#define Reserved (0x8000u)\r
+//#define Reserved (0x4000u)\r
+#define RT0PSDIV2 (0x2000u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */\r
+#define RT0PSDIV1 (0x1000u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */\r
+#define RT0PSDIV0 (0x0800u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */\r
+//#define Reserved (0x0400u)\r
+//#define Reserved (0x0200u)\r
+#define RT0PSHOLD (0x0100u) /* RTC Prescale Timer 0 Hold */\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+#define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
+#define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
+#define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
+#define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
+#define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */\r
+\r
+/* RTCPS0CTL Control Bits */\r
+//#define Reserved (0x8000u)\r
+//#define Reserved (0x4000u)\r
+//#define Reserved (0x0400u)\r
+//#define Reserved (0x0200u)\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+#define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */\r
+#define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */\r
+#define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */\r
+#define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */\r
+#define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */\r
+\r
+/* RTCPS0CTL Control Bits */\r
+//#define Reserved (0x8000u)\r
+//#define Reserved (0x4000u)\r
+#define RT0PSDIV2_H (0x0020u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */\r
+#define RT0PSDIV1_H (0x0010u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */\r
+#define RT0PSDIV0_H (0x0008u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */\r
+//#define Reserved (0x0400u)\r
+//#define Reserved (0x0200u)\r
+#define RT0PSHOLD_H (0x0001u) /* RTC Prescale Timer 0 Hold */\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+\r
+#define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */\r
+#define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */\r
+#define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */\r
+#define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */\r
+#define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */\r
+#define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */\r
+#define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */\r
+#define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */\r
+\r
+/* RTCPS1CTL Control Bits */\r
+#define RT1SSEL1 (0x8000u) /* RTC Prescale Timer 1 Source Select Bit 1 */\r
+#define RT1SSEL0 (0x4000u) /* RTC Prescale Timer 1 Source Select Bit 0 */\r
+#define RT1PSDIV2 (0x2000u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */\r
+#define RT1PSDIV1 (0x1000u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */\r
+#define RT1PSDIV0 (0x0800u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */\r
+//#define Reserved (0x0400u)\r
+//#define Reserved (0x0200u)\r
+#define RT1PSHOLD (0x0100u) /* RTC Prescale Timer 1 Hold */\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+#define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
+#define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
+#define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
+#define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
+#define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */\r
+\r
+/* RTCPS1CTL Control Bits */\r
+//#define Reserved (0x0400u)\r
+//#define Reserved (0x0200u)\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+#define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */\r
+#define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */\r
+#define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */\r
+#define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */\r
+#define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */\r
+\r
+/* RTCPS1CTL Control Bits */\r
+#define RT1SSEL1_H (0x0080u) /* RTC Prescale Timer 1 Source Select Bit 1 */\r
+#define RT1SSEL0_H (0x0040u) /* RTC Prescale Timer 1 Source Select Bit 0 */\r
+#define RT1PSDIV2_H (0x0020u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */\r
+#define RT1PSDIV1_H (0x0010u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */\r
+#define RT1PSDIV0_H (0x0008u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */\r
+//#define Reserved (0x0400u)\r
+//#define Reserved (0x0200u)\r
+#define RT1PSHOLD_H (0x0001u) /* RTC Prescale Timer 1 Hold */\r
+//#define Reserved (0x0080u)\r
+//#define Reserved (0x0040u)\r
+//#define Reserved (0x0020u)\r
+\r
+#define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */\r
+#define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */\r
+#define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */\r
+#define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */\r
+#define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */\r
+#define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */\r
+#define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */\r
+#define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */\r
+\r
+/* RTC Definitions */\r
+#define RTCIV_NONE (0x0000u) /* No Interrupt pending */\r
+#define RTCIV_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */\r
+#define RTCIV_RTCRDYIFG (0x0004u) /* RTC ready: RTCRDYIFG */\r
+#define RTCIV_RTCTEVIFG (0x0006u) /* RTC interval timer: RTCTEVIFG */\r
+#define RTCIV_RTCAIFG (0x0008u) /* RTC user alarm: RTCAIFG */\r
+#define RTCIV_RT0PSIFG (0x000Au) /* RTC prescaler 0: RT0PSIFG */\r
+#define RTCIV_RT1PSIFG (0x000Cu) /* RTC prescaler 1: RT1PSIFG */\r
+\r
+/* Legacy Definitions */\r
+#define RTC_NONE (0x0000u) /* No Interrupt pending */\r
+#define RTC_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */\r
+#define RTC_RTCRDYIFG (0x0004u) /* RTC ready: RTCRDYIFG */\r
+#define RTC_RTCTEVIFG (0x0006u) /* RTC interval timer: RTCTEVIFG */\r
+#define RTC_RTCAIFG (0x0008u) /* RTC user alarm: RTCAIFG */\r
+#define RTC_RT0PSIFG (0x000Au) /* RTC prescaler 0: RT0PSIFG */\r
+#define RTC_RT1PSIFG (0x000Cu) /* RTC prescaler 1: RT1PSIFG */\r
+\r
+#endif\r
+/************************************************************\r
+* SFR - Special Function Register Module\r
+************************************************************/\r
+#ifdef __MSP430_HAS_SFR__ /* Definition to show that Module is available */\r
+\r
+#define OFS_SFRIE1 (0x0000u) /* Interrupt Enable 1 */\r
+#define OFS_SFRIE1_L OFS_SFRIE1\r
+#define OFS_SFRIE1_H OFS_SFRIE1+1\r
+\r
+/* SFRIE1 Control Bits */\r
+#define WDTIE (0x0001u) /* WDT Interrupt Enable */\r
+#define OFIE (0x0002u) /* Osc Fault Enable */\r
+//#define Reserved (0x0004u)\r
+#define VMAIE (0x0008u) /* Vacant Memory Interrupt Enable */\r
+#define NMIIE (0x0010u) /* NMI Interrupt Enable */\r
+#define JMBINIE (0x0040u) /* JTAG Mail Box input Interrupt Enable */\r
+#define JMBOUTIE (0x0080u) /* JTAG Mail Box output Interrupt Enable */\r
+\r
+#define WDTIE_L (0x0001u) /* WDT Interrupt Enable */\r
+#define OFIE_L (0x0002u) /* Osc Fault Enable */\r
+//#define Reserved (0x0004u)\r
+#define VMAIE_L (0x0008u) /* Vacant Memory Interrupt Enable */\r
+#define NMIIE_L (0x0010u) /* NMI Interrupt Enable */\r
+#define JMBINIE_L (0x0040u) /* JTAG Mail Box input Interrupt Enable */\r
+#define JMBOUTIE_L (0x0080u) /* JTAG Mail Box output Interrupt Enable */\r
+\r
+#define OFS_SFRIFG1 (0x0002u) /* Interrupt Flag 1 */\r
+#define OFS_SFRIFG1_L OFS_SFRIFG1\r
+#define OFS_SFRIFG1_H OFS_SFRIFG1+1\r
+/* SFRIFG1 Control Bits */\r
+#define WDTIFG (0x0001u) /* WDT Interrupt Flag */\r
+#define OFIFG (0x0002u) /* Osc Fault Flag */\r
+//#define Reserved (0x0004u)\r
+#define VMAIFG (0x0008u) /* Vacant Memory Interrupt Flag */\r
+#define NMIIFG (0x0010u) /* NMI Interrupt Flag */\r
+//#define Reserved (0x0020u)\r
+#define JMBINIFG (0x0040u) /* JTAG Mail Box input Interrupt Flag */\r
+#define JMBOUTIFG (0x0080u) /* JTAG Mail Box output Interrupt Flag */\r
+\r
+#define WDTIFG_L (0x0001u) /* WDT Interrupt Flag */\r
+#define OFIFG_L (0x0002u) /* Osc Fault Flag */\r
+//#define Reserved (0x0004u)\r
+#define VMAIFG_L (0x0008u) /* Vacant Memory Interrupt Flag */\r
+#define NMIIFG_L (0x0010u) /* NMI Interrupt Flag */\r
+//#define Reserved (0x0020u)\r
+#define JMBINIFG_L (0x0040u) /* JTAG Mail Box input Interrupt Flag */\r
+#define JMBOUTIFG_L (0x0080u) /* JTAG Mail Box output Interrupt Flag */\r
+\r
+#define OFS_SFRRPCR (0x0004u) /* RESET Pin Control Register */\r
+#define OFS_SFRRPCR_L OFS_SFRRPCR\r
+#define OFS_SFRRPCR_H OFS_SFRRPCR+1\r
+/* SFRRPCR Control Bits */\r
+#define SYSNMI (0x0001u) /* NMI select */\r
+#define SYSNMIIES (0x0002u) /* NMI edge select */\r
+#define SYSRSTUP (0x0004u) /* RESET Pin pull down/up select */\r
+#define SYSRSTRE (0x0008u) /* RESET Pin Resistor enable */\r
+\r
+#define SYSNMI_L (0x0001u) /* NMI select */\r
+#define SYSNMIIES_L (0x0002u) /* NMI edge select */\r
+#define SYSRSTUP_L (0x0004u) /* RESET Pin pull down/up select */\r
+#define SYSRSTRE_L (0x0008u) /* RESET Pin Resistor enable */\r
+\r
+#endif\r
+/************************************************************\r
+* SYS - System Module\r
+************************************************************/\r
+#ifdef __MSP430_HAS_SYS__ /* Definition to show that Module is available */\r
+\r
+#define OFS_SYSCTL (0x0000u) /* System control */\r
+#define OFS_SYSCTL_L OFS_SYSCTL\r
+#define OFS_SYSCTL_H OFS_SYSCTL+1\r
+#define OFS_SYSBSLC (0x0002u) /* Boot strap configuration area */\r
+#define OFS_SYSBSLC_L OFS_SYSBSLC\r
+#define OFS_SYSBSLC_H OFS_SYSBSLC+1\r
+#define OFS_SYSJMBC (0x0006u) /* JTAG mailbox control */\r
+#define OFS_SYSJMBC_L OFS_SYSJMBC\r
+#define OFS_SYSJMBC_H OFS_SYSJMBC+1\r
+#define OFS_SYSJMBI0 (0x0008u) /* JTAG mailbox input 0 */\r
+#define OFS_SYSJMBI0_L OFS_SYSJMBI0\r
+#define OFS_SYSJMBI0_H OFS_SYSJMBI0+1\r
+#define OFS_SYSJMBI1 (0x000Au) /* JTAG mailbox input 1 */\r
+#define OFS_SYSJMBI1_L OFS_SYSJMBI1\r
+#define OFS_SYSJMBI1_H OFS_SYSJMBI1+1\r
+#define OFS_SYSJMBO0 (0x000Cu) /* JTAG mailbox output 0 */\r
+#define OFS_SYSJMBO0_L OFS_SYSJMBO0\r
+#define OFS_SYSJMBO0_H OFS_SYSJMBO0+1\r
+#define OFS_SYSJMBO1 (0x000Eu) /* JTAG mailbox output 1 */\r
+#define OFS_SYSJMBO1_L OFS_SYSJMBO1\r
+#define OFS_SYSJMBO1_H OFS_SYSJMBO1+1\r
+\r
+#define OFS_SYSBERRIV (0x0018u) /* Bus Error vector generator */\r
+#define OFS_SYSBERRIV_L OFS_SYSBERRIV\r
+#define OFS_SYSBERRIV_H OFS_SYSBERRIV+1\r
+#define OFS_SYSUNIV (0x001Au) /* User NMI vector generator */\r
+#define OFS_SYSUNIV_L OFS_SYSUNIV\r
+#define OFS_SYSUNIV_H OFS_SYSUNIV+1\r
+#define OFS_SYSSNIV (0x001Cu) /* System NMI vector generator */\r
+#define OFS_SYSSNIV_L OFS_SYSSNIV\r
+#define OFS_SYSSNIV_H OFS_SYSSNIV+1\r
+#define OFS_SYSRSTIV (0x001Eu) /* Reset vector generator */\r
+#define OFS_SYSRSTIV_L OFS_SYSRSTIV\r
+#define OFS_SYSRSTIV_H OFS_SYSRSTIV+1\r
+\r
+/* SYSCTL Control Bits */\r
+#define SYSRIVECT (0x0001u) /* SYS - RAM based interrupt vectors */\r
+//#define RESERVED (0x0002u) /* SYS - Reserved */\r
+#define SYSPMMPE (0x0004u) /* SYS - PMM access protect */\r
+//#define RESERVED (0x0008u) /* SYS - Reserved */\r
+#define SYSBSLIND (0x0010u) /* SYS - TCK/RST indication detected */\r
+#define SYSJTAGPIN (0x0020u) /* SYS - Dedicated JTAG pins enabled */\r
+//#define RESERVED (0x0040u) /* SYS - Reserved */\r
+//#define RESERVED (0x0080u) /* SYS - Reserved */\r
+//#define RESERVED (0x0100u) /* SYS - Reserved */\r
+//#define RESERVED (0x0200u) /* SYS - Reserved */\r
+//#define RESERVED (0x0400u) /* SYS - Reserved */\r
+//#define RESERVED (0x0800u) /* SYS - Reserved */\r
+//#define RESERVED (0x1000u) /* SYS - Reserved */\r
+//#define RESERVED (0x2000u) /* SYS - Reserved */\r
+//#define RESERVED (0x4000u) /* SYS - Reserved */\r
+//#define RESERVED (0x8000u) /* SYS - Reserved */\r
+\r
+/* SYSCTL Control Bits */\r
+#define SYSRIVECT_L (0x0001u) /* SYS - RAM based interrupt vectors */\r
+//#define RESERVED (0x0002u) /* SYS - Reserved */\r
+#define SYSPMMPE_L (0x0004u) /* SYS - PMM access protect */\r
+//#define RESERVED (0x0008u) /* SYS - Reserved */\r
+#define SYSBSLIND_L (0x0010u) /* SYS - TCK/RST indication detected */\r
+#define SYSJTAGPIN_L (0x0020u) /* SYS - Dedicated JTAG pins enabled */\r
+//#define RESERVED (0x0040u) /* SYS - Reserved */\r
+//#define RESERVED (0x0080u) /* SYS - Reserved */\r
+//#define RESERVED (0x0100u) /* SYS - Reserved */\r
+//#define RESERVED (0x0200u) /* SYS - Reserved */\r
+//#define RESERVED (0x0400u) /* SYS - Reserved */\r
+//#define RESERVED (0x0800u) /* SYS - Reserved */\r
+//#define RESERVED (0x1000u) /* SYS - Reserved */\r
+//#define RESERVED (0x2000u) /* SYS - Reserved */\r
+//#define RESERVED (0x4000u) /* SYS - Reserved */\r
+//#define RESERVED (0x8000u) /* SYS - Reserved */\r
+\r
+/* SYSBSLC Control Bits */\r
+#define SYSBSLSIZE0 (0x0001u) /* SYS - BSL Protection Size 0 */\r
+#define SYSBSLSIZE1 (0x0002u) /* SYS - BSL Protection Size 1 */\r
+#define SYSBSLR (0x0004u) /* SYS - RAM assigned to BSL */\r
+//#define RESERVED (0x0008u) /* SYS - Reserved */\r
+//#define RESERVED (0x0010u) /* SYS - Reserved */\r
+//#define RESERVED (0x0020u) /* SYS - Reserved */\r
+//#define RESERVED (0x0040u) /* SYS - Reserved */\r
+//#define RESERVED (0x0080u) /* SYS - Reserved */\r
+//#define RESERVED (0x0100u) /* SYS - Reserved */\r
+//#define RESERVED (0x0200u) /* SYS - Reserved */\r
+//#define RESERVED (0x0400u) /* SYS - Reserved */\r
+//#define RESERVED (0x0800u) /* SYS - Reserved */\r
+//#define RESERVED (0x1000u) /* SYS - Reserved */\r
+//#define RESERVED (0x2000u) /* SYS - Reserved */\r
+#define SYSBSLOFF (0x4000u) /* SYS - BSL Memory disabled */\r
+#define SYSBSLPE (0x8000u) /* SYS - BSL Memory protection enabled */\r
+\r
+/* SYSBSLC Control Bits */\r
+#define SYSBSLSIZE0_L (0x0001u) /* SYS - BSL Protection Size 0 */\r
+#define SYSBSLSIZE1_L (0x0002u) /* SYS - BSL Protection Size 1 */\r
+#define SYSBSLR_L (0x0004u) /* SYS - RAM assigned to BSL */\r
+//#define RESERVED (0x0008u) /* SYS - Reserved */\r
+//#define RESERVED (0x0010u) /* SYS - Reserved */\r
+//#define RESERVED (0x0020u) /* SYS - Reserved */\r
+//#define RESERVED (0x0040u) /* SYS - Reserved */\r
+//#define RESERVED (0x0080u) /* SYS - Reserved */\r
+//#define RESERVED (0x0100u) /* SYS - Reserved */\r
+//#define RESERVED (0x0200u) /* SYS - Reserved */\r
+//#define RESERVED (0x0400u) /* SYS - Reserved */\r
+//#define RESERVED (0x0800u) /* SYS - Reserved */\r
+//#define RESERVED (0x1000u) /* SYS - Reserved */\r
+//#define RESERVED (0x2000u) /* SYS - Reserved */\r
+\r
+/* SYSBSLC Control Bits */\r
+//#define RESERVED (0x0008u) /* SYS - Reserved */\r
+//#define RESERVED (0x0010u) /* SYS - Reserved */\r
+//#define RESERVED (0x0020u) /* SYS - Reserved */\r
+//#define RESERVED (0x0040u) /* SYS - Reserved */\r
+//#define RESERVED (0x0080u) /* SYS - Reserved */\r
+//#define RESERVED (0x0100u) /* SYS - Reserved */\r
+//#define RESERVED (0x0200u) /* SYS - Reserved */\r
+//#define RESERVED (0x0400u) /* SYS - Reserved */\r
+//#define RESERVED (0x0800u) /* SYS - Reserved */\r
+//#define RESERVED (0x1000u) /* SYS - Reserved */\r
+//#define RESERVED (0x2000u) /* SYS - Reserved */\r
+#define SYSBSLOFF_H (0x0040u) /* SYS - BSL Memory disabled */\r
+#define SYSBSLPE_H (0x0080u) /* SYS - BSL Memory protection enabled */\r
+\r
+/* SYSJMBC Control Bits */\r
+#define JMBIN0FG (0x0001u) /* SYS - Incoming JTAG Mailbox 0 Flag */\r
+#define JMBIN1FG (0x0002u) /* SYS - Incoming JTAG Mailbox 1 Flag */\r
+#define JMBOUT0FG (0x0004u) /* SYS - Outgoing JTAG Mailbox 0 Flag */\r
+#define JMBOUT1FG (0x0008u) /* SYS - Outgoing JTAG Mailbox 1 Flag */\r
+#define JMBMODE (0x0010u) /* SYS - JMB 16/32 Bit Mode */\r
+//#define RESERVED (0x0020u) /* SYS - Reserved */\r
+#define JMBCLR0OFF (0x0040u) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */\r
+#define JMBCLR1OFF (0x0080u) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */\r
+//#define RESERVED (0x0100u) /* SYS - Reserved */\r
+//#define RESERVED (0x0200u) /* SYS - Reserved */\r
+//#define RESERVED (0x0400u) /* SYS - Reserved */\r
+//#define RESERVED (0x0800u) /* SYS - Reserved */\r
+//#define RESERVED (0x1000u) /* SYS - Reserved */\r
+//#define RESERVED (0x2000u) /* SYS - Reserved */\r
+//#define RESERVED (0x4000u) /* SYS - Reserved */\r
+//#define RESERVED (0x8000u) /* SYS - Reserved */\r
+\r
+/* SYSJMBC Control Bits */\r
+#define JMBIN0FG_L (0x0001u) /* SYS - Incoming JTAG Mailbox 0 Flag */\r
+#define JMBIN1FG_L (0x0002u) /* SYS - Incoming JTAG Mailbox 1 Flag */\r
+#define JMBOUT0FG_L (0x0004u) /* SYS - Outgoing JTAG Mailbox 0 Flag */\r
+#define JMBOUT1FG_L (0x0008u) /* SYS - Outgoing JTAG Mailbox 1 Flag */\r
+#define JMBMODE_L (0x0010u) /* SYS - JMB 16/32 Bit Mode */\r
+//#define RESERVED (0x0020u) /* SYS - Reserved */\r
+#define JMBCLR0OFF_L (0x0040u) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */\r
+#define JMBCLR1OFF_L (0x0080u) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */\r
+//#define RESERVED (0x0100u) /* SYS - Reserved */\r
+//#define RESERVED (0x0200u) /* SYS - Reserved */\r
+//#define RESERVED (0x0400u) /* SYS - Reserved */\r
+//#define RESERVED (0x0800u) /* SYS - Reserved */\r
+//#define RESERVED (0x1000u) /* SYS - Reserved */\r
+//#define RESERVED (0x2000u) /* SYS - Reserved */\r
+//#define RESERVED (0x4000u) /* SYS - Reserved */\r
+//#define RESERVED (0x8000u) /* SYS - Reserved */\r
+\r
+\r
+#endif\r
+/************************************************************\r
+* Timerx_A7\r
+************************************************************/\r
+#ifdef __MSP430_HAS_TxA7__ /* Definition to show that Module is available */\r
+\r
+#define OFS_TAxCTL (0x0000u) /* Timerx_A7 Control */\r
+#define OFS_TAxCCTL0 (0x0002u) /* Timerx_A7 Capture/Compare Control 0 */\r
+#define OFS_TAxCCTL1 (0x0004u) /* Timerx_A7 Capture/Compare Control 1 */\r
+#define OFS_TAxCCTL2 (0x0006u) /* Timerx_A7 Capture/Compare Control 2 */\r
+#define OFS_TAxCCTL3 (0x0008u) /* Timerx_A7 Capture/Compare Control 3 */\r
+#define OFS_TAxCCTL4 (0x000Au) /* Timerx_A7 Capture/Compare Control 4 */\r
+#define OFS_TAxCCTL5 (0x000Cu) /* Timerx_A7 Capture/Compare Control 5 */\r
+#define OFS_TAxCCTL6 (0x000Eu) /* Timerx_A7 Capture/Compare Control 6 */\r
+#define OFS_TAxR (0x0010u) /* Timerx_A7 */\r
+#define OFS_TAxCCR0 (0x0012u) /* Timerx_A7 Capture/Compare 0 */\r
+#define OFS_TAxCCR1 (0x0014u) /* Timerx_A7 Capture/Compare 1 */\r
+#define OFS_TAxCCR2 (0x0016u) /* Timerx_A7 Capture/Compare 2 */\r
+#define OFS_TAxCCR3 (0x0018u) /* Timerx_A7 Capture/Compare 3 */\r
+#define OFS_TAxCCR4 (0x001Au) /* Timerx_A7 Capture/Compare 4 */\r
+#define OFS_TAxCCR5 (0x001Cu) /* Timerx_A7 Capture/Compare 5 */\r
+#define OFS_TAxCCR6 (0x001Eu) /* Timerx_A7 Capture/Compare 6 */\r
+#define OFS_TAxIV (0x002Eu) /* Timerx_A7 Interrupt Vector Word */\r
+#define OFS_TAxEX0 (0x0020u) /* Timerx_A7 Expansion Register 0 */\r
+\r
+/* Bits are already defined within the Timer0_Ax */\r
+\r
+/* TAxIV Definitions */\r
+#define TAxIV_NONE (0x0000u) /* No Interrupt pending */\r
+#define TAxIV_TACCR1 (0x0002u) /* TAxCCR1_CCIFG */\r
+#define TAxIV_TACCR2 (0x0004u) /* TAxCCR2_CCIFG */\r
+#define TAxIV_TACCR3 (0x0006u) /* TAxCCR3_CCIFG */\r
+#define TAxIV_TACCR4 (0x0008u) /* TAxCCR4_CCIFG */\r
+#define TAxIV_TACCR5 (0x000Au) /* TAxCCR5_CCIFG */\r
+#define TAxIV_TACCR6 (0x000Cu) /* TAxCCR6_CCIFG */\r
+#define TAxIV_TAIFG (0x000Eu) /* TAxIFG */\r
+\r
+/* Legacy Defines */\r
+#define TAxIV_TAxCCR1 (0x0002u) /* TAxCCR1_CCIFG */\r
+#define TAxIV_TAxCCR2 (0x0004u) /* TAxCCR2_CCIFG */\r
+#define TAxIV_TAxCCR3 (0x0006u) /* TAxCCR3_CCIFG */\r
+#define TAxIV_TAxCCR4 (0x0008u) /* TAxCCR4_CCIFG */\r
+#define TAxIV_TAxCCR5 (0x000Au) /* TAxCCR5_CCIFG */\r
+#define TAxIV_TAxCCR6 (0x000Cu) /* TAxCCR6_CCIFG */\r
+#define TAxIV_TAxIFG (0x000Eu) /* TAxIFG */\r
+\r
+/* TAxCTL Control Bits */\r
+#define TASSEL1 (0x0200u) /* Timer A clock source select 1 */\r
+#define TASSEL0 (0x0100u) /* Timer A clock source select 0 */\r
+#define ID1 (0x0080u) /* Timer A clock input divider 1 */\r
+#define ID0 (0x0040u) /* Timer A clock input divider 0 */\r
+#define MC1 (0x0020u) /* Timer A mode control 1 */\r
+#define MC0 (0x0010u) /* Timer A mode control 0 */\r
+#define TACLR (0x0004u) /* Timer A counter clear */\r
+#define TAIE (0x0002u) /* Timer A counter interrupt enable */\r
+#define TAIFG (0x0001u) /* Timer A counter interrupt flag */\r
+\r
+#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */\r
+#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */\r
+#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continuous up */\r
+#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */\r
+#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */\r
+#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */\r
+#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */\r
+#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */\r
+#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */\r
+#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */\r
+#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */\r
+#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */\r
+#define MC__STOP (0*0x10u) /* Timer A mode control: 0 - Stop */\r
+#define MC__UP (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */\r
+#define MC__CONTINUOUS (2*0x10u) /* Timer A mode control: 2 - Continuous up */\r
+#define MC__CONTINOUS (2*0x10u) /* Legacy define */\r
+#define MC__UPDOWN (3*0x10u) /* Timer A mode control: 3 - Up/Down */\r
+#define ID__1 (0*0x40u) /* Timer A input divider: 0 - /1 */\r
+#define ID__2 (1*0x40u) /* Timer A input divider: 1 - /2 */\r
+#define ID__4 (2*0x40u) /* Timer A input divider: 2 - /4 */\r
+#define ID__8 (3*0x40u) /* Timer A input divider: 3 - /8 */\r
+#define TASSEL__TACLK (0*0x100u) /* Timer A clock source select: 0 - TACLK */\r
+#define TASSEL__ACLK (1*0x100u) /* Timer A clock source select: 1 - ACLK */\r
+#define TASSEL__SMCLK (2*0x100u) /* Timer A clock source select: 2 - SMCLK */\r
+#define TASSEL__INCLK (3*0x100u) /* Timer A clock source select: 3 - INCLK */\r
+\r
+/* TAxCCTLx Control Bits */\r
+#define CM1 (0x8000u) /* Capture mode 1 */\r
+#define CM0 (0x4000u) /* Capture mode 0 */\r
+#define CCIS1 (0x2000u) /* Capture input select 1 */\r
+#define CCIS0 (0x1000u) /* Capture input select 0 */\r
+#define SCS (0x0800u) /* Capture sychronize */\r
+#define SCCI (0x0400u) /* Latched capture signal (read) */\r
+#define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */\r
+#define OUTMOD2 (0x0080u) /* Output mode 2 */\r
+#define OUTMOD1 (0x0040u) /* Output mode 1 */\r
+#define OUTMOD0 (0x0020u) /* Output mode 0 */\r
+#define CCIE (0x0010u) /* Capture/compare interrupt enable */\r
+#define CCI (0x0008u) /* Capture input signal (read) */\r
+#define OUT (0x0004u) /* PWM Output signal if output mode 0 */\r
+#define COV (0x0002u) /* Capture/compare overflow flag */\r
+#define CCIFG (0x0001u) /* Capture/compare interrupt flag */\r
+\r
+#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */\r
+#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */\r
+#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */\r
+#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */\r
+#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */\r
+#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */\r
+#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */\r
+#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */\r
+#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */\r
+#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */\r
+#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */\r
+#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */\r
+#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */\r
+#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */\r
+#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */\r
+#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */\r
+\r
+/* TAxEX0 Control Bits */\r
+#define TAIDEX0 (0x0001u) /* Timer A Input divider expansion Bit: 0 */\r
+#define TAIDEX1 (0x0002u) /* Timer A Input divider expansion Bit: 1 */\r
+#define TAIDEX2 (0x0004u) /* Timer A Input divider expansion Bit: 2 */\r
+\r
+#define TAIDEX_0 (0*0x0001u) /* Timer A Input divider expansion : /1 */\r
+#define TAIDEX_1 (1*0x0001u) /* Timer A Input divider expansion : /2 */\r
+#define TAIDEX_2 (2*0x0001u) /* Timer A Input divider expansion : /3 */\r
+#define TAIDEX_3 (3*0x0001u) /* Timer A Input divider expansion : /4 */\r
+#define TAIDEX_4 (4*0x0001u) /* Timer A Input divider expansion : /5 */\r
+#define TAIDEX_5 (5*0x0001u) /* Timer A Input divider expansion : /6 */\r
+#define TAIDEX_6 (6*0x0001u) /* Timer A Input divider expansion : /7 */\r
+#define TAIDEX_7 (7*0x0001u) /* Timer A Input divider expansion : /8 */\r
+\r
+#endif\r
+/************************************************************\r
+* Timerx_B7\r
+************************************************************/\r
+#ifdef __MSP430_HAS_TxB7__ /* Definition to show that Module is available */\r
+\r
+#define OFS_TBxCTL (0x0000u) /* Timerx_B7 Control */\r
+#define OFS_TBxCCTL0 (0x0002u) /* Timerx_B7 Capture/Compare Control 0 */\r
+#define OFS_TBxCCTL1 (0x0004u) /* Timerx_B7 Capture/Compare Control 1 */\r
+#define OFS_TBxCCTL2 (0x0006u) /* Timerx_B7 Capture/Compare Control 2 */\r
+#define OFS_TBxCCTL3 (0x0008u) /* Timerx_B7 Capture/Compare Control 3 */\r
+#define OFS_TBxCCTL4 (0x000Au) /* Timerx_B7 Capture/Compare Control 4 */\r
+#define OFS_TBxCCTL5 (0x000Cu) /* Timerx_B7 Capture/Compare Control 5 */\r
+#define OFS_TBxCCTL6 (0x000Eu) /* Timerx_B7 Capture/Compare Control 6 */\r
+#define OFS_TBxR (0x0010u) /* Timerx_B7 */\r
+#define OFS_TBxCCR0 (0x0012u) /* Timerx_B7 Capture/Compare 0 */\r
+#define OFS_TBxCCR1 (0x0014u) /* Timerx_B7 Capture/Compare 1 */\r
+#define OFS_TBxCCR2 (0x0016u) /* Timerx_B7 Capture/Compare 2 */\r
+#define OFS_TBxCCR3 (0x0018u) /* Timerx_B7 Capture/Compare 3 */\r
+#define OFS_TBxCCR4 (0x001Au) /* Timerx_B7 Capture/Compare 4 */\r
+#define OFS_TBxCCR5 (0x001Cu) /* Timerx_B7 Capture/Compare 5 */\r
+#define OFS_TBxCCR6 (0x001Eu) /* Timerx_B7 Capture/Compare 6 */\r
+#define OFS_TBxIV (0x002Eu) /* Timerx_B7 Interrupt Vector Word */\r
+#define OFS_TBxEX0 (0x0020u) /* Timerx_B7 Expansion Register 0 */\r
+\r
+/* Bits are already defined within the Timer0_Ax */\r
+\r
+/* TBxIV Definitions */\r
+#define TBxIV_NONE (0x0000u) /* No Interrupt pending */\r
+#define TBxIV_TBCCR1 (0x0002u) /* TBxCCR1_CCIFG */\r
+#define TBxIV_TBCCR2 (0x0004u) /* TBxCCR2_CCIFG */\r
+#define TBxIV_TBCCR3 (0x0006u) /* TBxCCR3_CCIFG */\r
+#define TBxIV_TBCCR4 (0x0008u) /* TBxCCR4_CCIFG */\r
+#define TBxIV_TBCCR5 (0x000Au) /* TBxCCR5_CCIFG */\r
+#define TBxIV_TBCCR6 (0x000Cu) /* TBxCCR6_CCIFG */\r
+#define TBxIV_TBIFG (0x000Eu) /* TBxIFG */\r
+\r
+/* Legacy Defines */\r
+#define TBxIV_TBxCCR1 (0x0002u) /* TBxCCR1_CCIFG */\r
+#define TBxIV_TBxCCR2 (0x0004u) /* TBxCCR2_CCIFG */\r
+#define TBxIV_TBxCCR3 (0x0006u) /* TBxCCR3_CCIFG */\r
+#define TBxIV_TBxCCR4 (0x0008u) /* TBxCCR4_CCIFG */\r
+#define TBxIV_TBxCCR5 (0x000Au) /* TBxCCR5_CCIFG */\r
+#define TBxIV_TBxCCR6 (0x000Cu) /* TBxCCR6_CCIFG */\r
+#define TBxIV_TBxIFG (0x000Eu) /* TBxIFG */\r
+\r
+/* TBxCTL Control Bits */\r
+#define TBCLGRP1 (0x4000u) /* Timer_B7 Compare latch load group 1 */\r
+#define TBCLGRP0 (0x2000u) /* Timer_B7 Compare latch load group 0 */\r
+#define CNTL1 (0x1000u) /* Counter lenght 1 */\r
+#define CNTL0 (0x0800u) /* Counter lenght 0 */\r
+#define TBSSEL1 (0x0200u) /* Clock source 1 */\r
+#define TBSSEL0 (0x0100u) /* Clock source 0 */\r
+#define TBCLR (0x0004u) /* Timer_B7 counter clear */\r
+#define TBIE (0x0002u) /* Timer_B7 interrupt enable */\r
+#define TBIFG (0x0001u) /* Timer_B7 interrupt flag */\r
+\r
+#define SHR1 (0x4000u) /* Timer_B7 Compare latch load group 1 */\r
+#define SHR0 (0x2000u) /* Timer_B7 Compare latch load group 0 */\r
+\r
+#define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */\r
+#define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */\r
+#define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */\r
+#define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */\r
+#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */\r
+#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */\r
+#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */\r
+#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */\r
+#define SHR_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */\r
+#define SHR_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */\r
+#define SHR_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/\r
+#define SHR_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */\r
+#define TBCLGRP_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */\r
+#define TBCLGRP_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */\r
+#define TBCLGRP_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/\r
+#define TBCLGRP_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */\r
+#define TBSSEL__TBCLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK */\r
+#define TBSSEL__TACLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */\r
+#define TBSSEL__ACLK (1*0x100u) /* Timer_B7 clock source select: 1 - ACLK */\r
+#define TBSSEL__SMCLK (2*0x100u) /* Timer_B7 clock source select: 2 - SMCLK */\r
+#define TBSSEL__INCLK (3*0x100u) /* Timer_B7 clock source select: 3 - INCLK */\r
+#define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */\r
+#define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */\r
+#define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */\r
+#define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */\r
+\r
+/* Additional Timer B Control Register bits are defined in Timer A */\r
+/* TBxCCTLx Control Bits */\r
+#define CLLD1 (0x0400u) /* Compare latch load source 1 */\r
+#define CLLD0 (0x0200u) /* Compare latch load source 0 */\r
+\r
+#define SLSHR1 (0x0400u) /* Compare latch load source 1 */\r
+#define SLSHR0 (0x0200u) /* Compare latch load source 0 */\r
+\r
+#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */\r
+#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */\r
+#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */\r
+#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */\r
+\r
+#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */\r
+#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */\r
+#define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */\r
+#define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */\r
+\r
+/* TBxEX0 Control Bits */\r
+#define TBIDEX0 (0x0001u) /* Timer_B7 Input divider expansion Bit: 0 */\r
+#define TBIDEX1 (0x0002u) /* Timer_B7 Input divider expansion Bit: 1 */\r
+#define TBIDEX2 (0x0004u) /* Timer_B7 Input divider expansion Bit: 2 */\r
+\r
+#define TBIDEX_0 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */\r
+#define TBIDEX_1 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */\r
+#define TBIDEX_2 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */\r
+#define TBIDEX_3 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */\r
+#define TBIDEX_4 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */\r
+#define TBIDEX_5 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */\r
+#define TBIDEX_6 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */\r
+#define TBIDEX_7 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */\r
+#define TBIDEX__1 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */\r
+#define TBIDEX__2 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */\r
+#define TBIDEX__3 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */\r
+#define TBIDEX__4 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */\r
+#define TBIDEX__5 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */\r
+#define TBIDEX__6 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */\r
+#define TBIDEX__7 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */\r
+#define TBIDEX__8 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */\r
+\r
+\r
+#define ID1 (0x0080u) /* Timer B clock input divider 1 */\r
+#define ID0 (0x0040u) /* Timer B clock input divider 0 */\r
+#define MC1 (0x0020u) /* Timer B mode control 1 */\r
+#define MC0 (0x0010u) /* Timer B mode control 0 */\r
+#define MC__STOP (0*0x10u) /* Timer B mode control: 0 - Stop */\r
+#define MC__UP (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */\r
+#define MC__CONTINUOUS (2*0x10u) /* Timer B mode control: 2 - Continuous up */\r
+#define MC__CONTINOUS (2*0x10u) /* Legacy define */\r
+#define MC__UPDOWN (3*0x10u) /* Timer B mode control: 3 - Up/Down */\r
+#define CM1 (0x8000u) /* Capture mode 1 */\r
+#define CM0 (0x4000u) /* Capture mode 0 */\r
+#define MC_0 (0*0x10u) /* Timer B mode control: 0 - Stop */\r
+#define MC_1 (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */\r
+#define MC_2 (2*0x10u) /* Timer B mode control: 2 - Continuous up */\r
+#define MC_3 (3*0x10u) /* Timer B mode control: 3 - Up/Down */\r
+#define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */\r
+#define CCIE (0x0010u) /* Capture/compare interrupt enable */\r
+#define CCIFG (0x0001u) /* Capture/compare interrupt flag */\r
+#define CCIS_0 (0*0x1000u)\r
+#define CCIS_1 (1*0x1000u)\r
+#define CCIS_2 (2*0x1000u)\r
+#define CCIS_3 (3*0x1000u)\r
+#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */\r
+#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */\r
+#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */\r
+#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */\r
+#define OUT (0x0004u) /* PWM Output signal if output mode 0 */\r
+#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */\r
+#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */\r
+#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */\r
+#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */\r
+#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */\r
+#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */\r
+#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */\r
+#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */\r
+#define SCCI (0x0400u) /* Latched capture signal (read) */\r
+#define SCS (0x0800u) /* Capture sychronize */\r
+#define CCI (0x0008u) /* Capture input signal (read) */\r
+#define ID__1 (0*0x40u) /* Timer B input divider: 0 - /1 */\r
+#define ID__2 (1*0x40u) /* Timer B input divider: 1 - /2 */\r
+#define ID__4 (2*0x40u) /* Timer B input divider: 2 - /4 */\r
+#define ID__8 (3*0x40u) /* Timer B input divider: 3 - /8 */\r
+#define ID_0 (0*0x40u) /* Timer B input divider: 0 - /1 */\r
+#define ID_1 (1*0x40u) /* Timer B input divider: 1 - /2 */\r
+#define ID_2 (2*0x40u) /* Timer B input divider: 2 - /4 */\r
+#define ID_3 (3*0x40u) /* Timer B input divider: 3 - /8 */\r
+\r
+#endif\r
+/************************************************************\r
+* USCI Ax\r
+************************************************************/\r
+#ifdef __MSP430_HAS_EUSCI_Ax__ /* Definition to show that Module is available */\r
+\r
+#define OFS_UCAxCTLW0 (0x0000u) /* USCI Ax Control Word Register 0 */\r
+#define OFS_UCAxCTLW0_L OFS_UCAxCTLW0\r
+#define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1\r
+#define OFS_UCAxCTL0 (0x0001u)\r
+#define OFS_UCAxCTL1 (0x0000u)\r
+#define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */\r
+#define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */\r
+#define OFS_UCAxCTLW1 (0x0002u) /* USCI Ax Control Word Register 1 */\r
+#define OFS_UCAxCTLW1_L OFS_UCAxCTLW1\r
+#define OFS_UCAxCTLW1_H OFS_UCAxCTLW1+1\r
+#define OFS_UCAxBRW (0x0006u) /* USCI Ax Baud Word Rate 0 */\r
+#define OFS_UCAxBRW_L OFS_UCAxBRW\r
+#define OFS_UCAxBRW_H OFS_UCAxBRW+1\r
+#define OFS_UCAxBR0 (0x0006u)\r
+#define OFS_UCAxBR1 (0x0007u)\r
+#define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */\r
+#define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */\r
+#define OFS_UCAxMCTLW (0x0008u) /* USCI Ax Modulation Control */\r
+#define OFS_UCAxMCTLW_L OFS_UCAxMCTLW\r
+#define OFS_UCAxMCTLW_H OFS_UCAxMCTLW+1\r
+#define OFS_UCAxSTATW (0x000Au) /* USCI Ax Status Register */\r
+#define OFS_UCAxRXBUF (0x000Cu) /* USCI Ax Receive Buffer */\r
+#define OFS_UCAxRXBUF_L OFS_UCAxRXBUF\r
+#define OFS_UCAxRXBUF_H OFS_UCAxRXBUF+1\r
+#define OFS_UCAxTXBUF (0x000Eu) /* USCI Ax Transmit Buffer */\r
+#define OFS_UCAxTXBUF_L OFS_UCAxTXBUF\r
+#define OFS_UCAxTXBUF_H OFS_UCAxTXBUF+1\r
+#define OFS_UCAxABCTL (0x0010u) /* USCI Ax LIN Control */\r
+#define OFS_UCAxIRCTL (0x0012u) /* USCI Ax IrDA Transmit Control */\r
+#define OFS_UCAxIRCTL_L OFS_UCAxIRCTL\r
+#define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1\r
+#define OFS_UCAxIRTCTL (0x0012u)\r
+#define OFS_UCAxIRRCTL (0x0013u)\r
+#define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */\r
+#define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */\r
+#define OFS_UCAxIE (0x001Au) /* USCI Ax Interrupt Enable Register */\r
+#define OFS_UCAxIE_L OFS_UCAxIE\r
+#define OFS_UCAxIE_H OFS_UCAxIE+1\r
+#define OFS_UCAxIFG (0x001Cu) /* USCI Ax Interrupt Flags Register */\r
+#define OFS_UCAxIFG_L OFS_UCAxIFG\r
+#define OFS_UCAxIFG_H OFS_UCAxIFG+1\r
+#define OFS_UCAxIE__UART (0x001Au)\r
+#define OFS_UCAxIE__UART_L OFS_UCAxIE__UART\r
+#define OFS_UCAxIE__UART_H OFS_UCAxIE__UART+1\r
+#define OFS_UCAxIFG__UART (0x001Cu)\r
+#define OFS_UCAxIFG__UART_L OFS_UCAxIFG__UART\r
+#define OFS_UCAxIFG__UART_H OFS_UCAxIFG__UART+1\r
+#define OFS_UCAxIV (0x001Eu) /* USCI Ax Interrupt Vector Register */\r
+\r
+#define OFS_UCAxCTLW0__SPI (0x0000u)\r
+#define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI\r
+#define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1\r
+#define OFS_UCAxCTL0__SPI (0x0001u)\r
+#define OFS_UCAxCTL1__SPI (0x0000u)\r
+#define OFS_UCAxBRW__SPI (0x0006u)\r
+#define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI\r
+#define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1\r
+#define OFS_UCAxBR0__SPI (0x0006u)\r
+#define OFS_UCAxBR1__SPI (0x0007u)\r
+#define OFS_UCAxSTATW__SPI (0x000Au)\r
+#define OFS_UCAxRXBUF__SPI (0x000Cu)\r
+#define OFS_UCAxRXBUF__SPI_L OFS_UCAxRXBUF__SPI\r
+#define OFS_UCAxRXBUF__SPI_H OFS_UCAxRXBUF__SPI+1\r
+#define OFS_UCAxTXBUF__SPI (0x000Eu)\r
+#define OFS_UCAxTXBUF__SPI_L OFS_UCAxTXBUF__SPI\r
+#define OFS_UCAxTXBUF__SPI_H OFS_UCAxTXBUF__SPI+1\r
+#define OFS_UCAxIE__SPI (0x001Au)\r
+#define OFS_UCAxIFG__SPI (0x001Cu)\r
+#define OFS_UCAxIV__SPI (0x001Eu)\r
+\r
+#endif\r
+/************************************************************\r
+* USCI Bx\r
+************************************************************/\r
+#ifdef __MSP430_HAS_EUSCI_Bx__ /* Definition to show that Module is available */\r
+\r
+#define OFS_UCBxCTLW0__SPI (0x0000u)\r
+#define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI\r
+#define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1\r
+#define OFS_UCBxCTL0__SPI (0x0001u)\r
+#define OFS_UCBxCTL1__SPI (0x0000u)\r
+#define OFS_UCBxBRW__SPI (0x0006u)\r
+#define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI\r
+#define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1\r
+#define OFS_UCBxBR0__SPI (0x0006u)\r
+#define OFS_UCBxBR1__SPI (0x0007u)\r
+#define OFS_UCBxSTATW__SPI (0x0008u)\r
+#define OFS_UCBxSTATW__SPI_L OFS_UCBxSTATW__SPI\r
+#define OFS_UCBxSTATW__SPI_H OFS_UCBxSTATW__SPI+1\r
+#define OFS_UCBxRXBUF__SPI (0x000Cu)\r
+#define OFS_UCBxRXBUF__SPI_L OFS_UCBxRXBUF__SPI\r
+#define OFS_UCBxRXBUF__SPI_H OFS_UCBxRXBUF__SPI+1\r
+#define OFS_UCBxTXBUF__SPI (0x000Eu)\r
+#define OFS_UCBxTXBUF__SPI_L OFS_UCBxTXBUF__SPI\r
+#define OFS_UCBxTXBUF__SPI_H OFS_UCBxTXBUF__SPI+1\r
+#define OFS_UCBxIE__SPI (0x002Au)\r
+#define OFS_UCBxIE__SPI_L OFS_UCBxIE__SPI\r
+#define OFS_UCBxIE__SPI_H OFS_UCBxIE__SPI+1\r
+#define OFS_UCBxIFG__SPI (0x002Cu)\r
+#define OFS_UCBxIFG__SPI_L OFS_UCBxIFG__SPI\r
+#define OFS_UCBxIFG__SPI_H OFS_UCBxIFG__SPI+1\r
+#define OFS_UCBxIV__SPI (0x002Eu)\r
+\r
+#define OFS_UCBxCTLW0 (0x0000u) /* USCI Bx Control Word Register 0 */\r
+#define OFS_UCBxCTLW0_L OFS_UCBxCTLW0\r
+#define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1\r
+#define OFS_UCBxCTL0 (0x0001u)\r
+#define OFS_UCBxCTL1 (0x0000u)\r
+#define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */\r
+#define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */\r
+#define OFS_UCBxCTLW1 (0x0002u) /* USCI Bx Control Word Register 1 */\r
+#define OFS_UCBxCTLW1_L OFS_UCBxCTLW1\r
+#define OFS_UCBxCTLW1_H OFS_UCBxCTLW1+1\r
+#define OFS_UCBxBRW (0x0006u) /* USCI Bx Baud Word Rate 0 */\r
+#define OFS_UCBxBRW_L OFS_UCBxBRW\r
+#define OFS_UCBxBRW_H OFS_UCBxBRW+1\r
+#define OFS_UCBxBR0 (0x0006u)\r
+#define OFS_UCBxBR1 (0x0007u)\r
+#define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */\r
+#define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */\r
+#define OFS_UCBxSTATW (0x0008u) /* USCI Bx Status Word Register */\r
+#define OFS_UCBxSTATW_L OFS_UCBxSTATW\r
+#define OFS_UCBxSTATW_H OFS_UCBxSTATW+1\r
+#define OFS_UCBxSTATW__I2C (0x0008u)\r
+#define OFS_UCBxSTAT__I2C (0x0008u)\r
+#define OFS_UCBxBCNT__I2C (0x0009u)\r
+#define UCBxSTAT UCBxSTATW_L /* USCI Bx Status Register */\r
+#define UCBxBCNT UCBxSTATW_H /* USCI Bx Byte Counter Register */\r
+#define OFS_UCBxTBCNT (0x000Au) /* USCI Bx Byte Counter Threshold Register */\r
+#define OFS_UCBxTBCNT_L OFS_UCBxTBCNT\r
+#define OFS_UCBxTBCNT_H OFS_UCBxTBCNT+1\r
+#define OFS_UCBxRXBUF (0x000Cu) /* USCI Bx Receive Buffer */\r
+#define OFS_UCBxRXBUF_L OFS_UCBxRXBUF\r
+#define OFS_UCBxRXBUF_H OFS_UCBxRXBUF+1\r
+#define OFS_UCBxTXBUF (0x000Eu) /* USCI Bx Transmit Buffer */\r
+#define OFS_UCBxTXBUF_L OFS_UCBxTXBUF\r
+#define OFS_UCBxTXBUF_H OFS_UCBxTXBUF+1\r
+#define OFS_UCBxI2COA0 (0x0014u) /* USCI Bx I2C Own Address 0 */\r
+#define OFS_UCBxI2COA0_L OFS_UCBxI2COA0\r
+#define OFS_UCBxI2COA0_H OFS_UCBxI2COA0+1\r
+#define OFS_UCBxI2COA1 (0x0016u) /* USCI Bx I2C Own Address 1 */\r
+#define OFS_UCBxI2COA1_L OFS_UCBxI2COA1\r
+#define OFS_UCBxI2COA1_H OFS_UCBxI2COA1+1\r
+#define OFS_UCBxI2COA2 (0x0018u) /* USCI Bx I2C Own Address 2 */\r
+#define OFS_UCBxI2COA2_L OFS_UCBxI2COA2\r
+#define OFS_UCBxI2COA2_H OFS_UCBxI2COA2+1\r
+#define OFS_UCBxI2COA3 (0x001Au) /* USCI Bx I2C Own Address 3 */\r
+#define OFS_UCBxI2COA3_L OFS_UCBxI2COA3\r
+#define OFS_UCBxI2COA3_H OFS_UCBxI2COA3+1\r
+#define OFS_UCBxADDRX (0x001Cu) /* USCI Bx Received Address Register */\r
+#define OFS_UCBxADDRX_L OFS_UCBxADDRX\r
+#define OFS_UCBxADDRX_H OFS_UCBxADDRX+1\r
+#define OFS_UCBxADDMASK (0x001Eu) /* USCI Bx Address Mask Register */\r
+#define OFS_UCBxADDMASK_L OFS_UCBxADDMASK\r
+#define OFS_UCBxADDMASK_H OFS_UCBxADDMASK+1\r
+#define OFS_UCBxI2CSA (0x0020u) /* USCI Bx I2C Slave Address */\r
+#define OFS_UCBxI2CSA_L OFS_UCBxI2CSA\r
+#define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1\r
+#define OFS_UCBxIE (0x002Au) /* USCI Bx Interrupt Enable Register */\r
+#define OFS_UCBxIE_L OFS_UCBxIE\r
+#define OFS_UCBxIE_H OFS_UCBxIE+1\r
+#define OFS_UCBxIFG (0x002Cu) /* USCI Bx Interrupt Flags Register */\r
+#define OFS_UCBxIFG_L OFS_UCBxIFG\r
+#define OFS_UCBxIFG_H OFS_UCBxIFG+1\r
+#define OFS_UCBxIE__I2C (0x002Au)\r
+#define OFS_UCBxIE__I2C_L OFS_UCBxIE__I2C\r
+#define OFS_UCBxIE__I2C_H OFS_UCBxIE__I2C+1\r
+#define OFS_UCBxIFG__I2C (0x002Cu)\r
+#define OFS_UCBxIFG__I2C_L OFS_UCBxIFG__I2C\r
+#define OFS_UCBxIFG__I2C_H OFS_UCBxIFG__I2C+1\r
+#define OFS_UCBxIV (0x002Eu) /* USCI Bx Interrupt Vector Register */\r
+\r
+#endif\r
+#if (defined(__MSP430_HAS_EUSCI_Ax__) || defined(__MSP430_HAS_EUSCI_Bx__))\r
+\r
+// UCAxCTLW0 UART-Mode Control Bits\r
+#define UCPEN (0x8000u) /* Async. Mode: Parity enable */\r
+#define UCPAR (0x4000u) /* Async. Mode: Parity 0:odd / 1:even */\r
+#define UCMSB (0x2000u) /* Async. Mode: MSB first 0:LSB / 1:MSB */\r
+#define UC7BIT (0x1000u) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */\r
+#define UCSPB (0x0800u) /* Async. Mode: Stop Bits 0:one / 1: two */\r
+#define UCMODE1 (0x0400u) /* Async. Mode: USCI Mode 1 */\r
+#define UCMODE0 (0x0200u) /* Async. Mode: USCI Mode 0 */\r
+#define UCSYNC (0x0100u) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */\r
+#define UCSSEL1 (0x0080u) /* USCI 0 Clock Source Select 1 */\r
+#define UCSSEL0 (0x0040u) /* USCI 0 Clock Source Select 0 */\r
+#define UCRXEIE (0x0020u) /* RX Error interrupt enable */\r
+#define UCBRKIE (0x0010u) /* Break interrupt enable */\r
+#define UCDORM (0x0008u) /* Dormant (Sleep) Mode */\r
+#define UCTXADDR (0x0004u) /* Send next Data as Address */\r
+#define UCTXBRK (0x0002u) /* Send next Data as Break */\r
+#define UCSWRST (0x0001u) /* USCI Software Reset */\r
+\r
+// UCAxCTLW0 UART-Mode Control Bits\r
+#define UCSSEL1_L (0x0080u) /* USCI 0 Clock Source Select 1 */\r
+#define UCSSEL0_L (0x0040u) /* USCI 0 Clock Source Select 0 */\r
+#define UCRXEIE_L (0x0020u) /* RX Error interrupt enable */\r
+#define UCBRKIE_L (0x0010u) /* Break interrupt enable */\r
+#define UCDORM_L (0x0008u) /* Dormant (Sleep) Mode */\r
+#define UCTXADDR_L (0x0004u) /* Send next Data as Address */\r
+#define UCTXBRK_L (0x0002u) /* Send next Data as Break */\r
+#define UCSWRST_L (0x0001u) /* USCI Software Reset */\r
+\r
+// UCAxCTLW0 UART-Mode Control Bits\r
+#define UCPEN_H (0x0080u) /* Async. Mode: Parity enable */\r
+#define UCPAR_H (0x0040u) /* Async. Mode: Parity 0:odd / 1:even */\r
+#define UCMSB_H (0x0020u) /* Async. Mode: MSB first 0:LSB / 1:MSB */\r
+#define UC7BIT_H (0x0010u) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */\r
+#define UCSPB_H (0x0008u) /* Async. Mode: Stop Bits 0:one / 1: two */\r
+#define UCMODE1_H (0x0004u) /* Async. Mode: USCI Mode 1 */\r
+#define UCMODE0_H (0x0002u) /* Async. Mode: USCI Mode 0 */\r
+#define UCSYNC_H (0x0001u) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */\r
+\r
+// UCxxCTLW0 SPI-Mode Control Bits\r
+#define UCCKPH (0x8000u) /* Sync. Mode: Clock Phase */\r
+#define UCCKPL (0x4000u) /* Sync. Mode: Clock Polarity */\r
+#define UCMST (0x0800u) /* Sync. Mode: Master Select */\r
+//#define res (0x0020u) /* reserved */\r
+//#define res (0x0010u) /* reserved */\r
+//#define res (0x0008u) /* reserved */\r
+//#define res (0x0004u) /* reserved */\r
+#define UCSTEM (0x0002u) /* USCI STE Mode */\r
+\r
+// UCBxCTLW0 I2C-Mode Control Bits\r
+#define UCA10 (0x8000u) /* 10-bit Address Mode */\r
+#define UCSLA10 (0x4000u) /* 10-bit Slave Address Mode */\r
+#define UCMM (0x2000u) /* Multi-Master Environment */\r
+//#define res (0x1000u) /* reserved */\r
+//#define res (0x0100u) /* reserved */\r
+#define UCTXACK (0x0020u) /* Transmit ACK */\r
+#define UCTR (0x0010u) /* Transmit/Receive Select/Flag */\r
+#define UCTXNACK (0x0008u) /* Transmit NACK */\r
+#define UCTXSTP (0x0004u) /* Transmit STOP */\r
+#define UCTXSTT (0x0002u) /* Transmit START */\r
+\r
+// UCBxCTLW0 I2C-Mode Control Bits\r
+//#define res (0x1000u) /* reserved */\r
+//#define res (0x0100u) /* reserved */\r
+#define UCTXACK_L (0x0020u) /* Transmit ACK */\r
+#define UCTR_L (0x0010u) /* Transmit/Receive Select/Flag */\r
+#define UCTXNACK_L (0x0008u) /* Transmit NACK */\r
+#define UCTXSTP_L (0x0004u) /* Transmit STOP */\r
+#define UCTXSTT_L (0x0002u) /* Transmit START */\r
+\r
+// UCBxCTLW0 I2C-Mode Control Bits\r
+#define UCA10_H (0x0080u) /* 10-bit Address Mode */\r
+#define UCSLA10_H (0x0040u) /* 10-bit Slave Address Mode */\r
+#define UCMM_H (0x0020u) /* Multi-Master Environment */\r
+//#define res (0x1000u) /* reserved */\r
+//#define res (0x0100u) /* reserved */\r
+\r
+#define UCMODE_0 (0x0000u) /* Sync. Mode: USCI Mode: 0 */\r
+#define UCMODE_1 (0x0200u) /* Sync. Mode: USCI Mode: 1 */\r
+#define UCMODE_2 (0x0400u) /* Sync. Mode: USCI Mode: 2 */\r
+#define UCMODE_3 (0x0600u) /* Sync. Mode: USCI Mode: 3 */\r
+\r
+#define UCSSEL_0 (0x0000u) /* USCI 0 Clock Source: 0 */\r
+#define UCSSEL_1 (0x0040u) /* USCI 0 Clock Source: 1 */\r
+#define UCSSEL_2 (0x0080u) /* USCI 0 Clock Source: 2 */\r
+#define UCSSEL_3 (0x00C0u) /* USCI 0 Clock Source: 3 */\r
+#define UCSSEL__UCLK (0x0000u) /* USCI 0 Clock Source: UCLK */\r
+#define UCSSEL__ACLK (0x0040u) /* USCI 0 Clock Source: ACLK */\r
+#define UCSSEL__SMCLK (0x0080u) /* USCI 0 Clock Source: SMCLK */\r
+\r
+// UCAxCTLW1 UART-Mode Control Bits\r
+#define UCGLIT1 (0x0002u) /* USCI Deglitch Time Bit 1 */\r
+#define UCGLIT0 (0x0001u) /* USCI Deglitch Time Bit 0 */\r
+\r
+// UCAxCTLW1 UART-Mode Control Bits\r
+#define UCGLIT1_L (0x0002u) /* USCI Deglitch Time Bit 1 */\r
+#define UCGLIT0_L (0x0001u) /* USCI Deglitch Time Bit 0 */\r
+\r
+// UCBxCTLW1 I2C-Mode Control Bits\r
+#define UCETXINT (0x0100u) /* USCI Early UCTXIFG0 */\r
+#define UCCLTO1 (0x0080u) /* USCI Clock low timeout Bit: 1 */\r
+#define UCCLTO0 (0x0040u) /* USCI Clock low timeout Bit: 0 */\r
+#define UCSTPNACK (0x0020u) /* USCI Acknowledge Stop last byte */\r
+#define UCSWACK (0x0010u) /* USCI Software controlled ACK */\r
+#define UCASTP1 (0x0008u) /* USCI Automatic Stop condition generation Bit: 1 */\r
+#define UCASTP0 (0x0004u) /* USCI Automatic Stop condition generation Bit: 0 */\r
+#define UCGLIT1 (0x0002u) /* USCI Deglitch time Bit: 1 */\r
+#define UCGLIT0 (0x0001u) /* USCI Deglitch time Bit: 0 */\r
+\r
+// UCBxCTLW1 I2C-Mode Control Bits\r
+#define UCCLTO1_L (0x0080u) /* USCI Clock low timeout Bit: 1 */\r
+#define UCCLTO0_L (0x0040u) /* USCI Clock low timeout Bit: 0 */\r
+#define UCSTPNACK_L (0x0020u) /* USCI Acknowledge Stop last byte */\r
+#define UCSWACK_L (0x0010u) /* USCI Software controlled ACK */\r
+#define UCASTP1_L (0x0008u) /* USCI Automatic Stop condition generation Bit: 1 */\r
+#define UCASTP0_L (0x0004u) /* USCI Automatic Stop condition generation Bit: 0 */\r
+#define UCGLIT1_L (0x0002u) /* USCI Deglitch time Bit: 1 */\r
+#define UCGLIT0_L (0x0001u) /* USCI Deglitch time Bit: 0 */\r
+\r
+// UCBxCTLW1 I2C-Mode Control Bits\r
+#define UCETXINT_H (0x0001u) /* USCI Early UCTXIFG0 */\r
+\r
+#define UCGLIT_0 (0x0000u) /* USCI Deglitch time: 0 */\r
+#define UCGLIT_1 (0x0001u) /* USCI Deglitch time: 1 */\r
+#define UCGLIT_2 (0x0002u) /* USCI Deglitch time: 2 */\r
+#define UCGLIT_3 (0x0003u) /* USCI Deglitch time: 3 */\r
+\r
+#define UCASTP_0 (0x0000u) /* USCI Automatic Stop condition generation: 0 */\r
+#define UCASTP_1 (0x0004u) /* USCI Automatic Stop condition generation: 1 */\r
+#define UCASTP_2 (0x0008u) /* USCI Automatic Stop condition generation: 2 */\r
+#define UCASTP_3 (0x000Cu) /* USCI Automatic Stop condition generation: 3 */\r
+\r
+#define UCCLTO_0 (0x0000u) /* USCI Clock low timeout: 0 */\r
+#define UCCLTO_1 (0x0040u) /* USCI Clock low timeout: 1 */\r
+#define UCCLTO_2 (0x0080u) /* USCI Clock low timeout: 2 */\r
+#define UCCLTO_3 (0x00C0u) /* USCI Clock low timeout: 3 */\r
+\r
+/* UCAxMCTLW Control Bits */\r
+#define UCBRS7 (0x8000u) /* USCI Second Stage Modulation Select 7 */\r
+#define UCBRS6 (0x4000u) /* USCI Second Stage Modulation Select 6 */\r
+#define UCBRS5 (0x2000u) /* USCI Second Stage Modulation Select 5 */\r
+#define UCBRS4 (0x1000u) /* USCI Second Stage Modulation Select 4 */\r
+#define UCBRS3 (0x0800u) /* USCI Second Stage Modulation Select 3 */\r
+#define UCBRS2 (0x0400u) /* USCI Second Stage Modulation Select 2 */\r
+#define UCBRS1 (0x0200u) /* USCI Second Stage Modulation Select 1 */\r
+#define UCBRS0 (0x0100u) /* USCI Second Stage Modulation Select 0 */\r
+#define UCBRF3 (0x0080u) /* USCI First Stage Modulation Select 3 */\r
+#define UCBRF2 (0x0040u) /* USCI First Stage Modulation Select 2 */\r
+#define UCBRF1 (0x0020u) /* USCI First Stage Modulation Select 1 */\r
+#define UCBRF0 (0x0010u) /* USCI First Stage Modulation Select 0 */\r
+#define UCOS16 (0x0001u) /* USCI 16-times Oversampling enable */\r
+\r
+/* UCAxMCTLW Control Bits */\r
+#define UCBRF3_L (0x0080u) /* USCI First Stage Modulation Select 3 */\r
+#define UCBRF2_L (0x0040u) /* USCI First Stage Modulation Select 2 */\r
+#define UCBRF1_L (0x0020u) /* USCI First Stage Modulation Select 1 */\r
+#define UCBRF0_L (0x0010u) /* USCI First Stage Modulation Select 0 */\r
+#define UCOS16_L (0x0001u) /* USCI 16-times Oversampling enable */\r
+\r
+/* UCAxMCTLW Control Bits */\r
+#define UCBRS7_H (0x0080u) /* USCI Second Stage Modulation Select 7 */\r
+#define UCBRS6_H (0x0040u) /* USCI Second Stage Modulation Select 6 */\r
+#define UCBRS5_H (0x0020u) /* USCI Second Stage Modulation Select 5 */\r
+#define UCBRS4_H (0x0010u) /* USCI Second Stage Modulation Select 4 */\r
+#define UCBRS3_H (0x0008u) /* USCI Second Stage Modulation Select 3 */\r
+#define UCBRS2_H (0x0004u) /* USCI Second Stage Modulation Select 2 */\r
+#define UCBRS1_H (0x0002u) /* USCI Second Stage Modulation Select 1 */\r
+#define UCBRS0_H (0x0001u) /* USCI Second Stage Modulation Select 0 */\r
+\r
+#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */\r
+#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */\r
+#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */\r
+#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */\r
+#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */\r
+#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */\r
+#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */\r
+#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */\r
+#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */\r
+#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */\r
+#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */\r
+#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */\r
+#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */\r
+#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */\r
+#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */\r
+#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */\r
+\r
+/* UCAxSTATW Control Bits */\r
+#define UCLISTEN (0x0080u) /* USCI Listen mode */\r
+#define UCFE (0x0040u) /* USCI Frame Error Flag */\r
+#define UCOE (0x0020u) /* USCI Overrun Error Flag */\r
+#define UCPE (0x0010u) /* USCI Parity Error Flag */\r
+#define UCBRK (0x0008u) /* USCI Break received */\r
+#define UCRXERR (0x0004u) /* USCI RX Error Flag */\r
+#define UCADDR (0x0002u) /* USCI Address received Flag */\r
+#define UCBUSY (0x0001u) /* USCI Busy Flag */\r
+#define UCIDLE (0x0002u) /* USCI Idle line detected Flag */\r
+\r
+/* UCBxSTATW I2C Control Bits */\r
+#define UCBCNT7 (0x8000u) /* USCI Byte Counter Bit 7 */\r
+#define UCBCNT6 (0x4000u) /* USCI Byte Counter Bit 6 */\r
+#define UCBCNT5 (0x2000u) /* USCI Byte Counter Bit 5 */\r
+#define UCBCNT4 (0x1000u) /* USCI Byte Counter Bit 4 */\r
+#define UCBCNT3 (0x0800u) /* USCI Byte Counter Bit 3 */\r
+#define UCBCNT2 (0x0400u) /* USCI Byte Counter Bit 2 */\r
+#define UCBCNT1 (0x0200u) /* USCI Byte Counter Bit 1 */\r
+#define UCBCNT0 (0x0100u) /* USCI Byte Counter Bit 0 */\r
+#define UCSCLLOW (0x0040u) /* SCL low */\r
+#define UCGC (0x0020u) /* General Call address received Flag */\r
+#define UCBBUSY (0x0010u) /* Bus Busy Flag */\r
+\r
+/* UCBxTBCNT I2C Control Bits */\r
+#define UCTBCNT7 (0x0080u) /* USCI Byte Counter Bit 7 */\r
+#define UCTBCNT6 (0x0040u) /* USCI Byte Counter Bit 6 */\r
+#define UCTBCNT5 (0x0020u) /* USCI Byte Counter Bit 5 */\r
+#define UCTBCNT4 (0x0010u) /* USCI Byte Counter Bit 4 */\r
+#define UCTBCNT3 (0x0008u) /* USCI Byte Counter Bit 3 */\r
+#define UCTBCNT2 (0x0004u) /* USCI Byte Counter Bit 2 */\r
+#define UCTBCNT1 (0x0002u) /* USCI Byte Counter Bit 1 */\r
+#define UCTBCNT0 (0x0001u) /* USCI Byte Counter Bit 0 */\r
+\r
+/* UCAxIRCTL Control Bits */\r
+#define UCIRRXFL5 (0x8000u) /* IRDA Receive Filter Length 5 */\r
+#define UCIRRXFL4 (0x4000u) /* IRDA Receive Filter Length 4 */\r
+#define UCIRRXFL3 (0x2000u) /* IRDA Receive Filter Length 3 */\r
+#define UCIRRXFL2 (0x1000u) /* IRDA Receive Filter Length 2 */\r
+#define UCIRRXFL1 (0x0800u) /* IRDA Receive Filter Length 1 */\r
+#define UCIRRXFL0 (0x0400u) /* IRDA Receive Filter Length 0 */\r
+#define UCIRRXPL (0x0200u) /* IRDA Receive Input Polarity */\r
+#define UCIRRXFE (0x0100u) /* IRDA Receive Filter enable */\r
+#define UCIRTXPL5 (0x0080u) /* IRDA Transmit Pulse Length 5 */\r
+#define UCIRTXPL4 (0x0040u) /* IRDA Transmit Pulse Length 4 */\r
+#define UCIRTXPL3 (0x0020u) /* IRDA Transmit Pulse Length 3 */\r
+#define UCIRTXPL2 (0x0010u) /* IRDA Transmit Pulse Length 2 */\r
+#define UCIRTXPL1 (0x0008u) /* IRDA Transmit Pulse Length 1 */\r
+#define UCIRTXPL0 (0x0004u) /* IRDA Transmit Pulse Length 0 */\r
+#define UCIRTXCLK (0x0002u) /* IRDA Transmit Pulse Clock Select */\r
+#define UCIREN (0x0001u) /* IRDA Encoder/Decoder enable */\r
+\r
+/* UCAxIRCTL Control Bits */\r
+#define UCIRTXPL5_L (0x0080u) /* IRDA Transmit Pulse Length 5 */\r
+#define UCIRTXPL4_L (0x0040u) /* IRDA Transmit Pulse Length 4 */\r
+#define UCIRTXPL3_L (0x0020u) /* IRDA Transmit Pulse Length 3 */\r
+#define UCIRTXPL2_L (0x0010u) /* IRDA Transmit Pulse Length 2 */\r
+#define UCIRTXPL1_L (0x0008u) /* IRDA Transmit Pulse Length 1 */\r
+#define UCIRTXPL0_L (0x0004u) /* IRDA Transmit Pulse Length 0 */\r
+#define UCIRTXCLK_L (0x0002u) /* IRDA Transmit Pulse Clock Select */\r
+#define UCIREN_L (0x0001u) /* IRDA Encoder/Decoder enable */\r
+\r
+/* UCAxIRCTL Control Bits */\r
+#define UCIRRXFL5_H (0x0080u) /* IRDA Receive Filter Length 5 */\r
+#define UCIRRXFL4_H (0x0040u) /* IRDA Receive Filter Length 4 */\r
+#define UCIRRXFL3_H (0x0020u) /* IRDA Receive Filter Length 3 */\r
+#define UCIRRXFL2_H (0x0010u) /* IRDA Receive Filter Length 2 */\r
+#define UCIRRXFL1_H (0x0008u) /* IRDA Receive Filter Length 1 */\r
+#define UCIRRXFL0_H (0x0004u) /* IRDA Receive Filter Length 0 */\r
+#define UCIRRXPL_H (0x0002u) /* IRDA Receive Input Polarity */\r
+#define UCIRRXFE_H (0x0001u) /* IRDA Receive Filter enable */\r
+\r
+/* UCAxABCTL Control Bits */\r
+//#define res (0x80) /* reserved */\r
+//#define res (0x40) /* reserved */\r
+#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */\r
+#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */\r
+#define UCSTOE (0x08) /* Sync-Field Timeout error */\r
+#define UCBTOE (0x04) /* Break Timeout error */\r
+//#define res (0x02) /* reserved */\r
+#define UCABDEN (0x01) /* Auto Baud Rate detect enable */\r
+\r
+/* UCBxI2COA0 Control Bits */\r
+#define UCGCEN (0x8000u) /* I2C General Call enable */\r
+#define UCOAEN (0x0400u) /* I2C Own Address enable */\r
+#define UCOA9 (0x0200u) /* I2C Own Address Bit 9 */\r
+#define UCOA8 (0x0100u) /* I2C Own Address Bit 8 */\r
+#define UCOA7 (0x0080u) /* I2C Own Address Bit 7 */\r
+#define UCOA6 (0x0040u) /* I2C Own Address Bit 6 */\r
+#define UCOA5 (0x0020u) /* I2C Own Address Bit 5 */\r
+#define UCOA4 (0x0010u) /* I2C Own Address Bit 4 */\r
+#define UCOA3 (0x0008u) /* I2C Own Address Bit 3 */\r
+#define UCOA2 (0x0004u) /* I2C Own Address Bit 2 */\r
+#define UCOA1 (0x0002u) /* I2C Own Address Bit 1 */\r
+#define UCOA0 (0x0001u) /* I2C Own Address Bit 0 */\r
+\r
+/* UCBxI2COA0 Control Bits */\r
+#define UCOA7_L (0x0080u) /* I2C Own Address Bit 7 */\r
+#define UCOA6_L (0x0040u) /* I2C Own Address Bit 6 */\r
+#define UCOA5_L (0x0020u) /* I2C Own Address Bit 5 */\r
+#define UCOA4_L (0x0010u) /* I2C Own Address Bit 4 */\r
+#define UCOA3_L (0x0008u) /* I2C Own Address Bit 3 */\r
+#define UCOA2_L (0x0004u) /* I2C Own Address Bit 2 */\r
+#define UCOA1_L (0x0002u) /* I2C Own Address Bit 1 */\r
+#define UCOA0_L (0x0001u) /* I2C Own Address Bit 0 */\r
+\r
+/* UCBxI2COA0 Control Bits */\r
+#define UCGCEN_H (0x0080u) /* I2C General Call enable */\r
+#define UCOAEN_H (0x0004u) /* I2C Own Address enable */\r
+#define UCOA9_H (0x0002u) /* I2C Own Address Bit 9 */\r
+#define UCOA8_H (0x0001u) /* I2C Own Address Bit 8 */\r
+\r
+/* UCBxI2COAx Control Bits */\r
+#define UCOAEN (0x0400u) /* I2C Own Address enable */\r
+#define UCOA9 (0x0200u) /* I2C Own Address Bit 9 */\r
+#define UCOA8 (0x0100u) /* I2C Own Address Bit 8 */\r
+#define UCOA7 (0x0080u) /* I2C Own Address Bit 7 */\r
+#define UCOA6 (0x0040u) /* I2C Own Address Bit 6 */\r
+#define UCOA5 (0x0020u) /* I2C Own Address Bit 5 */\r
+#define UCOA4 (0x0010u) /* I2C Own Address Bit 4 */\r
+#define UCOA3 (0x0008u) /* I2C Own Address Bit 3 */\r
+#define UCOA2 (0x0004u) /* I2C Own Address Bit 2 */\r
+#define UCOA1 (0x0002u) /* I2C Own Address Bit 1 */\r
+#define UCOA0 (0x0001u) /* I2C Own Address Bit 0 */\r
+\r
+/* UCBxI2COAx Control Bits */\r
+#define UCOA7_L (0x0080u) /* I2C Own Address Bit 7 */\r
+#define UCOA6_L (0x0040u) /* I2C Own Address Bit 6 */\r
+#define UCOA5_L (0x0020u) /* I2C Own Address Bit 5 */\r
+#define UCOA4_L (0x0010u) /* I2C Own Address Bit 4 */\r
+#define UCOA3_L (0x0008u) /* I2C Own Address Bit 3 */\r
+#define UCOA2_L (0x0004u) /* I2C Own Address Bit 2 */\r
+#define UCOA1_L (0x0002u) /* I2C Own Address Bit 1 */\r
+#define UCOA0_L (0x0001u) /* I2C Own Address Bit 0 */\r
+\r
+/* UCBxI2COAx Control Bits */\r
+#define UCOAEN_H (0x0004u) /* I2C Own Address enable */\r
+#define UCOA9_H (0x0002u) /* I2C Own Address Bit 9 */\r
+#define UCOA8_H (0x0001u) /* I2C Own Address Bit 8 */\r
+\r
+/* UCBxADDRX Control Bits */\r
+#define UCADDRX9 (0x0200u) /* I2C Receive Address Bit 9 */\r
+#define UCADDRX8 (0x0100u) /* I2C Receive Address Bit 8 */\r
+#define UCADDRX7 (0x0080u) /* I2C Receive Address Bit 7 */\r
+#define UCADDRX6 (0x0040u) /* I2C Receive Address Bit 6 */\r
+#define UCADDRX5 (0x0020u) /* I2C Receive Address Bit 5 */\r
+#define UCADDRX4 (0x0010u) /* I2C Receive Address Bit 4 */\r
+#define UCADDRX3 (0x0008u) /* I2C Receive Address Bit 3 */\r
+#define UCADDRX2 (0x0004u) /* I2C Receive Address Bit 2 */\r
+#define UCADDRX1 (0x0002u) /* I2C Receive Address Bit 1 */\r
+#define UCADDRX0 (0x0001u) /* I2C Receive Address Bit 0 */\r
+\r
+/* UCBxADDRX Control Bits */\r
+#define UCADDRX7_L (0x0080u) /* I2C Receive Address Bit 7 */\r
+#define UCADDRX6_L (0x0040u) /* I2C Receive Address Bit 6 */\r
+#define UCADDRX5_L (0x0020u) /* I2C Receive Address Bit 5 */\r
+#define UCADDRX4_L (0x0010u) /* I2C Receive Address Bit 4 */\r
+#define UCADDRX3_L (0x0008u) /* I2C Receive Address Bit 3 */\r
+#define UCADDRX2_L (0x0004u) /* I2C Receive Address Bit 2 */\r
+#define UCADDRX1_L (0x0002u) /* I2C Receive Address Bit 1 */\r
+#define UCADDRX0_L (0x0001u) /* I2C Receive Address Bit 0 */\r
+\r
+/* UCBxADDRX Control Bits */\r
+#define UCADDRX9_H (0x0002u) /* I2C Receive Address Bit 9 */\r
+#define UCADDRX8_H (0x0001u) /* I2C Receive Address Bit 8 */\r
+\r
+/* UCBxADDMASK Control Bits */\r
+#define UCADDMASK9 (0x0200u) /* I2C Address Mask Bit 9 */\r
+#define UCADDMASK8 (0x0100u) /* I2C Address Mask Bit 8 */\r
+#define UCADDMASK7 (0x0080u) /* I2C Address Mask Bit 7 */\r
+#define UCADDMASK6 (0x0040u) /* I2C Address Mask Bit 6 */\r
+#define UCADDMASK5 (0x0020u) /* I2C Address Mask Bit 5 */\r
+#define UCADDMASK4 (0x0010u) /* I2C Address Mask Bit 4 */\r
+#define UCADDMASK3 (0x0008u) /* I2C Address Mask Bit 3 */\r
+#define UCADDMASK2 (0x0004u) /* I2C Address Mask Bit 2 */\r
+#define UCADDMASK1 (0x0002u) /* I2C Address Mask Bit 1 */\r
+#define UCADDMASK0 (0x0001u) /* I2C Address Mask Bit 0 */\r
+\r
+/* UCBxADDMASK Control Bits */\r
+#define UCADDMASK7_L (0x0080u) /* I2C Address Mask Bit 7 */\r
+#define UCADDMASK6_L (0x0040u) /* I2C Address Mask Bit 6 */\r
+#define UCADDMASK5_L (0x0020u) /* I2C Address Mask Bit 5 */\r
+#define UCADDMASK4_L (0x0010u) /* I2C Address Mask Bit 4 */\r
+#define UCADDMASK3_L (0x0008u) /* I2C Address Mask Bit 3 */\r
+#define UCADDMASK2_L (0x0004u) /* I2C Address Mask Bit 2 */\r
+#define UCADDMASK1_L (0x0002u) /* I2C Address Mask Bit 1 */\r
+#define UCADDMASK0_L (0x0001u) /* I2C Address Mask Bit 0 */\r
+\r
+/* UCBxADDMASK Control Bits */\r
+#define UCADDMASK9_H (0x0002u) /* I2C Address Mask Bit 9 */\r
+#define UCADDMASK8_H (0x0001u) /* I2C Address Mask Bit 8 */\r
+\r
+/* UCBxI2CSA Control Bits */\r
+#define UCSA9 (0x0200u) /* I2C Slave Address Bit 9 */\r
+#define UCSA8 (0x0100u) /* I2C Slave Address Bit 8 */\r
+#define UCSA7 (0x0080u) /* I2C Slave Address Bit 7 */\r
+#define UCSA6 (0x0040u) /* I2C Slave Address Bit 6 */\r
+#define UCSA5 (0x0020u) /* I2C Slave Address Bit 5 */\r
+#define UCSA4 (0x0010u) /* I2C Slave Address Bit 4 */\r
+#define UCSA3 (0x0008u) /* I2C Slave Address Bit 3 */\r
+#define UCSA2 (0x0004u) /* I2C Slave Address Bit 2 */\r
+#define UCSA1 (0x0002u) /* I2C Slave Address Bit 1 */\r
+#define UCSA0 (0x0001u) /* I2C Slave Address Bit 0 */\r
+\r
+/* UCBxI2CSA Control Bits */\r
+#define UCSA7_L (0x0080u) /* I2C Slave Address Bit 7 */\r
+#define UCSA6_L (0x0040u) /* I2C Slave Address Bit 6 */\r
+#define UCSA5_L (0x0020u) /* I2C Slave Address Bit 5 */\r
+#define UCSA4_L (0x0010u) /* I2C Slave Address Bit 4 */\r
+#define UCSA3_L (0x0008u) /* I2C Slave Address Bit 3 */\r
+#define UCSA2_L (0x0004u) /* I2C Slave Address Bit 2 */\r
+#define UCSA1_L (0x0002u) /* I2C Slave Address Bit 1 */\r
+#define UCSA0_L (0x0001u) /* I2C Slave Address Bit 0 */\r
+\r
+/* UCBxI2CSA Control Bits */\r
+#define UCSA9_H (0x0002u) /* I2C Slave Address Bit 9 */\r
+#define UCSA8_H (0x0001u) /* I2C Slave Address Bit 8 */\r
+\r
+/* UCAxIE UART Control Bits */\r
+#define UCTXCPTIE (0x0008u) /* UART Transmit Complete Interrupt Enable */\r
+#define UCSTTIE (0x0004u) /* UART Start Bit Interrupt Enalble */\r
+#define UCTXIE (0x0002u) /* UART Transmit Interrupt Enable */\r
+#define UCRXIE (0x0001u) /* UART Receive Interrupt Enable */\r
+\r
+/* UCAxIE/UCBxIE SPI Control Bits */\r
+\r
+/* UCBxIE I2C Control Bits */\r
+#define UCBIT9IE (0x4000u) /* I2C Bit 9 Position Interrupt Enable 3 */\r
+#define UCTXIE3 (0x2000u) /* I2C Transmit Interrupt Enable 3 */\r
+#define UCRXIE3 (0x1000u) /* I2C Receive Interrupt Enable 3 */\r
+#define UCTXIE2 (0x0800u) /* I2C Transmit Interrupt Enable 2 */\r
+#define UCRXIE2 (0x0400u) /* I2C Receive Interrupt Enable 2 */\r
+#define UCTXIE1 (0x0200u) /* I2C Transmit Interrupt Enable 1 */\r
+#define UCRXIE1 (0x0100u) /* I2C Receive Interrupt Enable 1 */\r
+#define UCCLTOIE (0x0080u) /* I2C Clock Low Timeout interrupt enable */\r
+#define UCBCNTIE (0x0040u) /* I2C Automatic stop assertion interrupt enable */\r
+#define UCNACKIE (0x0020u) /* I2C NACK Condition interrupt enable */\r
+#define UCALIE (0x0010u) /* I2C Arbitration Lost interrupt enable */\r
+#define UCSTPIE (0x0008u) /* I2C STOP Condition interrupt enable */\r
+#define UCSTTIE (0x0004u) /* I2C START Condition interrupt enable */\r
+#define UCTXIE0 (0x0002u) /* I2C Transmit Interrupt Enable 0 */\r
+#define UCRXIE0 (0x0001u) /* I2C Receive Interrupt Enable 0 */\r
+\r
+/* UCAxIFG UART Control Bits */\r
+#define UCTXCPTIFG (0x0008u) /* UART Transmit Complete Interrupt Flag */\r
+#define UCSTTIFG (0x0004u) /* UART Start Bit Interrupt Flag */\r
+#define UCTXIFG (0x0002u) /* UART Transmit Interrupt Flag */\r
+#define UCRXIFG (0x0001u) /* UART Receive Interrupt Flag */\r
+\r
+/* UCAxIFG/UCBxIFG SPI Control Bits */\r
+#define UCTXIFG (0x0002u) /* SPI Transmit Interrupt Flag */\r
+#define UCRXIFG (0x0001u) /* SPI Receive Interrupt Flag */\r
+\r
+/* UCBxIFG Control Bits */\r
+#define UCBIT9IFG (0x4000u) /* I2C Bit 9 Possition Interrupt Flag 3 */\r
+#define UCTXIFG3 (0x2000u) /* I2C Transmit Interrupt Flag 3 */\r
+#define UCRXIFG3 (0x1000u) /* I2C Receive Interrupt Flag 3 */\r
+#define UCTXIFG2 (0x0800u) /* I2C Transmit Interrupt Flag 2 */\r
+#define UCRXIFG2 (0x0400u) /* I2C Receive Interrupt Flag 2 */\r
+#define UCTXIFG1 (0x0200u) /* I2C Transmit Interrupt Flag 1 */\r
+#define UCRXIFG1 (0x0100u) /* I2C Receive Interrupt Flag 1 */\r
+#define UCCLTOIFG (0x0080u) /* I2C Clock low Timeout interrupt Flag */\r
+#define UCBCNTIFG (0x0040u) /* I2C Byte counter interrupt flag */\r
+#define UCNACKIFG (0x0020u) /* I2C NACK Condition interrupt Flag */\r
+#define UCALIFG (0x0010u) /* I2C Arbitration Lost interrupt Flag */\r
+#define UCSTPIFG (0x0008u) /* I2C STOP Condition interrupt Flag */\r
+#define UCSTTIFG (0x0004u) /* I2C START Condition interrupt Flag */\r
+#define UCTXIFG0 (0x0002u) /* I2C Transmit Interrupt Flag 0 */\r
+#define UCRXIFG0 (0x0001u) /* I2C Receive Interrupt Flag 0 */\r
+\r
+/* USCI UART Definitions */\r
+#define USCI_NONE (0x0000u) /* No Interrupt pending */\r
+#define USCI_UART_UCRXIFG (0x0002u) /* USCI UCRXIFG */\r
+#define USCI_UART_UCTXIFG (0x0004u) /* USCI UCTXIFG */\r
+#define USCI_UART_UCSTTIFG (0x0006u) /* USCI UCSTTIFG */\r
+#define USCI_UART_UCTXCPTIFG (0x0008u) /* USCI UCTXCPTIFG */\r
+\r
+/* USCI SPI Definitions */\r
+#define USCI_SPI_UCRXIFG (0x0002u) /* USCI UCRXIFG */\r
+#define USCI_SPI_UCTXIFG (0x0004u) /* USCI UCTXIFG */\r
+\r
+/* USCI I2C Definitions */\r
+#define USCI_I2C_UCALIFG (0x0002u) /* USCI I2C Mode: UCALIFG */\r
+#define USCI_I2C_UCNACKIFG (0x0004u) /* USCI I2C Mode: UCNACKIFG */\r
+#define USCI_I2C_UCSTTIFG (0x0006u) /* USCI I2C Mode: UCSTTIFG*/\r
+#define USCI_I2C_UCSTPIFG (0x0008u) /* USCI I2C Mode: UCSTPIFG*/\r
+#define USCI_I2C_UCRXIFG3 (0x000Au) /* USCI I2C Mode: UCRXIFG3 */\r
+#define USCI_I2C_UCTXIFG3 (0x000Cu) /* USCI I2C Mode: UCTXIFG3 */\r
+#define USCI_I2C_UCRXIFG2 (0x000Eu) /* USCI I2C Mode: UCRXIFG2 */\r
+#define USCI_I2C_UCTXIFG2 (0x0010u) /* USCI I2C Mode: UCTXIFG2 */\r
+#define USCI_I2C_UCRXIFG1 (0x0012u) /* USCI I2C Mode: UCRXIFG1 */\r
+#define USCI_I2C_UCTXIFG1 (0x0014u) /* USCI I2C Mode: UCTXIFG1 */\r
+#define USCI_I2C_UCRXIFG0 (0x0016u) /* USCI I2C Mode: UCRXIFG0 */\r
+#define USCI_I2C_UCTXIFG0 (0x0018u) /* USCI I2C Mode: UCTXIFG0 */\r
+#define USCI_I2C_UCBCNTIFG (0x001Au) /* USCI I2C Mode: UCBCNTIFG */\r
+#define USCI_I2C_UCCLTOIFG (0x001Cu) /* USCI I2C Mode: UCCLTOIFG */\r
+#define USCI_I2C_UCBIT9IFG (0x001Eu) /* USCI I2C Mode: UCBIT9IFG */\r
+\r
+#endif\r
+/************************************************************\r
+* WATCHDOG TIMER A\r
+************************************************************/\r
+#ifdef __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */\r
+\r
+#define OFS_WDTCTL (0x000Cu) /* Watchdog Timer Control */\r
+#define OFS_WDTCTL_L OFS_WDTCTL\r
+#define OFS_WDTCTL_H OFS_WDTCTL+1\r
+/* The bit names have been prefixed with "WDT" */\r
+/* WDTCTL Control Bits */\r
+#define WDTIS0 (0x0001u) /* WDT - Timer Interval Select 0 */\r
+#define WDTIS1 (0x0002u) /* WDT - Timer Interval Select 1 */\r
+#define WDTIS2 (0x0004u) /* WDT - Timer Interval Select 2 */\r
+#define WDTCNTCL (0x0008u) /* WDT - Timer Clear */\r
+#define WDTTMSEL (0x0010u) /* WDT - Timer Mode Select */\r
+#define WDTSSEL0 (0x0020u) /* WDT - Timer Clock Source Select 0 */\r
+#define WDTSSEL1 (0x0040u) /* WDT - Timer Clock Source Select 1 */\r
+#define WDTHOLD (0x0080u) /* WDT - Timer hold */\r
+\r
+/* WDTCTL Control Bits */\r
+#define WDTIS0_L (0x0001u) /* WDT - Timer Interval Select 0 */\r
+#define WDTIS1_L (0x0002u) /* WDT - Timer Interval Select 1 */\r
+#define WDTIS2_L (0x0004u) /* WDT - Timer Interval Select 2 */\r
+#define WDTCNTCL_L (0x0008u) /* WDT - Timer Clear */\r
+#define WDTTMSEL_L (0x0010u) /* WDT - Timer Mode Select */\r
+#define WDTSSEL0_L (0x0020u) /* WDT - Timer Clock Source Select 0 */\r
+#define WDTSSEL1_L (0x0040u) /* WDT - Timer Clock Source Select 1 */\r
+#define WDTHOLD_L (0x0080u) /* WDT - Timer hold */\r
+\r
+#define WDTPW (0x5A00u)\r
+\r
+#define WDTIS_0 (0*0x0001u) /* WDT - Timer Interval Select: /2G */\r
+#define WDTIS_1 (1*0x0001u) /* WDT - Timer Interval Select: /128M */\r
+#define WDTIS_2 (2*0x0001u) /* WDT - Timer Interval Select: /8192k */\r
+#define WDTIS_3 (3*0x0001u) /* WDT - Timer Interval Select: /512k */\r
+#define WDTIS_4 (4*0x0001u) /* WDT - Timer Interval Select: /32k */\r
+#define WDTIS_5 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */\r
+#define WDTIS_6 (6*0x0001u) /* WDT - Timer Interval Select: /512 */\r
+#define WDTIS_7 (7*0x0001u) /* WDT - Timer Interval Select: /64 */\r
+#define WDTIS__2G (0*0x0001u) /* WDT - Timer Interval Select: /2G */\r
+#define WDTIS__128M (1*0x0001u) /* WDT - Timer Interval Select: /128M */\r
+#define WDTIS__8192K (2*0x0001u) /* WDT - Timer Interval Select: /8192k */\r
+#define WDTIS__512K (3*0x0001u) /* WDT - Timer Interval Select: /512k */\r
+#define WDTIS__32K (4*0x0001u) /* WDT - Timer Interval Select: /32k */\r
+#define WDTIS__8192 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */\r
+#define WDTIS__512 (6*0x0001u) /* WDT - Timer Interval Select: /512 */\r
+#define WDTIS__64 (7*0x0001u) /* WDT - Timer Interval Select: /64 */\r
+\r
+#define WDTSSEL_0 (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */\r
+#define WDTSSEL_1 (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */\r
+#define WDTSSEL_2 (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */\r
+#define WDTSSEL_3 (3*0x0020u) /* WDT - Timer Clock Source Select: reserved */\r
+#define WDTSSEL__SMCLK (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */\r
+#define WDTSSEL__ACLK (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */\r
+#define WDTSSEL__VLO (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */\r
+\r
+/* WDT-interval times [1ms] coded with Bits 0-2 */\r
+/* WDT is clocked by fSMCLK (assumed 1MHz) */\r
+#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */\r
+#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */\r
+#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */\r
+#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */\r
+/* WDT is clocked by fACLK (assumed 32KHz) */\r
+#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */\r
+#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */\r
+#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */\r
+#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */\r
+/* Watchdog mode -> reset after expired time */\r
+/* WDT is clocked by fSMCLK (assumed 1MHz) */\r
+#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */\r
+#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */\r
+#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */\r
+#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */\r
+/* WDT is clocked by fACLK (assumed 32KHz) */\r
+#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */\r
+#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */\r
+#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */\r
+#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */\r
+\r
+#endif\r
+\r
+/************************************************************\r
+* TLV Descriptors\r
+************************************************************/\r
+#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */\r
+#define TLV_BASE __MSP430_BASEADDRESS_TLV__\r
+\r
+#define TLV_START (0x1A08u) /* Start Address of the TLV structure */\r
+#define TLV_END (0x1AFFu) /* End Address of the TLV structure */\r
+\r
+#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */\r
+#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */\r
+#define TLV_Reserved3 (0x03) /* Future usage */\r
+#define TLV_Reserved4 (0x04) /* Future usage */\r
+#define TLV_BLANK (0x05) /* Blank descriptor */\r
+#define TLV_Reserved6 (0x06) /* Future usage */\r
+#define TLV_Reserved7 (0x07) /* Serial Number */\r
+#define TLV_DIERECORD (0x08) /* Die Record */\r
+#define TLV_ADCCAL (0x11) /* ADC12 calibration */\r
+#define TLV_ADC12CAL (0x11) /* ADC12 calibration */\r
+#define TLV_REFCAL (0x12) /* REF calibration */\r
+#define TLV_ADC10CAL (0x13) /* ADC10 calibration */\r
+#define TLV_TIMERDCAL (0x15) /* TIMER_D calibration */\r
+#define TLV_TAGEXT (0xFE) /* Tag extender */\r
+#define TLV_TAGEND (0xFF) /* Tag End of Table */\r
+\r
+/************************************************************\r
+* Interrupt Vectors (offset from 0xFF80)\r
+************************************************************/\r
+\r
+\r
+/************************************************************\r
+* End of Modules\r
+************************************************************/\r
+#pragma language=default\r
+\r
+#endif /* #ifndef __msp430FR5XX_FR6XXGENERIC */\r
+\r
projects / freertos / blobdiff