--- /dev/null
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// eusci_b_spi.c - Driver for the eusci_b_spi Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup eusci_b_spi_api eusci_b_spi\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_EUSCI_Bx__\r
+#include "eusci_b_spi.h"\r
+\r
+#include <assert.h>\r
+\r
+void EUSCI_B_SPI_initMaster(uint16_t baseAddress,\r
+ EUSCI_B_SPI_initMasterParam *param)\r
+{\r
+ //Disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
+\r
+ //Reset OFS_UCBxCTLW0 values\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCCKPH + UCCKPL + UC7BIT + UCMSB +\r
+ UCMST + UCMODE_3 + UCSYNC);\r
+\r
+ //Reset OFS_UCBxCTLW0 values\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSSEL_3);\r
+\r
+ //Select Clock\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= param->selectClockSource;\r
+\r
+ HWREG16(baseAddress + OFS_UCBxBRW) =\r
+ (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock);\r
+\r
+ /*\r
+ * Configure as SPI master mode.\r
+ * Clock phase select, polarity, msb\r
+ * UCMST = Master mode\r
+ * UCSYNC = Synchronous mode\r
+ * UCMODE_0 = 3-pin SPI\r
+ */\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= (\r
+ param->msbFirst +\r
+ param->clockPhase +\r
+ param->clockPolarity +\r
+ UCMST +\r
+ UCSYNC +\r
+ param->spiMode\r
+ );\r
+}\r
+\r
+void EUSCI_B_SPI_select4PinFunctionality(uint16_t baseAddress,\r
+ uint8_t select4PinFunctionality)\r
+{\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCSTEM;\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= select4PinFunctionality;\r
+}\r
+\r
+void EUSCI_B_SPI_changeMasterClock(uint16_t baseAddress,\r
+ EUSCI_B_SPI_changeMasterClockParam *param)\r
+{\r
+ //Disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
+\r
+ HWREG16(baseAddress + OFS_UCBxBRW) =\r
+ (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock);\r
+\r
+ //Reset the UCSWRST bit to enable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST);\r
+}\r
+\r
+void EUSCI_B_SPI_initSlave(uint16_t baseAddress,\r
+ EUSCI_B_SPI_initSlaveParam *param)\r
+{\r
+ //Disable USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
+\r
+ //Reset OFS_UCBxCTLW0 register\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCMSB +\r
+ UC7BIT +\r
+ UCMST +\r
+ UCCKPL +\r
+ UCCKPH +\r
+ UCMODE_3\r
+ );\r
+\r
+ //Clock polarity, phase select, msbFirst, SYNC, Mode0\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= (param->clockPhase +\r
+ param->clockPolarity +\r
+ param->msbFirst +\r
+ UCSYNC +\r
+ param->spiMode\r
+ );\r
+}\r
+\r
+void EUSCI_B_SPI_changeClockPhasePolarity(uint16_t baseAddress,\r
+ uint16_t clockPhase,\r
+ uint16_t clockPolarity)\r
+{\r
+ //Disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
+\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCCKPH + UCCKPL);\r
+\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= (\r
+ clockPhase +\r
+ clockPolarity\r
+ );\r
+\r
+ //Reset the UCSWRST bit to enable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST);\r
+}\r
+\r
+void EUSCI_B_SPI_transmitData(uint16_t baseAddress,\r
+ uint8_t transmitData)\r
+{\r
+ HWREG16(baseAddress + OFS_UCBxTXBUF) = transmitData;\r
+}\r
+\r
+uint8_t EUSCI_B_SPI_receiveData(uint16_t baseAddress)\r
+{\r
+ return (HWREG16(baseAddress + OFS_UCBxRXBUF));\r
+}\r
+\r
+void EUSCI_B_SPI_enableInterrupt(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ HWREG16(baseAddress + OFS_UCBxIE) |= mask;\r
+}\r
+\r
+void EUSCI_B_SPI_disableInterrupt(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ HWREG16(baseAddress + OFS_UCBxIE) &= ~mask;\r
+}\r
+\r
+uint8_t EUSCI_B_SPI_getInterruptStatus(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ return (HWREG16(baseAddress + OFS_UCBxIFG) & mask);\r
+}\r
+\r
+void EUSCI_B_SPI_clearInterrupt(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ HWREG16(baseAddress + OFS_UCBxIFG) &= ~mask;\r
+}\r
+\r
+void EUSCI_B_SPI_enable(uint16_t baseAddress)\r
+{\r
+ //Reset the UCSWRST bit to enable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST);\r
+}\r
+\r
+void EUSCI_B_SPI_disable(uint16_t baseAddress)\r
+{\r
+ //Set the UCSWRST bit to disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;\r
+}\r
+\r
+uint32_t EUSCI_B_SPI_getReceiveBufferAddress(uint16_t baseAddress)\r
+{\r
+ return (baseAddress + OFS_UCBxRXBUF);\r
+}\r
+\r
+uint32_t EUSCI_B_SPI_getTransmitBufferAddress(uint16_t baseAddress)\r
+{\r
+ return (baseAddress + OFS_UCBxTXBUF);\r
+}\r
+\r
+uint16_t EUSCI_B_SPI_isBusy(uint16_t baseAddress)\r
+{\r
+ //Return the bus busy status.\r
+ return (HWREG16(baseAddress + OFS_UCBxSTATW) & UCBUSY);\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for eusci_b_spi_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r
projects / freertos / blobdiff