Backup Microsemi Renode project before adding a build configuration for the target...

[freertos] / FreeRTOS / Demo / RISC-V_IGLOO2_Creative_SoftConsole / Microsemi_Code / riscv_hal / entry.S

diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/entry.S b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/entry.S
index 1a657feb46682c7eef7ef271ef81f07ba4acf63d..fce18d785643085ee215fb0eaf0dd10433295fd9 100644 (file)
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/entry.S
+++ b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/entry.S
@@ -24,7 +24,7 @@
 #endif\r
 \r
   .section      .text.entry\r
-  .extern vPortTrapHandler\r
+  .extern vFreeRTOSPortTrapHandler\r
   .globl _start\r
 \r
 _start:\r
@@ -34,10 +34,10 @@ nmi_vector:
   j nmi_vector\r
 \r
 trap_vector:\r
-  j vPortTrapHandler\r
+  j vFreeRTOSPortTrapHandler\r
 \r
 handle_reset:\r
-  la t0, vPortTrapHandler\r
+  la t0, vFreeRTOSPortTrapHandler\r
   csrw mtvec, t0\r
   csrwi mstatus, 0\r
   csrwi mie, 0\r