Tidy up the RISC-V_RV32_SiFive_HiFive1_GCC demo ready for its eventual release.

[freertos] / FreeRTOS / Demo / RISC-V_RV32_SiFive_HiFive1_GCC / freedom-metal / src / trap.S

diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_GCC/freedom-metal/src/trap.S b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_GCC/freedom-metal/src/trap.S
index 68103982ac9ac21bb3106d032cb982a80ae8f26b..b55b6656a87786e7f09da2bf7edc2b35429364e7 100644 (file)
--- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_GCC/freedom-metal/src/trap.S
+++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_GCC/freedom-metal/src/trap.S
@@ -28,12 +28,12 @@ _metal_trap:
 
     /* Set MIE=0 */
     li t1, -1
-    xori t1, t1, 8 /*_RB_ METAL_MSTATUS_MIE_SHIFT*/
+    xori t1, t1, METAL_MSTATUS_MIE_SHIFT
     and t0, t0, t1
 
     /* Set MPP=M */
-    li t1, 3 /*_RB_ METAL_MSTATUS_MPP_M*/
-    slli t1, t1, 11 /*_RB_METAL_MSTATUS_MPP_SHIFT*/
+    li t1, METAL_MSTATUS_MPP_M
+    slli t1, t1, METAL_MSTATUS_MPP_SHIFT
     or t0, t0, t1
 
     /* Write mstatus */
@@ -46,7 +46,7 @@ _metal_trap:
      * Mask the mtvec MODE bits
      * Exceptions always jump to mtvec.BASE regradless of the vectoring mode.
      */
-    andi t0, t0, 3 /*_RB_METAL_MTVEC_MODE_MASK*/
+    andi t0, t0, METAL_MTVEC_MODE_MASK
 
     /* Jump to mtvec */
     jr t0