+++ /dev/null
-/***************************************************************/\r
-/* */\r
-/* PROJECT NAME : RTOSDemo */\r
-/* FILE : vector_table.c */\r
-/* DESCRIPTION : Vector Table */\r
-/* CPU SERIES : RX100 */\r
-/* CPU TYPE : RX113 */\r
-/* */\r
-/* This file is generated by e2 studio. */\r
-/* */\r
-/***************************************************************/ \r
- \r
- \r
-/************************************************************************/\r
-/* File Version: V1.00 */\r
-/* Date Generated: 20/08/2014 */\r
-/************************************************************************/\r
-\r
-#include "interrupt_handlers.h"\r
-\r
-typedef void (*fp) (void);\r
-extern void PowerON_Reset (void);\r
-extern void stack (void);\r
-extern void vPortSoftwareInterruptISR( void );\r
-extern void vPortTickISR( void );\r
-extern void vIntQTimerISR0( void );\r
-extern void vIntQTimerISR1( void );\r
-\r
-#define FVECT_SECT __attribute__ ((section (".fvectors")))\r
-\r
-const void *HardwareVectors[] FVECT_SECT = {\r
-//;0xffffff80 MDES Endian Select Register\r
-#ifdef __RX_LITTLE_ENDIAN__ \r
-(fp)0xffffffff,\r
-#endif\r
-#ifdef __RX_BIG_ENDIAN__ \r
-(fp)0xfffffff8,\r
-#endif\r
-//;0xffffff84 Reserved\r
- (fp)0, \r
-//;0xffffff88 OFS1\r
- (fp)0xFFFFFFFF,\r
-//;0xffffff8C OFS0\r
- (fp)0xFFFFFFFF,\r
-//;0xffffff90 Reserved\r
- (fp)0, \r
-//;0xffffff94 Reserved\r
- (fp)0, \r
-//;0xffffff98 Reserved\r
- (fp)0, \r
-//;0xffffff9C Reserved\r
- (fp)0, \r
-//;0xffffffA0 Reserved\r
- (fp)0,\r
- //;0xffffffA4 Reserved\r
- (fp)0,\r
-//;0xffffffA8 Reserved\r
- (fp)0,\r
-//;0xffffffAC Reserved\r
- (fp)0,\r
-//;0xffffffB0 Reserved\r
- (fp)0,\r
-//;0xffffffB4 Reserved\r
- (fp)0,\r
-//;0xffffffB8 Reserved\r
- (fp)0,\r
-//;0xffffffBC Reserved\r
- (fp)0,\r
-//;0xffffffC0 Reserved\r
- (fp)0,\r
-//;0xffffffC4 Reserved\r
- (fp)0,\r
-//;0xffffffC8 Reserved\r
- (fp)0,\r
-//;0xffffffCC Reserved\r
- (fp)0,\r
-//;0xffffffd0 Exception(Supervisor Instruction)\r
- INT_Excep_SuperVisorInst,\r
-//;0xffffffd4 Reserved\r
- (fp)0,\r
-//;0xffffffd8 Reserved\r
- (fp)0,\r
-//;0xffffffdc Exception(Undefined Instruction)\r
- INT_Excep_UndefinedInst,\r
-//;0xffffffe0 Reserved\r
- (fp)0,\r
-//;0xffffffe4 Reserved\r
- (fp)0,\r
-//;0xffffffe8 Reserved\r
- (fp)0,\r
-//;0xffffffec Reserved\r
- (fp)0,\r
-//;0xfffffff0 Reserved\r
- (fp)0,\r
-//;0xfffffff4 Reserved\r
- (fp)0,\r
-//;0xfffffff8 NMI\r
- INT_NonMaskableInterrupt,\r
-//;0xfffffffc RESET\r
-//;<<VECTOR DATA START (POWER ON RESET)>>\r
-//;Power On Reset PC\r
- PowerON_Reset \r
-//;<<VECTOR DATA END (POWER ON RESET)>>\r
-};\r
-#define RVECT_SECT __attribute__ ((section (".rvectors")))\r
-\r
-const fp RelocatableVectors[] RVECT_SECT = {\r
-//;0x0000 BRK\r
- (fp)INT_Excep_BRK,\r
-//;0x0004 Reserved\r
- (fp)0,\r
-//;0x0008 Reserved\r
- (fp)0,\r
-//;0x000C Reserved\r
- (fp)0,\r
-//;0x0010 Reserved\r
- (fp)0,\r
-//;0x0014 Reserved\r
- (fp)0,\r
-//;0x0018 Reserved\r
- (fp)0,\r
-//;0x001C Reserved\r
- (fp)0,\r
-//;0x0020 Reserved\r
- (fp)0,\r
-//;0x0024 Reserved\r
- (fp)0,\r
-//;0x0028 Reserved\r
- (fp)0,\r
-//;0x002C Reserved\r
- (fp)0,\r
-//;0x0030 Reserved\r
- (fp)0,\r
-//;0x0034 Reserved\r
- (fp)0,\r
-//;0x0038 Reserved\r
- (fp)0,\r
-//;0x003C Reserved\r
- (fp)0,\r
-//;0x0040 BSC_BUSERR\r
- (fp)INT_Excep_BSC_BUSERR,\r
-//;0x0044 Reserved\r
- (fp)0,\r
-//;0x0048 Reserved\r
- (fp)0,\r
-//;0x004C Reserved\r
- (fp)0,\r
-//;0x0050 Reserved\r
- (fp)0,\r
-//;0x0054 FCUERR\r
- (fp)0,\r
-//;0x0058 Reserved\r
- (fp)0,\r
-//;0x005C FRDYI\r
- (fp)INT_Excep_FCU_FRDYI,\r
-//;0x0060 Reserved\r
- (fp)0,\r
-//;0x0064 Reserved\r
- (fp)0,\r
-//;0x0068 Reserved\r
- (fp)0,\r
-//;0x006C ICU_SWINT\r
- (fp)vPortSoftwareInterruptISR,\r
-//;0x0070 CMT0_CMI0\r
- (fp)vPortTickISR,\r
-//;0x0074 CMT1_CMI1\r
- (fp)INT_Excep_CMT1_CMI1,\r
-//;0x0078 CMT2_CMI2\r
- (fp)INT_Excep_CMT2_CMI2,\r
-//;0x007C CMT3_CMI3\r
- (fp)INT_Excep_CMT3_CMI3,\r
-//;0x0080 CAC_FERRF\r
- (fp)INT_Excep_CAC_FERRF,\r
-//;0x0084 CAC_MENDF\r
- (fp)INT_Excep_CAC_MENDF,\r
-//;0x0088 CAC_OVFF\r
- (fp)INT_Excep_CAC_OVFF,\r
-//;0x008C Reserved\r
- (fp)0,\r
-//;0x0090 USB0_D0FIFO0\r
- (fp)INT_Excep_USB0_D0FIFO0,\r
-//;0x0094 USB0_D1FIFO0\r
- (fp)INT_Excep_USB0_D1FIFO0,\r
-//;0x0098 USB0_USBI0\r
- (fp)INT_Excep_USB0_USBI0,\r
-//;0x009C Reserved\r
- (fp)0,\r
-//;0x00A0 Reserved\r
- (fp)0,\r
-//;0x00A4 Reserved\r
- (fp)0,\r
-//;0x00A8 Reserved\r
- (fp)0,\r
-//;0x00AC Reserved\r
- (fp)0,\r
-//;0x00B0 RSPI0_SPEI0\r
- (fp)INT_Excep_RSPI0_SPEI0,\r
-//;0x00B4 RSPI0_SPRI0\r
- (fp)INT_Excep_RSPI0_SPRI0,\r
-//;0x00B8 RSPI0_SPTI0\r
- (fp)INT_Excep_RSPI0_SPTI0,\r
-//;0x00BC RSPI0_SPII0\r
- (fp)INT_Excep_RSPI0_SPII0,\r
-//;0x00C0 Reserved\r
- (fp)0,\r
-//;0x00C4 Reserved\r
- (fp)0,\r
-//;0x00C8 Reserved\r
- (fp)0,\r
-//;0x00CC Reserved\r
- (fp)0,\r
-//;0x00D0 Reserved\r
- (fp)0,\r
-//;0x00D4 Reserved\r
- (fp)0,\r
-//;0x00D8 Reserved\r
- (fp)0,\r
-//;0x00DC Reserved\r
- (fp)0,\r
-//;0x00E0 Reserved\r
- (fp)0,\r
-//;0x00E4 DOC_DOPCF\r
- (fp)INT_Excep_DOC_DOPCF,\r
-//;0x00E8 CMPB_CMPB0\r
- (fp)INT_Excep_CMPB_CMPB0,\r
-//;0x00EC CMPB_CMPB1\r
- (fp)INT_Excep_CMPB_CMPB1,\r
-//;0x00F0 CTSU_CTSUWR\r
- (fp)INT_Excep_CTSU_CTSUWR,\r
-//;0x00F4 CTSU_CTSURD\r
- (fp)INT_Excep_CTSU_CTSURD,\r
-//;0x00F8 CTSU_CTSUFN\r
- (fp)INT_Excep_CTSU_CTSUFN,\r
-//;0x00FC Excep_RTC_CUP\r
- (fp)INT_Excep_RTC_CUP,\r
-//;0x0100 IRQ0\r
- (fp)INT_Excep_ICU_IRQ0,\r
-//;0x0104 IRQ1\r
- (fp)INT_Excep_ICU_IRQ1,\r
-//;0x0108 IRQ2\r
- (fp)INT_Excep_ICU_IRQ2,\r
-//;0x010C IRQ3\r
- (fp)INT_Excep_ICU_IRQ3,\r
-//;0x0110 IRQ4\r
- (fp)INT_Excep_ICU_IRQ4,\r
-//;0x0114 IRQ5\r
- (fp)INT_Excep_ICU_IRQ5,\r
-//;0x0118 IRQ6\r
- (fp)INT_Excep_ICU_IRQ6,\r
-//;0x011C IRQ7\r
- (fp)INT_Excep_ICU_IRQ7,\r
-//;0x0120 Reserved\r
- (fp)0,\r
-//;0x0124 Reserved\r
- (fp)0,\r
-//;0x0128 Reserved\r
- (fp)0,\r
-//;0x012C Reserved\r
- (fp)0,\r
-//;0x0130 Reserved\r
- (fp)0,\r
-//;0x0134 Reserved\r
- (fp)0,\r
-//;0x0138 Reserved\r
- (fp)0,\r
-//;0x013C Reserved\r
- (fp)0,\r
-//;0x0140 ELC ELSR8I\r
- (fp)INT_Excep_ELC_ELSR8I,\r
-//;0x0144 Reserved\r
- (fp)0,\r
-//;0x0148 Reserved\r
- (fp)0,\r
-//;0x014C Reserved\r
- (fp)0,\r
-//;0x0150 Reserved\r
- (fp)0,\r
-//;0x0154 Reserved\r
- (fp)0,\r
-//;0x0158 Reserved\r
- (fp)0,\r
-//;0x015C Reserved\r
- (fp)0,\r
-//;0x0160 LVD_LVD1\r
- (fp)INT_Excep_LVD_LVD1,\r
-//;0x0164 LVD_LVD2\r
- (fp)INT_Excep_LVD_LVD2,\r
-//;0x0168 USB0_USBR0\r
- (fp)INT_Excep_USB0_USBR0,\r
-//;0x016C Reserved\r
- (fp)0,\r
-//;0x0170 RTC_ALM\r
- (fp)INT_Excep_RTC_ALM,\r
-//;0x0174 RTC_PRD\r
- (fp)INT_Excep_RTC_PRD,\r
-//;0x0178 Reserved\r
- (fp)0,\r
-//;0x017C Reserved\r
- (fp)0,\r
-//;0x0180 Reserved\r
- (fp)0,\r
-//;0x0184 Reserved\r
- (fp)0,\r
-//;0x0188 Reserved\r
- (fp)0,\r
-//;0x018C Reserved\r
- (fp)0,\r
-//;0x0190 Reserved\r
- (fp)0,\r
-//;0x0194 Reserved\r
- (fp)0,\r
-//;0x0198 S12AD_S12ADI0 \r
- (fp)INT_Excep_S12AD_S12ADI0,\r
-//;0x019C S12AD_GBADI \r
- (fp)INT_Excep_S12AD_GBADI,\r
-//104;0x01A0 Reserved \r
- (fp)0,\r
-//105;0x01A4 Reserved \r
- (fp)0,\r
-//;0x01A8 ELC_ELSR18I\r
- (fp)INT_Excep_ELC_ELSR18I,\r
-//;0x01AC Reserved\r
- (fp)0,\r
-//;0x01B0 SSI0_SSIF0\r
- (fp)INT_Excep_SSI0_SSIF0,\r
-//;0x01B4 SSI0_SSIRXI0\r
- (fp)INT_Excep_SSI0_SSIRXI0,\r
-//;0x01B8 SSI0_SSITXI0\r
- (fp)INT_Excep_SSI0_SSITXI0,\r
-//;0x01BC Reserved\r
- (fp)0,\r
-//;0x01C0 Reserved\r
- (fp)0,\r
-//;0x01C4 Reserved\r
- (fp)0,\r
-//;0x01C8 MTU0_TGIA0 \r
- (fp)INT_Excep_MTU0_TGIA0,\r
-//;0x01CC MTU0_TGIB0 \r
- (fp)INT_Excep_MTU0_TGIB0,\r
-//;0x01D0 MTU0_TGIC0 \r
- (fp)INT_Excep_MTU0_TGIC0,\r
-//;0x01D4 MTU0_TGID0 \r
- (fp)INT_Excep_MTU0_TGID0,\r
-//;0x01D8 MTU0_TCIV0 \r
- (fp)INT_Excep_MTU0_TCIV0,\r
-//;0x01DC MTU0_TGIE0 \r
- (fp)INT_Excep_MTU0_TGIE0,\r
-//;0x01E0 MTU0_TGIF0 \r
- (fp)INT_Excep_MTU0_TGIF0, \r
-//;0x01E4 MTU1_TGIA1 \r
- (fp)INT_Excep_MTU1_TGIA1,\r
-//;0x01E8 MTU1_TGIB1 \r
- (fp)INT_Excep_MTU1_TGIB1,\r
-//;0x01EC MTU1_TCIV1 \r
- (fp)INT_Excep_MTU1_TCIV1,\r
-//;0x01F0 MTU1_TCIU1 \r
- (fp)INT_Excep_MTU1_TCIU1, \r
-//;0x01F4 MTU2_TGIA2 \r
- (fp)INT_Excep_MTU2_TGIA2,\r
-//;0x01F8 MTU2_TGIB2 \r
- (fp)INT_Excep_MTU2_TGIB2,\r
-//;0x01FC MTU2_TCIV2 \r
- (fp)INT_Excep_MTU2_TCIV2,\r
-//;0x0200 MTU2_TCIU2 \r
- (fp)INT_Excep_MTU2_TCIU2, \r
-//;0x0204 MTU3_TGIA3 \r
- (fp)INT_Excep_MTU3_TGIA3,\r
-//;0x0208 MTU3_TGIB3 \r
- (fp)INT_Excep_MTU3_TGIB3,\r
-//;0x020C MTU3_TGIC3 \r
- (fp)INT_Excep_MTU3_TGIC3,\r
-//;0x0210 MTU3_TGID3 \r
- (fp)INT_Excep_MTU3_TGID3,\r
-//;0x0214 MTU3_TCIV3 \r
- (fp)INT_Excep_MTU3_TCIV3, \r
-//;0x0218 MTU4_TGIA4 \r
- (fp)INT_Excep_MTU4_TGIA4,\r
-//;0x021C MTU4_TGIB4 \r
- (fp)INT_Excep_MTU4_TGIB4,\r
-//;0x0220 MTU4_TGIC4 \r
- (fp)INT_Excep_MTU4_TGIC4,\r
-//;0x0224 MTU4_TGID4 \r
- (fp)INT_Excep_MTU4_TGID4,\r
-//;0x0228 MTU4_TCIV4 \r
- (fp)INT_Excep_MTU4_TCIV4, \r
-//;0x022C MTU5_TGIU5 \r
- (fp)INT_Excep_MTU5_TGIU5,\r
-//;0x0230 MTU5_TGIV5 \r
- (fp)INT_Excep_MTU5_TGIV5,\r
-//;0x0234 MTU5_TGIW5 \r
- (fp)INT_Excep_MTU5_TGIW5,\r
-//;0x0238 Reserved\r
- (fp)0,\r
-//;0x023C Reserved\r
- (fp)0,\r
-//;0x0240 Reserved\r
- (fp)0,\r
-//;0x0244 Reserved\r
- (fp)0,\r
-//;0x0248 Reserved\r
- (fp)0,\r
-//;0x024C Reserved\r
- (fp)0,\r
-//;0x0250 Reserved\r
- (fp)0,\r
-//;0x0254 Reserved\r
- (fp)0,\r
-//;0x0258 Reserved\r
- (fp)0,\r
-//;0x025C Reserved\r
- (fp)0,\r
-//;0x0260 Reserved\r
- (fp)0,\r
-//;0x0264 Reserved\r
- (fp)0,\r
-//;0x0268 Reserved\r
- (fp)0,\r
-//;0x026C Reserved\r
- (fp)0,\r
-//;0x0270 Reserved\r
- (fp)0,\r
-//;0x0274 Reserved\r
- (fp)0,\r
-//;0x0278 Reserved\r
- (fp)0,\r
-//;0x027C Reserved\r
- (fp)0,\r
-//;0x0280 Reserved\r
- (fp)0,\r
-//;0x0284 Reserved\r
- (fp)0,\r
-//;0x0288 Reserved\r
- (fp)0,\r
-//;0x028C Reserved\r
- (fp)0,\r
-//;0x0290 Reserved\r
- (fp)0,\r
-//;0x0294 Reserved\r
- (fp)0,\r
-//;0x0298 Reserved\r
- (fp)0,\r
-//;0x029C Reserved\r
- (fp)0,\r
-//;0x02A0 Reserved\r
- (fp)0,\r
-//;0x02A4 Reserved\r
- (fp)0,\r
-//;0x02A8 POE_OEI1\r
- (fp)INT_Excep_POE_OEI1,\r
-//;0x02AC POE_OEI2\r
- (fp)INT_Excep_POE_OEI2,\r
-//;0x02B0 Reserved\r
- (fp)0,\r
-//;0x02B4 Reserved\r
- (fp)0,\r
-//;0x02B8 TMR0_CMIA0\r
- (fp)vIntQTimerISR0,\r
-//;0x02BC TMR0_CMIB0\r
- (fp)INT_Excep_TMR0_CMIB0,\r
-//;0x02C0 TMR0_OVI0\r
- (fp)INT_Excep_TMR0_OVI0,\r
-//;0x02C4 TMR1_CMIA1\r
- (fp)INT_Excep_TMR1_CMIA1,\r
-//;0x02C8 TMR1_CMIB1\r
- (fp)INT_Excep_TMR1_CMIB1,\r
-//;0x02CC TMR1_OVI1\r
- (fp)INT_Excep_TMR1_OVI1,\r
-//;0x02D0 TMR2_CMIA2\r
- (fp)vIntQTimerISR1,\r
-//;0x02D4 TMR2_CMIB2\r
- (fp)INT_Excep_TMR2_CMIB2,\r
-//;0x02D8 TMR2_OVI2\r
- (fp)INT_Excep_TMR2_OVI2,\r
-//;0x02DC TMR3_CMIA3\r
- (fp)INT_Excep_TMR3_CMIA3,\r
-//;0x02E0 TMR3_CMIB3\r
- (fp)INT_Excep_TMR3_CMIB3,\r
-//;0x02E4 TMR3_OVI3\r
- (fp)INT_Excep_TMR3_OVI3,\r
-//;0x02E8 SCI2_ERI2\r
- (fp)INT_Excep_SCI2_ERI2,\r
-//;0x02EC SCI2_RXI2\r
- (fp)INT_Excep_SCI2_RXI2,\r
-//;0x02F0 SCI2_TXI2\r
- (fp)INT_Excep_SCI2_TXI2,\r
-//;0x02F4 SCI2_TEI2\r
- (fp)INT_Excep_SCI2_TEI2,\r
-//;0x02F8 Reserved\r
- (fp)0,\r
-//;0x02FC Reserved\r
- (fp)0,\r
-//;0x0300 Reserved\r
- (fp)0,\r
-//;0x0304 Reserved\r
- (fp)0,\r
-//;0x0308 Reserved\r
- (fp)0,\r
-//;0x030C Reserved\r
- (fp)0,\r
-//;0x0310 Reserved\r
- (fp)0,\r
-//;0x0314 Reserved\r
- (fp)0,\r
-//;0x0318 Reserved\r
- (fp)0,\r
-//;0x031C Reserved\r
- (fp)0,\r
-//;0x0320 Reserved\r
- (fp)0,\r
-//;0x0324 Reserved\r
- (fp)0,\r
-//;0x0328 Reserved\r
- (fp)0,\r
-//;0x032C Reserved\r
- (fp)0,\r
-//;0x0330 Reserved\r
- (fp)0,\r
-//;0x0334 Reserved\r
- (fp)0,\r
-//;0x0338 Reserved\r
- (fp)0,\r
-//;0x033C Reserved\r
- (fp)0,\r
-//;0x0340 Reserved\r
- (fp)0,\r
-//;0x0344 Reserved\r
- (fp)0,\r
-//;0x0348 Reserved\r
- (fp)0,\r
-//;0x034C Reserved\r
- (fp)0,\r
-//;0x0350 Reserved\r
- (fp)0,\r
-//;0x0354 Reserved\r
- (fp)0,\r
-//;0x0358 SCI0_ERI0\r
- (fp)INT_Excep_SCI0_ERI0,\r
-//;0x035C SCI0_RXI0\r
- (fp)INT_Excep_SCI0_RXI0,\r
-//;0x0360 SCI0_TXI0\r
- (fp)INT_Excep_SCI0_TXI0,\r
-//;0x0364 SCI0_TEI0\r
- (fp)INT_Excep_SCI0_TEI0,\r
-//;0x0368 SCI1_ERI1\r
- (fp)INT_Excep_SCI1_ERI1,\r
-//;0x036C SCI1_RXI1\r
- (fp)INT_Excep_SCI1_RXI1,\r
-//;0x0370 SCI1_TXI1\r
- (fp)INT_Excep_SCI1_TXI1,\r
-//;0x0374 SCI1_TEI1\r
- (fp)INT_Excep_SCI1_TEI1,\r
-//;0x0378 SCI5_ERI5\r
- (fp)INT_Excep_SCI5_ERI5,\r
-//;0x037C SCI5_RXI5\r
- (fp)INT_Excep_SCI5_RXI5,\r
-//;0x0380 SCI5_TXI5\r
- (fp)INT_Excep_SCI5_TXI5,\r
-//;0x0384 SCI5_TEI5\r
- (fp)INT_Excep_SCI5_TEI5,\r
-//;0x0388 SCI6_ERI6\r
- (fp)INT_Excep_SCI6_ERI6,\r
-//;0x038C SCI6_RXI6\r
- (fp)INT_Excep_SCI6_RXI6,\r
-//;0x0390 SCI6_TXI6\r
- (fp)INT_Excep_SCI6_TXI6,\r
-//;0x0394 SCI6_TEI6\r
- (fp)INT_Excep_SCI6_TEI6,\r
-//;0x0398 SCI8_ERI8\r
- (fp)INT_Excep_SCI8_ERI8,\r
-//;0x039C SCI8_RXI8\r
- (fp)INT_Excep_SCI8_RXI8,\r
-//;0x03A0 SCI8_TXI8\r
- (fp)INT_Excep_SCI8_TXI8,\r
-//;0x03A4 SCI8_TEI8\r
- (fp)INT_Excep_SCI8_TEI8,\r
-//;0x03A8 SCI9_ERI9\r
- (fp)INT_Excep_SCI9_ERI9,\r
-//;0x03AC SCI9_RXI9\r
- (fp)INT_Excep_SCI9_RXI9,\r
-//;0x03B0 SCI9_TXI9\r
- (fp)INT_Excep_SCI9_TXI9,\r
-//;0x03B4 SCI9_TEI9\r
- (fp)INT_Excep_SCI9_TEI9,\r
-//;0x03B8 SCI12_ERI12\r
- (fp)INT_Excep_SCI12_ERI12,\r
-//;0x03BC SCI12_RXI12\r
- (fp)INT_Excep_SCI12_RXI12,\r
-//;0x03C0 SCI12_TXI12\r
- (fp)INT_Excep_SCI12_TXI12,\r
-//;0x03C4 SCI12_TEI12\r
- (fp)INT_Excep_SCI12_TEI12,\r
-//;0x03C8 SCI12_SCIX0\r
- (fp)INT_Excep_SCI12_SCIX0,\r
-//;0x03CC SCI12_SCIX1\r
- (fp)INT_Excep_SCI12_SCIX1,\r
-//;0x03D0 SCI12_SCIX2\r
- (fp)INT_Excep_SCI12_SCIX2,\r
-//;0x03D4 SCI12_SCIX3\r
- (fp)INT_Excep_SCI12_SCIX3,\r
-//;0x03D8 RIIC0_EEI0\r
- (fp)INT_Excep_RIIC0_EEI0,\r
-//;0x03DC RIIC0_RXI0\r
- (fp)INT_Excep_RIIC0_RXI0,\r
-//;0x03E0 RIIC0_TXI0\r
- (fp)INT_Excep_RIIC0_TXI0,\r
-//;0x03E4 RIIC0_TEI0\r
- (fp)INT_Excep_RIIC0_TEI0,\r
-//;0x03E8 Reserved\r
- (fp)0,\r
-//;0x03EC Reserved\r
- (fp)0,\r
-//;0x03F0 Reserved\r
- (fp)0,\r
-//;0x03F4 Reserved\r
- (fp)0,\r
-//;0x03F8 Reserved\r
- (fp)0,\r
-//;0x03FC Reserved\r
- (fp)0,\r
-};\r
projects / freertos / blobdiff