+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_cgc.h\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for CGC module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-#ifndef CGC_H\r
-#define CGC_H\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions (Register bit)\r
-***********************************************************************************************************************/\r
-/*\r
- System Clock Control Register (SCKCR)\r
-*/\r
-/* Peripheral Module Clock D (PCLKD) */\r
-#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */\r
-#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */\r
-#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */\r
-#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */\r
-#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */\r
-#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */\r
-#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */\r
-/* Peripheral Module Clock B (PCLKB) */\r
-#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */\r
-#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */\r
-#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */\r
-#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */\r
-#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */\r
-#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */\r
-#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */\r
-/* System Clock (ICLK) */\r
-#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */\r
-#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */\r
-#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */\r
-#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */\r
-#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */\r
-#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */\r
-#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */\r
-/* System Clock (FCLK) */\r
-#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */\r
-#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */\r
-#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */\r
-#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */\r
-#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */\r
-#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */\r
-#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */\r
-\r
-/*\r
- System Clock Control Register 3 (SCKCR3)\r
-*/\r
-#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */\r
-#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */\r
-#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */\r
-#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */\r
-#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */\r
-\r
-/*\r
- PLL Control Register (PLLCR)\r
-*/\r
-/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */\r
-#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */\r
-#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */\r
-#define _0002_CGC_PLL_FREQ_DIV_4 (0x0002U) /* x1/4 */\r
-/* Frequency Multiplication Factor Select (STC[5:0]) */\r
-#define _0B00_CGC_PLL_FREQ_MUL_6 (0x0B00U) /* x6 */\r
-#define _0F00_CGC_PLL_FREQ_MUL_8 (0x0F00U) /* x8 */\r
-\r
-/*\r
- USB-dedicated PLL Control Register (UPLLCR)\r
-*/\r
-/* USB-dedicated PLL Input Frequency Division Ratio Select (UPLIDIV[1:0]) */\r
-#define _0000_CGC_PLL_UPLIDIV_1 (0x0000U) /* x1 */\r
-#define _0001_CGC_PLL_UPLIDIV_2 (0x0001U) /* x1/2 */\r
-#define _0002_CGC_PLL_UPLIDIV_4 (0x0002U) /* x1/4 */\r
-/* UCLK Source USB-Dedicated PLL Select (UCKUPLLSEL) */\r
-#define _0000_CGC_UCLK_SYSCLK (0x0000U) /* System clock is selected as UCLK */\r
-#define _0010_CGC_UCLK_USBPLL (0x0010U) /* USB-dedicated PLL is selected as UCLK */\r
-/* Frequency Multiplication Factor Select (USTC[5:0]) */\r
-#define _0B00_CGC_PLL_USTC_6 (0x0B00U) /* x6 */\r
-#define _0F00_CGC_PLL_USTC_8 (0x0F00U) /* x8 */\r
-\r
-/*\r
- Oscillation Stop Detection Control Register (OSTDCR)\r
-*/\r
-/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */\r
-#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */\r
-#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */\r
-/* Oscillation Stop Detection Function Enable (OSTDE) */\r
-#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */\r
-#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */\r
-\r
-/*\r
- Main Clock Oscillator Wait Control Register (MOSCWTCR)\r
-*/\r
-/* Main Clock Oscillator Wait Time (MSTS[4:0]) */\r
-#define _00_CGC_OSC_WAIT_CYCLE_2 (0x00U) /* Wait time = 2 cycles */\r
-#define _01_CGC_OSC_WAIT_CYCLE_1024 (0x01U) /* Wait time = 1024 cycles */\r
-#define _02_CGC_OSC_WAIT_CYCLE_2048 (0x02U) /* Wait time = 2048 cycles */\r
-#define _03_CGC_OSC_WAIT_CYCLE_4096 (0x03U) /* Wait time = 4096 cycles */\r
-#define _04_CGC_OSC_WAIT_CYCLE_8192 (0x04U) /* Wait time = 8192 cycles */\r
-#define _05_CGC_OSC_WAIT_CYCLE_16384 (0x05U) /* Wait time = 16384 cycles */\r
-#define _06_CGC_OSC_WAIT_CYCLE_32768 (0x06U) /* Wait time = 32768 cycles */\r
-#define _07_CGC_OSC_WAIT_CYCLE_65536 (0x07U) /* Wait time = 65536 cycles */\r
-\r
-/*\r
- HOCO Wait Control Register (HOCOWTCR)\r
-*/\r
-/* HOCO Wait Time (HOCOWTCR) */\r
-#define _05_CGC_HOCO_WAIT_CYCLE_138 (0x05U) /* Wait time = 138 cycles (34.5us) */\r
-#define _06_CGC_HOCO_WAIT_CYCLE_266 (0x06U) /* Wait time = 266 cycles (66.5us) */\r
-\r
-/*\r
- Clock Output Control Register (CKOCR)\r
-*/\r
-/* Clock Output Source Select (CKOSEL[2:0]) */\r
-#define _0000_CGC_CLKOUT_LOCO (0x0000U) /* LOCO */\r
-#define _0100_CGC_CLKOUT_HOCO (0x0100U) /* HOCO */\r
-#define _0200_CGC_CLKOUT_MAINCLK (0x0200U) /* Main clock oscillator */\r
-#define _0300_CGC_CLKOUT_SUBCLK (0x0300U) /* Sub-clock oscillator */\r
-/* Clock Output Division Ratio Select (CKODIV[2:0]) */\r
-#define _0000_CGC_CLKOUT_DIV_1 (0x0000U) /* x1 */\r
-#define _1000_CGC_CLKOUT_DIV_2 (0x1000U) /* x1/2 */\r
-#define _2000_CGC_CLKOUT_DIV_4 (0x2000U) /* x1/4 */\r
-#define _3000_CGC_CLKOUT_DIV_8 (0x3000U) /* x1/8 */\r
-#define _4000_CGC_CLKOUT_DIV_16 (0x4000U) /* x1/16 */\r
-/* Clock Output Control (CKOSTP) */\r
-#define _0000_CGC_CLKOUT_ENABLE (0x0000U) /* CLKOUT pin output is operating */\r
-#define _8000_CGC_CLKOUT_DISABLE (0x8000U) /* CLKOUT pin output is stopped (fixed at low level) */\r
-\r
-/*\r
- Main Clock Oscillator Forced Oscillation Control Register (MOFCR)\r
-*/\r
-/* Main Oscillator Drive Capability Switch (MODRV21) */\r
-#define _00_CGC_MAINOSC_UNDER10M (0x00U) /* 1 MHz to 10 MHz */\r
-#define _20_CGC_MAINOSC_OVER10M (0x20U) /* 10 MHz to 20 MHz */\r
-/* Main Clock Oscillator Switch (MOSEL) */\r
-#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */\r
-#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */\r
-\r
-/*\r
- LCD Source Clock Control Register (LCDSCLKCR)\r
-*/\r
-/* LCD Source Clock Select (LCDSCLKSEL[2:0]) */\r
-#define _00_CGC_LCDSCLKSEL_LOCO (0x00U) /* LOCO */\r
-#define _01_CGC_LCDSCLKSEL_HOCO (0x01U) /* HOCO */\r
-#define _02_CGC_LCDSCLKSEL_MAINCLK (0x02U) /* Main clock oscillator */\r
-#define _03_CGC_LCDSCLKSEL_SUBCLK (0x03U) /* Sub-clock oscillator */\r
-#define _04_CGC_LCDSCLKSEL_IWDT (0x04U) /* IWDT-dedicated on-chip oscillator */\r
-\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions\r
-***********************************************************************************************************************/\r
-#define _007B_CGC_SUBSTPWT_WAIT (0x007BU) /* Wait time for 5 sub clock cycles */\r
-#define _00061A81_CGC_SUBOSCWT_WAIT (0x00061A81U) /* Wait time for sub clock stable */\r
-\r
-/***********************************************************************************************************************\r
-Typedef definitions\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Global functions\r
-***********************************************************************************************************************/\r
-void R_CGC_Create(void);\r
-\r
-/* Start user code for function. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#endif
\ No newline at end of file
projects / freertos / blobdiff