--- /dev/null
+/*---------------------------------------------------------------------------*/\r
+/* - defaults.s - */\r
+/* */\r
+/* This module contains default values for the following symbols */\r
+/* */\r
+/* For RxV1 core: */\r
+/* __MDES @ 0xFFFFFF80 to 0xFFFFFF83 */\r
+/* __OFS1 @ 0xFFFFFF88 to 0xFFFFFF8B */\r
+/* __OFS0 @ 0xFFFFFF8C to 0xFFFFFF8F */\r
+/* __ROM_CODE @ 0xFFFFFF9C */\r
+/* __ID_BYTES_1_4 @ 0xFFFFFFA0 to 0xFFFFFFA3 */\r
+/* __ID_BYTES_5_8 @ 0xFFFFFFA4 to 0xFFFFFFA7 */\r
+/* __ID_BYTES_9_12 @ 0xFFFFFFA8 to 0xFFFFFFAB */\r
+/* __ID_BYTES_13_16 @ 0xFFFFFFAC to 0xFFFFFFAF */\r
+/* */\r
+/* For RxV1 core: */\r
+/* __MDES @ 0xFFFFFF80 to 0xFFFFFF83 */\r
+/* __OFS1 @ 0xFFFFFF88 to 0xFFFFFF8B */\r
+/* __OFS0 @ 0xFFFFFF8C to 0xFFFFFF8F */\r
+/* __ROM_CODE @ 0xFFFFFF9C to 0xFFFFFF9F */\r
+/* __OSIS_1 @ 0xFFFFFFA0 to 0xFFFFFFA3 */\r
+/* __OSIS_2 @ 0xFFFFFFA4 to 0xFFFFFFA7 */\r
+/* __OSIS_3 @ 0xFFFFFFA8 to 0xFFFFFFAB */\r
+/* __OSIS_4 @ 0xFFFFFFAC to 0xFFFFFFAF */\r
+/* */\r
+/* For RxV2 core (RX64M): */\r
+/* __SPCC @ 0x00120040 to 0x00120043 */\r
+/* __TMEF @ 0x00120048 to 0x0012004B */\r
+/* __OSIS_1 @ 0x00120050 to 0x00120053 */\r
+/* __OSIS_2 @ 0x00120054 to 0x00120057 */\r
+/* __OSIS_3 @ 0x00120058 to 0x0012005D */\r
+/* __OSIS_4 @ 0x0012005C to 0x0012005F */\r
+/* __TMINF @ 0x00120060 to 0x00120063 */\r
+/* __MDE @ 0x00120064 to 0x00120067 */\r
+/* __OFS0 @ 0x00120068 to 0x0012006B */\r
+/* __OFS1 @ 0x0012006C to 0x0012006F */\r
+/* */\r
+/* To override default values in library add this file to your */\r
+/* project and change the values. */\r
+/* */\r
+/* Copyright 2014 IAR Systems AB. */\r
+/* */\r
+/* $Revision: 6046 $ */\r
+/* */\r
+/*---------------------------------------------------------------------------*/\r
+\r
+ MODULE DEFAULTS\r
+ SECTION .text:CONST:NOROOT\r
+\r
+#if __CORE__ == __CORE_V1__\r
+ PUBWEAK __MDES\r
+ PUBWEAK __OFS1\r
+ PUBWEAK __OFS0\r
+ PUBWEAK __ROM_CODE\r
+ PUBWEAK __ID_BYTES_1_4\r
+ PUBWEAK __ID_BYTES_5_8\r
+ PUBWEAK __ID_BYTES_9_12\r
+ PUBWEAK __ID_BYTES_13_16\r
+#if __LITTLE_ENDIAN__\r
+__MDES equ 0xffffffff\r
+#else\r
+__MDES equ 0xfffffff8\r
+#endif\r
+__OFS0 equ 0xffffffff\r
+__OFS1 equ 0xffffffff\r
+__ROM_CODE equ 0xffffffff\r
+__ID_BYTES_1_4 equ 0xffffffff\r
+__ID_BYTES_5_8 equ 0xffffffff\r
+__ID_BYTES_9_12 equ 0xffffffff\r
+__ID_BYTES_13_16 equ 0xffffffff\r
+\r
+#else /* __CORE__ == __CORE_V2__ */\r
+ PUBWEAK __ROM_CODE\r
+ PUBWEAK __MDE\r
+ PUBWEAK __OFS1\r
+ PUBWEAK __OFS0\r
+ PUBWEAK __OSIS_1\r
+ PUBWEAK __OSIS_2\r
+ PUBWEAK __OSIS_3\r
+ PUBWEAK __OSIS_4\r
+ PUBWEAK __SPCC\r
+ PUBWEAK __TMEF\r
+ PUBWEAK __TMINF\r
+\r
+__ROM_CODE equ 0xffffffff\r
+\r
+// 0x00120040 SPCC register\r
+__SPCC equ 0xffffffff\r
+\r
+// 0x00120048 TMEF register\r
+__TMEF equ 0xffffffff\r
+\r
+// 0x00120050 OSIC register (ID codes)\r
+__OSIS_1 equ 0xffffffff\r
+__OSIS_2 equ 0xffffffff\r
+__OSIS_3 equ 0xffffffff\r
+__OSIS_4 equ 0xffffffff\r
+\r
+// 0x00120060 TMINF register\r
+__TMINF equ 0xffffffff\r
+\r
+// 0x00120064 MDE register (Single Chip Mode)\r
+#if __LITTLE_ENDIAN__\r
+__MDE equ 0xffffffff // little\r
+#else\r
+__MDE equ 0xfffffff8 // big\r
+#endif\r
+\r
+// 0x00120068 OFS0 register\r
+__OFS0 equ 0xffffffff\r
+\r
+// 0x0012006c OFS1 register\r
+__OFS1 equ 0xffffffff\r
+\r
+#endif\r
+ END\r