+ New feature added: Task notifications.

[freertos] / FreeRTOS / Demo / RX600_RX630-RSK_Renesas / RTOSDemo / Renesas-Files / cgc_set.h

diff --git a/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc_set.h b/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc_set.h
index b155b1149f11b99c64a6067e4e840334babd39bc..f05b9336616c93c4ef75c962f8fc784a9203633f 100644 (file)
--- a/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc_set.h
+++ b/FreeRTOS/Demo/RX600_RX630-RSK_Renesas/RTOSDemo/Renesas-Files/cgc_set.h
@@ -1,7 +1,7 @@
 #ifndef CGC_SET_VALUES_H_\r
 #define CGC_SET_VALUES_H_\r
 \r
-/* Do not modify these macros.  These values are used to initialise  \r
+/* Do not modify these macros.  These values are used to initialise\r
    the SCKCR and SCKCR2 registers based upon the above values.      */\r
 #if   (FCLK_DIV == 64)\r
     #define FCLK_SCKCR  0x60000000L\r
@@ -40,12 +40,12 @@
     #define ICLK_SCKCR  0x01000000L\r
 #endif\r
 \r
-    \r
+\r
 #if (BCLK_PIN == 1)\r
     #define PSTOP1_SCKCR 0x00800000L\r
-#elif    \r
+#else\r
     #define PSTOP1_SCKCR 0x00000000L\r
-#endif    \r
+#endif\r
 \r
 \r
 #if   (BCLK_DIV == 64)\r
@@ -120,7 +120,7 @@
 #elif (PCLK47_DIV ==  1)\r
     #define PCLK47_SCKCR  0x00000000L\r
 #else\r
-    #define PCLK47_SCKCR  0x00000010L    \r
+    #define PCLK47_SCKCR  0x00000010L\r
 #endif\r
 \r
 \r
@@ -139,7 +139,7 @@
 #elif (PCLK03_DIV ==  1)\r
     #define PCLK03_SCKCR  0x00000000L\r
 #else\r
-    #define PCLK03_SCKCR  0x00000001L    \r
+    #define PCLK03_SCKCR  0x00000001L\r
 #endif\r
 \r
 \r
@@ -173,7 +173,7 @@
 \r
 #if (CLK_SOURCE == CLK_SOURCE_LOCO)\r
 /* Internal LOCO circuit - 125kHz*/\r
-#define     CLK_FREQUENCY       (125000L)      \r
+#define     CLK_FREQUENCY       (125000L)\r
 #define     FCLK_FREQUENCY      (CLK_FREQUENCY / FCLK_DIV)\r
 #define     ICLK_FREQUENCY      (CLK_FREQUENCY / ICLK_DIV)\r
 #define     BCLK_FREQUENCY      (CLK_FREQUENCY / BCLK_DIV)\r
@@ -185,7 +185,7 @@
 \r
 #elif (CLK_SOURCE == CLK_SOURCE_HOCO)\r
 /* Internal high speed on-chip oscillator (HOCO) */\r
-#define     CLK_FREQUENCY       (50000000L)    \r
+#define     CLK_FREQUENCY       (50000000L)\r
 #define     FCLK_FREQUENCY      (CLK_FREQUENCY / FCLK_DIV)\r
 #define     ICLK_FREQUENCY      (CLK_FREQUENCY / ICLK_DIV)\r
 #define     BCLK_FREQUENCY      (CLK_FREQUENCY / BCLK_DIV)\r
@@ -196,7 +196,7 @@
 \r
 \r
 #elif (CLK_SOURCE == CLK_SOURCE_MAIN)\r
-/* External XTAL, but not via the PLL circuit */       \r
+/* External XTAL, but not via the PLL circuit */\r
 #define     FCLK_FREQUENCY      (XTAL_FREQUENCY / FCLK_DIV)\r
 #define     ICLK_FREQUENCY      (XTAL_FREQUENCY / ICLK_DIV)\r
 #define     BCLK_FREQUENCY      (XTAL_FREQUENCY / BCLK_DIV)\r
@@ -207,7 +207,7 @@
 \r
 \r
 #elif (CLK_SOURCE == CLK_SOURCE_SUB)\r
-/* External 32khZ XTAL */      \r
+/* External 32khZ XTAL */\r
 #define     FCLK_FREQUENCY      (SUB_FREQUENCY / FCLK_DIV)\r
 #define     ICLK_FREQUENCY      (SUB_FREQUENCY / ICLK_DIV)\r
 #define     BCLK_FREQUENCY      (SUB_FREQUENCY / BCLK_DIV)\r
@@ -219,7 +219,7 @@
 \r
 #elif (CLK_SOURCE == CLK_SOURCE_PLL)\r
 /* External XTAL, but using the PLL circuit */\r
-#define     PLL_FREQUENCY       (XTAL_FREQUENCY * (PLL_MUL / PLL_INPUT_FREQ_DIV))      \r
+#define     PLL_FREQUENCY       (XTAL_FREQUENCY * (PLL_MUL / PLL_INPUT_FREQ_DIV))\r
 #define     FCLK_FREQUENCY      (PLL_FREQUENCY / FCLK_DIV)\r
 #define     ICLK_FREQUENCY      (PLL_FREQUENCY / ICLK_DIV)\r
 #define     BCLK_FREQUENCY      (PLL_FREQUENCY / BCLK_DIV)\r