Update version number to 9.0.0rc2.

[freertos] / FreeRTOS / Demo / RX700_RX71M_RSK_GCC_e2studio_IAR / src / Full_Demo / IntQueueTimer.c

diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c
index 0da468ed3bcabaa1a589d291cd9d618552cc31a2..6086df76779e6bb58612bba177f8f8289dd6bece 100644 (file)
--- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c
+++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c
@@ -1,5 +1,5 @@
 /*\r
-    FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+    FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
     All rights reserved\r
 \r
     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
@@ -8,7 +8,7 @@
 \r
     FreeRTOS is free software; you can redistribute it and/or modify it under\r
     the terms of the GNU General Public License (version 2) as published by the\r
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
 \r
     ***************************************************************************\r
     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
@@ -68,9 +68,9 @@
 */\r
 \r
 /*\r
- * This file contains the non-portable and therefore RX62N specific parts of\r
- * the IntQueue standard demo task - namely the configuration of the timers\r
- * that generate the interrupts and the interrupt entry points.\r
+ * This file contains the non-portable and therefore RX specific parts of the\r
+ * IntQueue standard demo task - namely the configuration of the timers that\r
+ * generate the interrupts and the interrupt entry points.\r
  */\r
 \r
 /* Scheduler includes. */\r
@@ -81,23 +81,8 @@
 #include "IntQueueTimer.h"\r
 #include "IntQueue.h"\r
 \r
-/* Hardware specifics. */\r
-#include "iodefine.h"\r
-\r
-#define IPR_PERIB_INTB128      128\r
-#define IPR_PERIB_INTB129      129\r
-#define IER_PERIB_INTB128      0x10\r
-#define IER_PERIB_INTB129      0x10\r
-#define        IEN_PERIB_INTB128       IEN0\r
-#define        IEN_PERIB_INTB129       IEN1\r
-#define IR_PERIB_INTB128       128\r
-#define IR_PERIB_INTB129       129\r
-\r
-void vIntQTimerISR0( void ) __attribute__ ((interrupt));\r
-void vIntQTimerISR1( void ) __attribute__ ((interrupt));\r
-\r
 #define tmrTIMER_0_1_FREQUENCY ( 2000UL )\r
-#define tmrTIMER_2_3_FREQUENCY ( 2001UL )\r
+#define tmrTIMER_2_3_FREQUENCY ( 2301UL )\r
 \r
 void vInitialiseTimerForIntQueueTest( void )\r
 {\r
@@ -107,7 +92,7 @@ void vInitialiseTimerForIntQueueTest( void )
                /* Give write access. */\r
                SYSTEM.PRCR.WORD = 0xa502;\r
 \r
-               /* Cascade two 8bit timer channels to generate the interrupts. \r
+               /* Cascade two 8bit timer channels to generate the interrupts.\r
                8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are\r
                utilised for this test. */\r
 \r
@@ -130,11 +115,11 @@ void vInitialiseTimerForIntQueueTest( void )
                /* 16 bit operation ( count from timer 1,2 ). */\r
                TMR0.TCCR.BIT.CSS = 3;\r
                TMR2.TCCR.BIT.CSS = 3;\r
-       \r
+\r
                /* Use PCLK as the input. */\r
                TMR1.TCCR.BIT.CSS = 1;\r
                TMR3.TCCR.BIT.CSS = 1;\r
-       \r
+\r
                /* Divide PCLK by 8. */\r
                TMR1.TCCR.BIT.CKS = 2;\r
                TMR3.TCCR.BIT.CKS = 2;\r
@@ -143,11 +128,9 @@ void vInitialiseTimerForIntQueueTest( void )
                TMR0.TCR.BIT.CMIEA = 1;\r
                TMR2.TCR.BIT.CMIEA = 1;\r
 \r
-               /* Map TMR0 CMIA0 interrupt to vector slot B number 128 and set\r
-               priority above the kernel's priority, but below the max syscall\r
-               priority. */\r
-           ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */\r
-           IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;\r
+               /* Set priority and enable interrupt. */\r
+               ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */\r
+               IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;\r
                IEN( PERIB, INTB128 ) = 1;\r
 \r
                /* Ensure that the flag is set to 0, otherwise the interrupt will not be\r
@@ -155,8 +138,8 @@ void vInitialiseTimerForIntQueueTest( void )
                IR( PERIB, INTB128 ) = 0;\r
 \r
                /* Do the same for TMR2, but to vector 129. */\r
-           ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */\r
-           IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;\r
+               ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */\r
+               IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;\r
                IEN( PERIB, INTB129 ) = 1;\r
                IR( PERIB, INTB129 ) = 0;\r
        }\r
@@ -164,25 +147,49 @@ void vInitialiseTimerForIntQueueTest( void )
 }\r
 /*-----------------------------------------------------------*/\r
 \r
-/* On vector 128. */\r
-void vIntQTimerISR0( void )\r
-{\r
-       /* Enable interrupts to allow interrupt nesting. */\r
-       __asm volatile( "setpsw i" );\r
+#ifdef __GNUC__\r
+\r
+       void vIntQTimerISR0( void ) __attribute__ ((interrupt));\r
+       void vIntQTimerISR1( void ) __attribute__ ((interrupt));\r
+\r
+       void vIntQTimerISR0( void )\r
+       {\r
+               /* Enable interrupts to allow interrupt nesting. */\r
+               __asm volatile( "setpsw i" );\r
+\r
+               portYIELD_FROM_ISR( xFirstTimerHandler() );\r
+       }\r
+       /*-----------------------------------------------------------*/\r
+\r
+       void vIntQTimerISR1( void )\r
+       {\r
+               /* Enable interrupts to allow interrupt nesting. */\r
+               __asm volatile( "setpsw i" );\r
+\r
+               portYIELD_FROM_ISR( xSecondTimerHandler() );\r
+       }\r
 \r
+#endif /* __GNUC__ */\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __ICCRX__\r
+\r
+#pragma vector = VECT_PERIB_INTB128\r
+__interrupt void vT0_1InterruptHandler( void )\r
+{\r
+       __enable_interrupt();\r
        portYIELD_FROM_ISR( xFirstTimerHandler() );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
-/* On vector 129. */\r
-void vIntQTimerISR1( void )\r
+#pragma vector = VECT_PERIB_INTB129\r
+__interrupt void vT2_3InterruptHandler( void )\r
 {\r
-       /* Enable interrupts to allow interrupt nesting. */\r
-       __asm volatile( "setpsw i" );\r
-\r
+       __enable_interrupt();\r
        portYIELD_FROM_ISR( xSecondTimerHandler() );\r
 }\r
 \r
+#endif /* __ICCRX__ */\r
 \r
 \r
 \r