Add FreeRTOS-Plus directory.

[freertos] / FreeRTOS / Demo / lwIP_MCF5235_GCC / include / arch / mcf523x / mcf523x_qspi.h

diff --git a/FreeRTOS/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h b/FreeRTOS/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h
new file mode 100644 (file)
index 0000000..9f05ada
--- /dev/null
+++ b/FreeRTOS/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h
@@ -0,0 +1,69 @@
+/*\r
+ * These files are taken from the MCF523X source code example package\r
+ * which is available on the Freescale website. Freescale explicitly \r
+ * grants the redistribution and modification of these source files.\r
+ * The complete licensing information is available in the file \r
+ * LICENSE_FREESCALE.TXT.\r
+ *\r
+ * File:       mcf523x_qspi.h\r
+ * Purpose:    Register and bit definitions for the MCF523X\r
+ *\r
+ * Notes:      \r
+ *     \r
+ */\r
+\r
+#ifndef __MCF523X_QSPI_H__\r
+#define __MCF523X_QSPI_H__\r
+\r
+/*********************************************************************\r
+*\r
+* Queued Serial Peripheral Interface (QSPI)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_QSPI_QMR      (*(vuint16*)(void*)(&__IPSBAR[0x000340]))\r
+#define MCF_QSPI_QDLYR    (*(vuint16*)(void*)(&__IPSBAR[0x000344]))\r
+#define MCF_QSPI_QWR      (*(vuint16*)(void*)(&__IPSBAR[0x000348]))\r
+#define MCF_QSPI_QIR      (*(vuint16*)(void*)(&__IPSBAR[0x00034C]))\r
+#define MCF_QSPI_QAR      (*(vuint16*)(void*)(&__IPSBAR[0x000350]))\r
+#define MCF_QSPI_QDR      (*(vuint16*)(void*)(&__IPSBAR[0x000354]))\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QMR */\r
+#define MCF_QSPI_QMR_BAUD(x)     (((x)&0x00FF)<<0)\r
+#define MCF_QSPI_QMR_CPHA        (0x0100)\r
+#define MCF_QSPI_QMR_CPOL        (0x0200)\r
+#define MCF_QSPI_QMR_BITS(x)     (((x)&0x000F)<<10)\r
+#define MCF_QSPI_QMR_DOHIE       (0x4000)\r
+#define MCF_QSPI_QMR_MSTR        (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QDLYR */\r
+#define MCF_QSPI_QDLYR_DTL(x)    (((x)&0x00FF)<<0)\r
+#define MCF_QSPI_QDLYR_QCD(x)    (((x)&0x007F)<<8)\r
+#define MCF_QSPI_QDLYR_SPE       (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QWR */\r
+#define MCF_QSPI_QWR_NEWQP(x)    (((x)&0x000F)<<0)\r
+#define MCF_QSPI_QWR_ENDQP(x)    (((x)&0x000F)<<8)\r
+#define MCF_QSPI_QWR_CSIV        (0x1000)\r
+#define MCF_QSPI_QWR_WRTO        (0x2000)\r
+#define MCF_QSPI_QWR_WREN        (0x4000)\r
+#define MCF_QSPI_QWR_HALT        (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QIR */\r
+#define MCF_QSPI_QIR_SPIF        (0x0001)\r
+#define MCF_QSPI_QIR_ABRT        (0x0004)\r
+#define MCF_QSPI_QIR_WCEF        (0x0008)\r
+#define MCF_QSPI_QIR_SPIFE       (0x0100)\r
+#define MCF_QSPI_QIR_ABRTE       (0x0400)\r
+#define MCF_QSPI_QIR_WCEFE       (0x0800)\r
+#define MCF_QSPI_QIR_ABRTL       (0x1000)\r
+#define MCF_QSPI_QIR_ABRTB       (0x4000)\r
+#define MCF_QSPI_QIR_WCEFB       (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QAR */\r
+#define MCF_QSPI_QAR_ADDR(x)     (((x)&0x003F)<<0)\r
+\r
+/********************************************************************/\r
+\r
+#endif /* __MCF523X_QSPI_H__ */\r