Add additional memory barriers into ARM GCC asm code to ensure no re-ordering across...

[freertos] / FreeRTOS / Source / portable / GCC / ARM_CA53_64_BIT / port.c

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
index 3933d277f013b6fec11c7efc2ee3ceace8505c44..1bacd3fbc3a313652e42fc4660e2ad9e4e7274c2 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
@@ -448,7 +448,7 @@ void FreeRTOS_Tick_Handler( void )
        {\r
                uint32_t ulMaskBits;\r
 \r
-               __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) );\r
+               __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) :: "memory" );\r
                configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );\r
        }\r
        #endif /* configASSERT_DEFINED */\r
@@ -460,7 +460,7 @@ void FreeRTOS_Tick_Handler( void )
        updated. */\r
        portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
        __asm volatile (        "dsb sy         \n"\r
-                                               "isb sy         \n" );\r
+                                               "isb sy         \n" ::: "memory" );\r
 \r
        /* Ok to enable interrupts after the interrupt source has been cleared. */\r
        configCLEAR_TICK_INTERRUPT();\r
@@ -514,7 +514,7 @@ uint32_t ulReturn;
                ulReturn = pdFALSE;\r
                portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
                __asm volatile (        "dsb sy         \n"\r
-                                                       "isb sy         \n" );\r
+                                                       "isb sy         \n" ::: "memory" );\r
        }\r
        portENABLE_INTERRUPTS();\r
 \r