Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to...

[freertos] / FreeRTOS / Source / portable / GCC / ARM_CA53_64_BIT / portmacro.h

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
index a617b829b577b520907a06ec68b7bf8a5b5ac431..3fe8cf645a108dd43538f800fac99d14e910e3da 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
@@ -128,8 +128,11 @@ extern uint64_t ullPortYieldRequired;                      \
 }\r
 \r
 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
-#define portYIELD() __asm volatile ( "SMC 0" )\r
-\r
+#if GUEST\r
+       #define portYIELD() __asm volatile ( "SVC 0" )\r
+#else\r
+       #define portYIELD() __asm volatile ( "SMC 0" )\r
+#endif\r
 /*-----------------------------------------------------------\r
  * Critical section control\r
  *----------------------------------------------------------*/\r