Add additional memory barriers into ARM GCC asm code to ensure no re-ordering across...

[freertos] / FreeRTOS / Source / portable / GCC / ARM_CM0 / port.c

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
index b70a49af20a58a2eccc145cb6f4b92c5ca034284..559883f5805a3120c65ddb99628adad7d6e4b9e0 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
@@ -79,15 +79,15 @@
 #define portNVIC_SYSTICK_CTRL                  ( ( volatile uint32_t * ) 0xe000e010 )\r
 #define portNVIC_SYSTICK_LOAD                  ( ( volatile uint32_t * ) 0xe000e014 )\r
 #define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
-#define portNVIC_INT_CTRL                      ( ( volatile uint32_t *) 0xe000ed04 )\r
-#define portNVIC_SYSPRI2                       ( ( volatile uint32_t *) 0xe000ed20 )\r
-#define portNVIC_SYSTICK_CLK           0x00000004\r
-#define portNVIC_SYSTICK_INT           0x00000002\r
-#define portNVIC_SYSTICK_ENABLE                0x00000001\r
-#define portNVIC_PENDSVSET                     0x10000000\r
-#define portMIN_INTERRUPT_PRIORITY     ( 255UL )\r
-#define portNVIC_PENDSV_PRI                    ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
-#define portNVIC_SYSTICK_PRI           ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+#define portNVIC_INT_CTRL                              ( ( volatile uint32_t *) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2                               ( ( volatile uint32_t *) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK                   0x00000004\r
+#define portNVIC_SYSTICK_INT                   0x00000002\r
+#define portNVIC_SYSTICK_ENABLE                        0x00000001\r
+#define portNVIC_PENDSVSET                             0x10000000\r
+#define portMIN_INTERRUPT_PRIORITY             ( 255UL )\r
+#define portNVIC_PENDSV_PRI                            ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI                   ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
 \r
 /* Constants required to set up the initial stack. */\r
 #define portINITIAL_XPSR                       ( 0x01000000 )\r
@@ -243,7 +243,7 @@ void vPortYield( void )
 \r
        /* Barriers are normally not required but do ensure the code is completely\r
        within the specified behaviour for the architecture. */\r
-       __asm volatile( "dsb" );\r
+       __asm volatile( "dsb" ::: "memory" );\r
        __asm volatile( "isb" );\r
 }\r
 /*-----------------------------------------------------------*/\r
@@ -252,7 +252,7 @@ void vPortEnterCritical( void )
 {\r
     portDISABLE_INTERRUPTS();\r
     uxCriticalNesting++;\r
-       __asm volatile( "dsb" );\r
+       __asm volatile( "dsb" ::: "memory" );\r
        __asm volatile( "isb" );\r
 }\r
 /*-----------------------------------------------------------*/\r
@@ -274,6 +274,7 @@ uint32_t ulSetInterruptMaskFromISR( void )
                                        " mrs r0, PRIMASK       \n"\r
                                        " cpsid i                       \n"\r
                                        " bx lr                           "\r
+                                       ::: "memory"\r
                                  );\r
 \r
        /* To avoid compiler warnings.  This line will never be reached. */\r
@@ -286,6 +287,7 @@ void vClearInterruptMaskFromISR( uint32_t ulMask )
        __asm volatile(\r
                                        " msr PRIMASK, r0       \n"\r
                                        " bx lr                           "\r
+                                       ::: "memory"\r
                                  );\r
 \r
        /* Just to avoid compiler warning. */\r