/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.\r
All rights reserved\r
\r
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
\r
FreeRTOS is free software; you can redistribute it and/or modify it under\r
the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
\r
***************************************************************************\r
>>! NOTE: The modification to the GPL is included to allow you to !<<\r
calculations. */\r
#define portMISSED_COUNTS_FACTOR ( 45UL )\r
\r
+/* For strict compliance with the Cortex-M spec the task start address should\r
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
+#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )\r
+\r
/* Let the user override the pre-loading of the initial LR with the address of\r
-prvTaskExitError() in case is messes up unwinding of the stack in the\r
+prvTaskExitError() in case it messes up unwinding of the stack in the\r
debugger. */\r
#ifdef configTASK_RETURN_ADDRESS\r
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */\r
pxTopOfStack--;\r
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
" orr r14, #0xd \n"\r
" bx r14 \n"\r
" \n"\r
- " .align 2 \n"\r
+ " .align 4 \n"\r
"pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
);\r
}\r
ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
}\r
\r
+ #ifdef __NVIC_PRIO_BITS\r
+ {\r
+ /* Check the CMSIS configuration that defines the number of\r
+ priority bits matches the number of priority bits actually queried\r
+ from the hardware. */\r
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\r
+ }\r
+ #endif\r
+\r
+ #ifdef configPRIO_BITS\r
+ {\r
+ /* Check the FreeRTOS configuration that defines the number of\r
+ priority bits matches the number of priority bits actually queried\r
+ from the hardware. */\r
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\r
+ }\r
+ #endif\r
+\r
/* Shift the priority group value back to its position within the AIRCR\r
register. */\r
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortYield( void )\r
-{\r
- /* Set a PendSV to request a context switch. */\r
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
-\r
- /* Barriers are normally not required but do ensure the code is completely\r
- within the specified behaviour for the architecture. */\r
- __asm volatile( "dsb" );\r
- __asm volatile( "isb" );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
void vPortEnterCritical( void )\r
{\r
portDISABLE_INTERRUPTS();\r
uxCriticalNesting++;\r
- __asm volatile( "dsb" );\r
- __asm volatile( "isb" );\r
- \r
+\r
/* This is not the interrupt safe version of the enter critical function so\r
- assert() if it is being called from an interrupt context. Only API \r
+ assert() if it is being called from an interrupt context. Only API\r
functions that end in "FromISR" can be used in an interrupt. Only assert if\r
the critical nesting count is 1 to protect against recursive calls if the\r
assert function also uses a critical section. */\r
}\r
/*-----------------------------------------------------------*/\r
\r
-__attribute__(( naked )) uint32_t ulPortSetInterruptMask( void )\r
-{\r
- __asm volatile \\r
- ( \\r
- " mrs r0, basepri \n" \\r
- " mov r1, %0 \n" \\r
- " msr basepri, r1 \n" \\r
- " bx lr \n" \\r
- :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1" \\r
- );\r
-\r
- /* This return will not be reached but is necessary to prevent compiler\r
- warnings. */\r
- return 0;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-__attribute__(( naked )) void vPortClearInterruptMask( uint32_t ulNewMaskValue )\r
-{\r
- __asm volatile \\r
- ( \\r
- " msr basepri, r0 \n" \\r
- " bx lr \n" \\r
- :::"r0" \\r
- );\r
-\r
- /* Just to avoid compiler warnings. */\r
- ( void ) ulNewMaskValue;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
void xPortPendSVHandler( void )\r
{\r
/* This is a naked function. */\r
" mov r0, #0 \n"\r
" msr basepri, r0 \n"\r
" ldmia sp!, {r3, r14} \n"\r
- " \n" /* Restore the context, including the critical nesting count. */\r
+ " \n" /* Restore the context, including the critical nesting count. */\r
" ldr r1, [r3] \n"\r
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
" ldmia r0!, {r4-r11} \n" /* Pop the registers. */\r
" isb \n"\r
" bx r14 \n"\r
" \n"\r
- " .align 2 \n"\r
+ " .align 4 \n"\r
"pxCurrentTCBConst: .word pxCurrentTCB \n"\r
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
);\r
executes all interrupts must be unmasked. There is therefore no need to\r
save and then restore the interrupt mask value as its value is already\r
known. */\r
- ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
+ portDISABLE_INTERRUPTS();\r
{\r
/* Increment the RTOS tick. */\r
if( xTaskIncrementTick() != pdFALSE )\r
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
}\r
}\r
- portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
+ portENABLE_INTERRUPTS();\r
}\r
/*-----------------------------------------------------------*/\r
\r
\r
__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
{\r
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;\r
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\r
TickType_t xModifiableIdleTime;\r
\r
/* Make sure the SysTick reload value does not overflow the counter. */\r
\r
/* Enter a critical section but don't use the taskENTER_CRITICAL()\r
method as that will mask interrupts that should exit sleep mode. */\r
- __asm volatile( "cpsid i" );\r
+ __asm volatile( "cpsid i" ::: "memory" );\r
+ __asm volatile( "dsb" );\r
+ __asm volatile( "isb" );\r
\r
/* If a context switch is pending or a task is waiting for the scheduler\r
to be unsuspended then abandon the low power entry. */\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
- __asm volatile( "cpsie i" );\r
+ __asm volatile( "cpsie i" ::: "memory" );\r
}\r
else\r
{\r
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
if( xModifiableIdleTime > 0 )\r
{\r
- __asm volatile( "dsb" );\r
+ __asm volatile( "dsb" ::: "memory" );\r
__asm volatile( "wfi" );\r
__asm volatile( "isb" );\r
}\r
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
\r
- /* Stop SysTick. Again, the time the SysTick is stopped for is\r
- accounted for as best it can be, but using the tickless mode will\r
- inevitably result in some tiny drift of the time maintained by the\r
- kernel with respect to calendar time. */\r
- ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;\r
- portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );\r
-\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
- __asm volatile( "cpsie i" );\r
-\r
- if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
+ __asm volatile( "cpsie i" ::: "memory" );\r
+\r
+ /* Disable the SysTick clock without reading the\r
+ portNVIC_SYSTICK_CTRL_REG register to ensure the\r
+ portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. */\r
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );\r
+\r
+ /* Determine if the SysTick clock has already counted to zero and\r
+ been set back to the current reload value (the reload back being\r
+ correct for the entire expected idle time) or if the SysTick is yet\r
+ to count to zero (in which case an interrupt other than the SysTick\r
+ must have brought the system out of sleep mode). */\r
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
{\r
uint32_t ulCalculatedLoadValue;\r
\r
\r
/* The reload value is set to whatever fraction of a single tick\r
period remains. */\r
- portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
}\r
\r
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
}\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
+ /* Stop and clear the SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG = 0UL;\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+\r
/* Configure SysTick to interrupt at the requested rate. */\r
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r
uint8_t ucCurrentPriority;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
- __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
\r
/* Is the interrupt number a user defined interrupt? */\r
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
projects / freertos / blobdiff