\r
#ifndef configSYSTICK_CLOCK_HZ\r
#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
+ /* Ensure the SysTick is clocked at the same frequency as the core. */\r
+ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )\r
+#else\r
+ /* The way the SysTick is clocked is not modified in case it is not the same\r
+ as the core. */\r
+ #define portNVIC_SYSTICK_CLK_BIT ( 0 )\r
#endif\r
\r
/* Constants required to manipulate the core. Registers first... */\r
-#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
-#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
-#define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
+#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
+#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
+#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
/* ...then bits in the registers. */\r
-#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )\r
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )\r
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )\r
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )\r
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )\r
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )\r
\r
-#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
-#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
\r
/* Constants required to check the validity of an interrupt priority. */\r
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )\r
-#define portAIRCR_REG ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )\r
-#define portMAX_8_BIT_VALUE ( ( unsigned char ) 0xff )\r
-#define portTOP_BIT_OF_BYTE ( ( unsigned char ) 0x80 )\r
-#define portMAX_PRIGROUP_BITS ( ( unsigned char ) 7 )\r
+#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )\r
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )\r
#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
#define portPRIGROUP_SHIFT ( 8UL )\r
\r
\r
/* Each task maintains its own interrupt status in the critical nesting\r
variable. */\r
-static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
\r
/*\r
* Setup the timer to generate the tick interrupts. The implementation in this\r
* The number of SysTick increments that make up one tick period.\r
*/\r
#if configUSE_TICKLESS_IDLE == 1\r
- static unsigned long ulTimerCountsForOneTick = 0;\r
+ static uint32_t ulTimerCountsForOneTick = 0;\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
/*\r
* 24 bit resolution of the SysTick timer.\r
*/\r
#if configUSE_TICKLESS_IDLE == 1\r
- static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
+ static uint32_t xMaximumPossibleSuppressedTicks = 0;\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
/*\r
* power functionality only.\r
*/\r
#if configUSE_TICKLESS_IDLE == 1\r
- static unsigned long ulStoppedTimerCompensation = 0;\r
+ static uint32_t ulStoppedTimerCompensation = 0;\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
/*\r
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
*/\r
#if ( configASSERT_DEFINED == 1 )\r
- static unsigned char ucMaxSysCallPriority = 0;\r
- static unsigned long ulMaxPRIGROUPValue = 0;\r
- static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
+ static uint8_t ucMaxSysCallPriority = 0;\r
+ static uint32_t ulMaxPRIGROUPValue = 0;\r
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
#endif /* configASSERT_DEFINED */\r
\r
/*-----------------------------------------------------------*/\r
/*\r
* See header file for description.\r
*/\r
-portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
{\r
/* Simulate the stack frame as it would be created by a context switch\r
interrupt. */\r
pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
pxTopOfStack--;\r
- *pxTopOfStack = ( portSTACK_TYPE ) portTASK_RETURN_ADDRESS; /* LR */\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
- *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
\r
return pxTopOfStack;\r
/*\r
* See header file for description.\r
*/\r
-portBASE_TYPE xPortStartScheduler( void )\r
+BaseType_t xPortStartScheduler( void )\r
{\r
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
\r
#if( configASSERT_DEFINED == 1 )\r
{\r
- volatile unsigned long ulOriginalPriority;\r
- volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
- volatile unsigned char ucMaxPriorityValue;\r
+ volatile uint32_t ulOriginalPriority;\r
+ volatile int8_t * const pcFirstUserPriorityRegister = ( volatile int8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile uint8_t ucMaxPriorityValue;\r
\r
/* Determine the maximum priority from which ISR safe FreeRTOS API\r
functions can be called. ISR safe functions are those that end in\r
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
{\r
ulMaxPRIGROUPValue--;\r
- ucMaxPriorityValue <<= ( unsigned char ) 0x01;\r
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
}\r
\r
/* Shift the priority group value back to its position within the AIRCR\r
}\r
/*-----------------------------------------------------------*/\r
\r
-__attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )\r
+__attribute__(( naked )) uint32_t ulPortSetInterruptMask( void )\r
{\r
__asm volatile \\r
( \\r
}\r
/*-----------------------------------------------------------*/\r
\r
-__attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )\r
+__attribute__(( naked )) void vPortClearInterruptMask( uint32_t ulNewMaskValue )\r
{\r
__asm volatile \\r
( \\r
\r
#if configUSE_TICKLESS_IDLE == 1\r
\r
- __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
+ __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
{\r
- unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;\r
- portTickType xModifiableIdleTime;\r
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;\r
+ TickType_t xModifiableIdleTime;\r
\r
/* Make sure the SysTick reload value does not overflow the counter. */\r
if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
\r
if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
{\r
- unsigned long ulCalculatedLoadValue;\r
+ uint32_t ulCalculatedLoadValue;\r
\r
/* The tick interrupt has already executed, and the SysTick\r
count reloaded with ulReloadValue. Reset the\r
\r
/* Configure SysTick to interrupt at the requested rate. */\r
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
- portNVIC_SYSTICK_CTRL_REG |= ( portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r
}\r
/*-----------------------------------------------------------*/\r
\r
\r
void vPortValidateInterruptPriority( void )\r
{\r
- unsigned long ulCurrentInterrupt;\r
- unsigned char ucCurrentPriority;\r
+ uint32_t ulCurrentInterrupt;\r
+ uint8_t ucCurrentPriority;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
projects / freertos / blobdiff