Update version number in readiness for V10.3.0 release. Sync SVN with reviewed releas...

[freertos] / FreeRTOS / Source / portable / GCC / ARM_CM33 / secure / secure_context_port.c

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c b/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
index 1c5e97ef0bdb82705ad25392eeb75bd06f390157..8d9c8c6c682a6aa3e63b03d758c765ab0c472e4f 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
@@ -1,6 +1,6 @@
 /*\r
- * FreeRTOS Kernel V10.2.0\r
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
+ * FreeRTOS Kernel V10.3.0\r
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
  *\r
  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
  * this software and associated documentation files (the "Software"), to deal in\r
@@ -33,56 +33,56 @@
 \r
 secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )\r
 {\r
-    /* xSecureContextHandle value is in r0. */\r
-    __asm volatile\r
-    (\r
-    "    .syntax unified                        \n"\r
-    "                                           \n"\r
-    "    mrs r1, ipsr                           \n" /* r1 = IPSR. */\r
-    "    cbz r1, load_ctx_therad_mode           \n" /* Do nothing if the processor is running in the Thread Mode. */\r
-    "    ldmia r0!, {r1, r2}                    \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
-    #if( configENABLE_MPU == 1 )\r
-    "    ldmia r1!, {r3}                        \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
-    "    msr control, r3                        \n" /* CONTROL = r3. */\r
-    #endif /* configENABLE_MPU */\r
-    "    msr psplim, r2                         \n" /* PSPLIM = r2. */\r
-    "    msr psp, r1                            \n" /* PSP = r1. */\r
-    "                                           \n"\r
-    " load_ctx_therad_mode:                     \n"\r
-    "    nop                                    \n"\r
-    "                                           \n"\r
-    :::"r0", "r1", "r2"\r
-    );\r
+       /* xSecureContextHandle value is in r0. */\r
+       __asm volatile\r
+       (\r
+       "       .syntax unified                                                 \n"\r
+       "                                                                                       \n"\r
+       "       mrs r1, ipsr                                                    \n" /* r1 = IPSR. */\r
+       "       cbz r1, load_ctx_therad_mode                    \n" /* Do nothing if the processor is running in the Thread Mode. */\r
+       "       ldmia r0!, {r1, r2}                                             \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
+       #if( configENABLE_MPU == 1 )\r
+       "       ldmia r1!, {r3}                                                 \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
+       "       msr control, r3                                                 \n" /* CONTROL = r3. */\r
+       #endif /* configENABLE_MPU */\r
+       "       msr psplim, r2                                                  \n" /* PSPLIM = r2. */\r
+       "       msr psp, r1                                                             \n" /* PSP = r1. */\r
+       "                                                                                       \n"\r
+       " load_ctx_therad_mode:                                         \n"\r
+       "       nop                                                                             \n"\r
+       "                                                                                       \n"\r
+       :::"r0", "r1", "r2"\r
+       );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
 secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )\r
 {\r
-    /* xSecureContextHandle value is in r0. */\r
-    __asm volatile\r
-    (\r
-    "    .syntax unified                        \n"\r
-    "                                           \n"\r
-    "    mrs r1, ipsr                           \n" /* r1 = IPSR. */\r
-    "    cbz r1, save_ctx_therad_mode           \n" /* Do nothing if the processor is running in the Thread Mode. */\r
-    "    mrs r1, psp                            \n" /* r1 = PSP. */\r
-    #if( configENABLE_FPU == 1 )\r
-    "    vstmdb r1!, {s0}                       \n" /* Trigger the defferred stacking of FPU registers. */\r
-    "    vldmia r1!, {s0}                       \n" /* Nullify the effect of the pervious statement. */\r
-    #endif /* configENABLE_FPU */\r
-    #if( configENABLE_MPU == 1 )\r
-    "    mrs r2, control                        \n" /* r2 = CONTROL. */\r
-    "    stmdb r1!, {r2}                        \n" /* Store CONTROL value on the stack. */\r
-    #endif /* configENABLE_MPU */\r
-    "    str r1, [r0]                           \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
-    "    movs r1, %0                            \n" /* r1 = securecontextNO_STACK. */\r
-    "    msr psplim, r1                         \n" /* PSPLIM = securecontextNO_STACK. */\r
-    "    msr psp, r1                            \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
-    "                                           \n"\r
-    " save_ctx_therad_mode:                     \n"\r
-    "    nop                                    \n"\r
-    "                                           \n"\r
-    :: "i" ( securecontextNO_STACK ) : "r1", "memory"\r
-    );\r
+       /* xSecureContextHandle value is in r0. */\r
+       __asm volatile\r
+       (\r
+       "       .syntax unified                                                 \n"\r
+       "                                                                                       \n"\r
+       "       mrs r1, ipsr                                                    \n" /* r1 = IPSR. */\r
+       "       cbz r1, save_ctx_therad_mode                    \n" /* Do nothing if the processor is running in the Thread Mode. */\r
+       "       mrs r1, psp                                                             \n" /* r1 = PSP. */\r
+       #if( configENABLE_FPU == 1 )\r
+       "       vstmdb r1!, {s0}                                                \n" /* Trigger the defferred stacking of FPU registers. */\r
+       "       vldmia r1!, {s0}                                                \n" /* Nullify the effect of the pervious statement. */\r
+       #endif /* configENABLE_FPU */\r
+       #if( configENABLE_MPU == 1 )\r
+       "       mrs r2, control                                                 \n" /* r2 = CONTROL. */\r
+       "       stmdb r1!, {r2}                                                 \n" /* Store CONTROL value on the stack. */\r
+       #endif /* configENABLE_MPU */\r
+       "       str r1, [r0]                                                    \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+       "       movs r1, %0                                                             \n" /* r1 = securecontextNO_STACK. */\r
+       "       msr psplim, r1                                                  \n" /* PSPLIM = securecontextNO_STACK. */\r
+       "       msr psp, r1                                                             \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
+       "                                                                                       \n"\r
+       " save_ctx_therad_mode:                                         \n"\r
+       "       nop                                                                             \n"\r
+       "                                                                                       \n"\r
+       :: "i" ( securecontextNO_STACK ) : "r1", "memory"\r
+       );\r
 }\r
 /*-----------------------------------------------------------*/\r