Add barrier instructions to the GCC CM3 ports.

[freertos] / FreeRTOS / Source / portable / GCC / ARM_CM3_MPU / port.c

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
index 913b03fcae204dae8ac4e05856c1fb5054401800..9b564e9a57ef27b68acb9787adbda7e3e601b718 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
@@ -56,19 +56,19 @@
     ***************************************************************************\r
 \r
 \r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
     license and Real Time Engineers Ltd. contact details.\r
 \r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
     fully thread aware and reentrant UDP/IP stack.\r
 \r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
-    Integrity Systems, who sell the code with commercial support, \r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
     indemnification and middleware, under the OpenRTOS brand.\r
-    \r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
-    engineered and independently SIL3 certified version for use in safety and \r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
 */\r
 \r
@@ -290,6 +290,13 @@ unsigned char ucSVCNumber;
                                                                                        break;\r
 \r
                case portSVC_YIELD                              :       *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
+                                                                                       /* Barriers are normally not required\r
+                                                                                       but do ensure the code is completely\r
+                                                                                       within the specified behaviour for the\r
+                                                                                       architecture. */\r
+                                                                                       __asm volatile( "dsb" );\r
+                                                                                       __asm volatile( "isb" );\r
+\r
                                                                                        break;\r
 \r
                case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r