/*\r
FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
\r
- FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT \r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
\r
***************************************************************************\r
FreeRTOS WEB site.\r
\r
1 tab == 4 spaces!\r
- \r
+\r
***************************************************************************\r
* *\r
* Having a problem? Start by reading the FAQ "My application does *\r
* *\r
***************************************************************************\r
\r
- \r
- http://www.FreeRTOS.org - Documentation, training, latest versions, license \r
- and contact details. \r
- \r
+\r
+ http://www.FreeRTOS.org - Documentation, training, latest versions, license\r
+ and contact details.\r
+\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
including FreeRTOS+Trace - an indispensable productivity tool.\r
\r
- Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
- the code with commercial support, indemnification, and middleware, under \r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell\r
+ the code with commercial support, indemnification, and middleware, under\r
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
- provide a safety engineered and independently SIL3 certified version under \r
+ provide a safety engineered and independently SIL3 certified version under\r
the SafeRTOS brand: http://www.SafeRTOS.com.\r
*/\r
\r
\r
#ifndef configSYSTICK_CLOCK_HZ\r
#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
- #if configUSE_TICKLESS_IDLE == 1\r
- static const unsigned long ulStoppedTimerCompensation = 45UL;\r
- #endif\r
-#else /* configSYSTICK_CLOCK_HZ */\r
- #if configUSE_TICKLESS_IDLE == 1\r
- /* Assumes the SysTick clock is slower than the CPU clock. */\r
- static const unsigned long ulStoppedTimerCompensation = 45UL / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
- #endif\r
-#endif /* configSYSTICK_CLOCK_HZ */\r
+#endif\r
\r
/* Constants required to manipulate the core. Registers first... */\r
#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
\r
/*\r
- * Setup the timer to generate the tick interrupts.\r
+ * Setup the timer to generate the tick interrupts. The implementation in this\r
+ * file is weak to allow application writers to change the timer used to\r
+ * generate the tick interrupt.\r
*/\r
-static void prvSetupTimerInterrupt( void );\r
+void vPortSetupTimerInterrupt( void );\r
\r
/*\r
* Exception handlers.\r
/*\r
* The number of SysTick increments that make up one tick period.\r
*/\r
-static unsigned long ulTimerReloadValueForOneTick = 0;\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static unsigned long ulTimerReloadValueForOneTick = 0;\r
+#endif\r
\r
/*\r
* The maximum number of tick periods that can be suppressed is limited by the\r
static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
+/*\r
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
+ * power functionality only.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static unsigned long ulStoppedTimerCompensation = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
\r
/*-----------------------------------------------------------*/\r
\r
\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
here already. */\r
- prvSetupTimerInterrupt();\r
+ vPortSetupTimerInterrupt();\r
\r
/* Initialise the critical nesting count ready for the first task. */\r
uxCriticalNesting = 0;\r
" bx lr \n" \\r
:::"r0" \\r
);\r
+\r
+ /* Just to avoid compiler warnings. */\r
+ ( void ) ulNewMaskValue;\r
}\r
/*-----------------------------------------------------------*/\r
\r
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
#endif\r
\r
+ /* Only reset the systick load register if configUSE_TICKLESS_IDLE is set to\r
+ 1. If it is set to 0 tickless idle is not being used. If it is set to a\r
+ value other than 0 or 1 then a timer other than the SysTick is being used\r
+ to generate the tick interrupt. */\r
#if configUSE_TICKLESS_IDLE == 1\r
portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick;\r
#endif\r
__attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
{\r
unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickIncrements;\r
+ portTickType xModifiableIdleTime;\r
\r
/* Make sure the SysTick reload value does not overflow the counter. */\r
if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
kernel with respect to calendar time. */\r
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
\r
- /* If a context switch is pending then abandon the low power entry as\r
- the context switch might have been pended by an external interrupt that\r
- requires processing. */\r
- if( ( portNVIC_INT_CTRL_REG & portNVIC_PENDSVSET_BIT ) != 0 )\r
+ /* Adjust the reload value to take into account that the current time\r
+ slice is already partially complete. */\r
+ ulReloadValue += ( portNVIC_SYSTICK_LOAD_REG - ( portNVIC_SYSTICK_LOAD_REG - portNVIC_SYSTICK_CURRENT_VALUE_REG ) );\r
+\r
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
+ method as that will mask interrupts that should exit sleep mode. */\r
+ __asm volatile( "cpsid i" );\r
+\r
+ /* If a context switch is pending or a task is waiting for the scheduler\r
+ to be unsuspended then abandon the low power entry. */\r
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
{\r
/* Restart SysTick. */\r
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Re-enable interrupts - see comments above the cpsid instruction()\r
+ above. */\r
+ __asm volatile( "cpsie i" );\r
}\r
else\r
{\r
- /* Adjust the reload value to take into account that the current\r
- time slice is already partially complete. */\r
- ulReloadValue += ( portNVIC_SYSTICK_LOAD_REG - ( portNVIC_SYSTICK_LOAD_REG - portNVIC_SYSTICK_CURRENT_VALUE_REG ) );\r
+ /* Set the new reload value. */\r
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
\r
/* Clear the SysTick count flag and set the count value back to\r
/* Restart SysTick. */\r
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
\r
- /* Sleep until something happens. */\r
- configPRE_SLEEP_PROCESSING();\r
- __asm volatile( "wfi" );\r
- configPOST_SLEEP_PROCESSING();\r
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can\r
+ set its parameter to 0 to indicate that its implementation contains\r
+ its own wait for interrupt or wait for event instruction, and so wfi\r
+ should not be executed again. However, the original expected idle\r
+ time variable must remain unmodified, so a copy is taken. */\r
+ xModifiableIdleTime = xExpectedIdleTime;\r
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
+ if( xModifiableIdleTime > 0 )\r
+ {\r
+ __asm volatile( "wfi" );\r
+ }\r
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
\r
/* Stop SysTick. Again, the time the SysTick is stopped for is\r
accounted for as best it can be, but using the tickless mode will\r
kernel with respect to calendar time. */\r
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
\r
+ /* Re-enable interrupts - see comments above the cpsid instruction()\r
+ above. */\r
+ __asm volatile( "cpsie i" );\r
+\r
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
{\r
/* The tick interrupt has already executed, and the SysTick\r
* Setup the systick timer to generate the tick interrupts at the required\r
* frequency.\r
*/\r
-void prvSetupTimerInterrupt( void )\r
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
{\r
/* Calculate the constants required to configure the tick interrupt. */\r
- ulTimerReloadValueForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
#if configUSE_TICKLESS_IDLE == 1\r
+ {\r
+ ulTimerReloadValueForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
xMaximumPossibleSuppressedTicks = 0xffffffUL / ( ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );\r
+ ulStoppedTimerCompensation = 45UL / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
+ }\r
#endif /* configUSE_TICKLESS_IDLE */\r
\r
-\r
/* Configure SysTick to interrupt at the requested rate. */\r
- portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick;\r
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
}\r
/*-----------------------------------------------------------*/\r