Improvements to the Cortex-M ports:

[freertos] / FreeRTOS / Source / portable / GCC / ARM_CM7 / r0p1 / port.c

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
index ce19d6af5593fdf6023d08a7ff641b29f71b75f1..51d1c1a661a22b2d125565059bfb5461dea6f8f7 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
@@ -437,8 +437,8 @@ void xPortPendSVHandler( void )
        "       vstmdbeq r0!, {s16-s31}                         \n"\r
        "                                                                               \n"\r
        "       stmdb r0!, {r4-r11, r14}                        \n" /* Save the core registers. */\r
-       "                                                                               \n"\r
        "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
+       "       clrex                                                           \n" /* Ensure thread safety of atomic operations. */\r
        "                                                                               \n"\r
        "       stmdb sp!, {r3}                                         \n"\r
        "       mov r0, %0                                                      \n"\r
@@ -669,6 +669,10 @@ __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
        }\r
        #endif /* configUSE_TICKLESS_IDLE */\r
 \r
+       /* Stop and clear the SysTick. */\r
+       portNVIC_SYSTICK_CTRL_REG = 0UL;\r
+       portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+\r
        /* Configure SysTick to interrupt at the requested rate. */\r
        portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
        portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r