Changes to core code and port layer:

[freertos] / FreeRTOS / Source / portable / GCC / ARM_CM7 / r0p1 / port.c

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
index 86fb9cc6bb3afcd6b9ddb465761c8f2d4513df80..e0719c4107ab55590c4879a6608fc31da488a45e 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
@@ -285,11 +285,17 @@ void vPortSVCHandler( void )
 \r
 static void prvPortStartFirstTask( void )\r
 {\r
+       /* Start the first task.  This also clears the bit that indicates the FPU is\r
+       in use in case the FPU was used before the scheduler was started - which\r
+       would otherwise result in the unnecessary leaving of space in the SVC stack\r
+       for lazy saving of FPU registers. */\r
        __asm volatile(\r
                                        " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
                                        " ldr r0, [r0]                  \n"\r
                                        " ldr r0, [r0]                  \n"\r
                                        " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
+                                       " mov r0, #0                    \n" /* Clear the bit that indicates the FPU is in use, see comment above. */\r
+                                       " msr control, r0               \n"\r
                                        " cpsie i                               \n" /* Globally enable interrupts. */\r
                                        " cpsie f                               \n"\r
                                        " dsb                                   \n"\r
@@ -342,6 +348,24 @@ BaseType_t xPortStartScheduler( void )
                        ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
                }\r
 \r
+               #ifdef __NVIC_PRIO_BITS\r
+               {\r
+                       /* Check the CMSIS configuration that defines the number of\r
+                       priority bits matches the number of priority bits actually queried\r
+                       from the hardware. */\r
+                       configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\r
+               }\r
+               #endif\r
+\r
+               #ifdef configPRIO_BITS\r
+               {\r
+                       /* Check the FreeRTOS configuration that defines the number of\r
+                       priority bits matches the number of priority bits actually queried\r
+                       from the hardware. */\r
+                       configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\r
+               }\r
+               #endif\r
+\r
                /* Shift the priority group value back to its position within the AIRCR\r
                register. */\r
                ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r