/*\r
- FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.\r
All rights reserved\r
\r
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
determined priority level. Sometimes it is necessary to turn interrupt off in\r
the CPU itself before modifying certain hardware registers. */\r
#define portCPU_IRQ_DISABLE() \\r
- __asm volatile ( "CPSID i" ); \\r
+ __asm volatile ( "CPSID i" ::: "memory" ); \\r
__asm volatile ( "DSB" ); \\r
__asm volatile ( "ISB" );\r
\r
#define portCPU_IRQ_ENABLE() \\r
- __asm volatile ( "CPSIE i" ); \\r
+ __asm volatile ( "CPSIE i" ::: "memory" ); \\r
__asm volatile ( "DSB" ); \\r
__asm volatile ( "ISB" );\r
\r
{ \\r
portCPU_IRQ_DISABLE(); \\r
portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \\r
- __asm( "DSB \n" \\r
- "ISB \n" ); \\r
+ __asm volatile ( "DSB \n" \\r
+ "ISB \n" ); \\r
portCPU_IRQ_ENABLE(); \\r
}\r
\r
\r
/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read\r
value. */\r
-// configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );\r
+ configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );\r
\r
/* Restore the clobbered interrupt priority register to its original\r
value. */\r
\r
/* Only continue if the CPU is not in User mode. The CPU must be in a\r
Privileged mode for the scheduler to start. */\r
- __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );\r
+ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );\r
ulAPSR &= portAPSR_MODE_BITS_MASK;\r
configASSERT( ulAPSR != portAPSR_USER_MODE );\r
\r
}\r
}\r
\r
- /* Will only get here if xTaskStartScheduler() was called with the CPU in\r
+ /* Will only get here if vTaskStartScheduler() was called with the CPU in\r
a non-privileged mode or the binary point register was not set to its lowest\r
possible value. prvTaskExitError() is referenced to prevent a compiler\r
warning about it being defined but not referenced in the case that the user\r
portCPU_IRQ_DISABLE();\r
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
__asm volatile ( "dsb \n"\r
- "isb \n" );\r
+ "isb \n" ::: "memory" );\r
portCPU_IRQ_ENABLE();\r
\r
/* Increment the RTOS tick. */\r
ulPortTaskHasFPUContext = pdTRUE;\r
\r
/* Initialise the floating point status register. */\r
- __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );\r
+ __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );\r
}\r
/*-----------------------------------------------------------*/\r
\r
ulReturn = pdFALSE;\r
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
__asm volatile ( "dsb \n"\r
- "isb \n" );\r
+ "isb \n" ::: "memory" );\r
}\r
portCPU_IRQ_ENABLE();\r
\r
this is not the case (if some bits represent a sub-priority).\r
\r
The priority grouping is configured by the GIC's binary point register\r
- (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest\r
+ (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest\r
possible value (which may be above 0). */\r
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );\r
}\r