Add additional memory barriers into ARM GCC asm code to ensure no re-ordering across...

[freertos] / FreeRTOS / Source / portable / GCC / ARM_CR5 / port.c

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c b/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c
index b7eab92bdd601f0222fa87c077dcfbcd2399b3f0..351d42203d80bff80b667f74ec508ab2e6a273ce 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c
@@ -1,5 +1,5 @@
 /*\r
-    FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+    FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.\r
     All rights reserved\r
 \r
     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
@@ -156,12 +156,12 @@ mode. */
 determined priority level.  Sometimes it is necessary to turn interrupt off in\r
 the CPU itself before modifying certain hardware registers. */\r
 #define portCPU_IRQ_DISABLE()                                                                          \\r
-       __asm volatile ( "CPSID i" );                                                                   \\r
+       __asm volatile ( "CPSID i" ::: "memory" );                                              \\r
        __asm volatile ( "DSB" );                                                                               \\r
        __asm volatile ( "ISB" );\r
 \r
 #define portCPU_IRQ_ENABLE()                                                                           \\r
-       __asm volatile ( "CPSIE i" );                                                                   \\r
+       __asm volatile ( "CPSIE i" ::: "memory" );                                              \\r
        __asm volatile ( "DSB" );                                                                               \\r
        __asm volatile ( "ISB" );\r
 \r
@@ -171,8 +171,8 @@ the CPU itself before modifying certain hardware registers. */
 {                                                                                                                                      \\r
        portCPU_IRQ_DISABLE();                                                                                  \\r
        portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;                   \\r
-       __asm(  "DSB            \n"                                                                                     \\r
-                       "ISB            \n" );                                                                          \\r
+       __asm volatile (        "DSB            \n"                                                             \\r
+                                               "ISB            \n" );                                                  \\r
        portCPU_IRQ_ENABLE();                                                                                   \\r
 }\r
 \r
@@ -357,7 +357,7 @@ uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */
 \r
                /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read\r
                value. */\r
-//             configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );\r
+               configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );\r
 \r
                /* Restore the clobbered interrupt priority register to its original\r
                value. */\r
@@ -367,7 +367,7 @@ uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */
 \r
        /* Only continue if the CPU is not in User mode.  The CPU must be in a\r
        Privileged mode for the scheduler to start. */\r
-       __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );\r
+       __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );\r
        ulAPSR &= portAPSR_MODE_BITS_MASK;\r
        configASSERT( ulAPSR != portAPSR_USER_MODE );\r
 \r
@@ -394,7 +394,7 @@ uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */
                }\r
        }\r
 \r
-       /* Will only get here if xTaskStartScheduler() was called with the CPU in\r
+       /* Will only get here if vTaskStartScheduler() was called with the CPU in\r
        a non-privileged mode or the binary point register was not set to its lowest\r
        possible value.  prvTaskExitError() is referenced to prevent a compiler\r
        warning about it being defined but not referenced in the case that the user\r
@@ -464,7 +464,7 @@ void FreeRTOS_Tick_Handler( void )
        portCPU_IRQ_DISABLE();\r
        portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
        __asm volatile (        "dsb            \n"\r
-                                               "isb            \n" );\r
+                                               "isb            \n" ::: "memory" );\r
        portCPU_IRQ_ENABLE();\r
 \r
        /* Increment the RTOS tick. */\r
@@ -488,7 +488,7 @@ uint32_t ulInitialFPSCR = 0;
        ulPortTaskHasFPUContext = pdTRUE;\r
 \r
        /* Initialise the floating point status register. */\r
-       __asm volatile ( "FMXR  FPSCR, %0" :: "r" (ulInitialFPSCR) );\r
+       __asm volatile ( "FMXR  FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -518,7 +518,7 @@ uint32_t ulReturn;
                ulReturn = pdFALSE;\r
                portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
                __asm volatile (        "dsb            \n"\r
-                                                       "isb            \n" );\r
+                                                       "isb            \n" ::: "memory" );\r
        }\r
        portCPU_IRQ_ENABLE();\r
 \r