Update version number to 9.0.0rc2.

[freertos] / FreeRTOS / Source / portable / GCC / MicroBlaze / port.c

diff --git a/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c b/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c
index 3ae975af79ce7871b33c142e999c5551752f3678..0ca17dd47162d336b06bca9270941a1045640d00 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c
+++ b/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c
@@ -1,5 +1,5 @@
 /*\r
-    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+    FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
     All rights reserved\r
 \r
     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
@@ -8,7 +8,7 @@
 \r
     FreeRTOS is free software; you can redistribute it and/or modify it under\r
     the terms of the GNU General Public License (version 2) as published by the\r
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
 \r
     ***************************************************************************\r
     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
@@ -84,6 +84,10 @@
 #include <xintc_i.h>\r
 #include <xtmrctr.h>\r
 \r
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )\r
+       #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port.\r
+#endif\r
+\r
 /* Tasks are started with interrupts enabled. */\r
 #define portINITIAL_MSR_STATE          ( ( StackType_t ) 0x02 )\r
 \r
@@ -99,7 +103,7 @@ to reach zero, so it is initialised to a high value. */
 debugging. */\r
 #define portISR_STACK_FILL_VALUE       0x55555555\r
 \r
-/* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task \r
+/* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task\r
 maintains it's own count, so this variable is saved as part of the task\r
 context. */\r
 volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;\r
@@ -117,10 +121,10 @@ uint32_t *pulISRStack;
 static void prvSetupTimerInterrupt( void );\r
 /*-----------------------------------------------------------*/\r
 \r
-/* \r
- * Initialise the stack of a task to look exactly as if a call to \r
+/*\r
+ * Initialise the stack of a task to look exactly as if a call to\r
  * portSAVE_CONTEXT had been made.\r
- * \r
+ *\r
  * See the header file portable.h.\r
  */\r
 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
@@ -129,16 +133,16 @@ extern void *_SDA2_BASE_, *_SDA_BASE_;
 const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;\r
 const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;\r
 \r
-       /* Place a few bytes of known values on the bottom of the stack. \r
+       /* Place a few bytes of known values on the bottom of the stack.\r
        This is essential for the Microblaze port and these lines must\r
-       not be omitted.  The parameter value will overwrite the \r
+       not be omitted.  The parameter value will overwrite the\r
        0x22222222 value during the function prologue. */\r
        *pxTopOfStack = ( StackType_t ) 0x11111111;\r
        pxTopOfStack--;\r
        *pxTopOfStack = ( StackType_t ) 0x22222222;\r
        pxTopOfStack--;\r
        *pxTopOfStack = ( StackType_t ) 0x33333333;\r
-       pxTopOfStack--; \r
+       pxTopOfStack--;\r
 \r
        /* First stack an initial value for the critical section nesting.  This\r
        is initialised to zero as tasks are started with interrupts enabled. */\r
@@ -261,7 +265,7 @@ void vPortEndScheduler( void )
 /*-----------------------------------------------------------*/\r
 \r
 /*\r
- * Manual context switch called by portYIELD or taskYIELD.  \r
+ * Manual context switch called by portYIELD or taskYIELD.\r
  */\r
 void vPortYield( void )\r
 {\r
@@ -280,7 +284,7 @@ extern void VPortYieldASM( void );
 /*-----------------------------------------------------------*/\r
 \r
 /*\r
- * Hardware initialisation to generate the RTOS tick.   \r
+ * Hardware initialisation to generate the RTOS tick.\r
  */\r
 static void prvSetupTimerInterrupt( void )\r
 {\r
@@ -295,12 +299,12 @@ UBaseType_t uxMask;
        XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );\r
        XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );\r
 \r
-       /* Set the timer interrupt enable bit while maintaining the other bit \r
+       /* Set the timer interrupt enable bit while maintaining the other bit\r
        states. */\r
        uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );\r
        uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;\r
-       XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );       \r
-       \r
+       XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );\r
+\r
        XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );\r
        XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );\r
        XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );\r
@@ -310,12 +314,12 @@ UBaseType_t uxMask;
 /*\r
  * The interrupt handler placed in the interrupt vector when the scheduler is\r
  * started.  The task context has already been saved when this is called.\r
- * This handler determines the interrupt source and calls the relevant \r
+ * This handler determines the interrupt source and calls the relevant\r
  * peripheral handler.\r
  */\r
 void vTaskISRHandler( void )\r
 {\r
-static uint32_t ulPending;    \r
+static uint32_t ulPending;\r
 \r
        /* Which interrupts are pending? */\r
        ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );\r
@@ -346,7 +350,7 @@ static uint32_t ulPending;
 }\r
 /*-----------------------------------------------------------*/\r
 \r
-/* \r
+/*\r
  * Handler for the timer interrupt.\r
  */\r
 void vTickISR( void *pvBaseAddress )\r
@@ -360,7 +364,7 @@ uint32_t ulCSR;
        }\r
 \r
        /* Clear the timer interrupt */\r
-       ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);     \r
+       ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);\r
        XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );\r
 }\r
 /*-----------------------------------------------------------*/\r