nesting variable is initialised to a non-zero value. */\r
#define portINITIAL_NESTING_VALUE ( 0xff )\r
\r
-/* The bit within the MSR register that enabled/disables interrupts. */\r
+/* The bit within the MSR register that enabled/disables interrupts and \r
+exceptions respectively. */\r
#define portMSR_IE ( 0x02U )\r
+#define portMSR_EE ( 0x100U )\r
\r
/* If the floating point unit is included in the MicroBlaze build, then the\r
FSR register is saved as part of the task context. portINITIAL_FSR is the value\r
*pxTopOfStack = ( StackType_t ) 0x00000000;\r
pxTopOfStack--;\r
\r
- #if XPAR_MICROBLAZE_0_USE_FPU != 0\r
+ #if( XPAR_MICROBLAZE_USE_FPU != 0 )\r
/* The FSR value placed in the initial task context is just 0. */\r
*pxTopOfStack = portINITIAL_FSR;\r
pxTopOfStack--;\r
disabled. Each task will enable interrupts automatically when it enters\r
the running state for the first time. */\r
*pxTopOfStack = mfmsr() & ~portMSR_IE;\r
+ \r
+ #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )\r
+ {\r
+ /* Ensure exceptions are enabled for the task. */\r
+ *pxTopOfStack |= portMSR_EE;\r
+ }\r
+ #endif\r
+\r
pxTopOfStack--;\r
\r
/* First stack an initial value for the critical section nesting. This\r