RISC-V port updates: The machine timer compare register can now be for any HART...

[freertos] / FreeRTOS / Source / portable / GCC / RISC-V / port.c

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/port.c b/FreeRTOS/Source/portable/GCC/RISC-V/port.c
index 1ab1c2e19cd1cec8e1c719a0272a513b8dea09cb..4cd9daa936ee784dd2a13fe7dd02df64e3018d9e 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/RISC-V/port.c
+++ b/FreeRTOS/Source/portable/GCC/RISC-V/port.c
@@ -75,7 +75,8 @@ void vPortSetupTimerInterrupt( void ) __attribute__(( weak ));
 uint64_t ullNextTime = 0ULL;\r
 const uint64_t *pullNextTime = &ullNextTime;\r
 const size_t uxTimerIncrementsForOneTick = ( size_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); /* Assumes increment won't go over 32-bits. */\r
-volatile uint64_t * const pullMachineTimerCompareRegister = ( volatile uint64_t * const ) ( configCLINT_BASE_ADDRESS + 0x4000 );\r
+volatile uint64_t * const pullMachineTimerCompareRegisterBase = ( volatile uint64_t * const ) ( configCLINT_BASE_ADDRESS + 0x4000 );\r
+volatile uint64_t * pullMachineTimerCompareRegister = 0;\r
 \r
 /* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task\r
 stack checking.  A problem in the ISR stack will trigger an assert, not call the\r
@@ -110,6 +111,10 @@ task stack, not the ISR stack). */
        uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;\r
        volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFFC );\r
        volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFF8 );\r
+       volatile uint32_t ulHartId = 0;\r
+\r
+               __asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) );\r
+               pullMachineTimerCompareRegister  = &( pullMachineTimerCompareRegisterBase[ ulHartId ] );\r
 \r
                do\r
                {\r