Basic 64-bit RISC-V port now functional. RISC-V port layer automatically switches...

[freertos] / FreeRTOS / Source / portable / GCC / RISC-V / portASM.S

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S b/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
index 68b6fa60706ccac48e1a4e3297f399cb819c98d9..4785ff0134dd019a161a85120107610d3de1099d 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
+++ b/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
@@ -56,15 +56,15 @@
  *\r
  */\r
 #if __riscv_xlen == 64\r
-    #define portWORD_SIZE 8\r
-    #define store_x sd\r
-    #define load_x ld\r
+       #define portWORD_SIZE 8\r
+       #define store_x sd\r
+       #define load_x ld\r
 #elif __riscv_xlen == 32\r
-    #define store_x sw\r
-    #define load_x lw\r
-    #define portWORD_SIZE 4\r
+       #define store_x sw\r
+       #define load_x lw\r
+       #define portWORD_SIZE 4\r
 #else\r
-    #error Assembler did not define __riscv_xlen\r
+       #error Assembler did not define __riscv_xlen\r
 #endif\r
 \r
 #include "freertos_risc_v_chip_specific_extensions.h"\r
@@ -95,7 +95,7 @@ at the top of this file. */
 .extern Timer_IRQHandler\r
 .extern pullMachineTimerCompareRegister\r
 .extern pullNextTime\r
-.extern ulTimerIncrementsForOneTick\r
+.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */\r
 .extern xISRStackTop\r
 \r
 /*-----------------------------------------------------------*/\r
@@ -145,7 +145,7 @@ freertos_risc_v_trap_handler:
        csrr a1, mepc\r
 \r
 test_if_asynchronous:\r
-       srli a2, a0, 0x1f                                       /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */\r
+       srli a2, a0, __riscv_xlen - 1           /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */\r
        beq a2, x0, handle_synchronous          /* Branch past interrupt handing if not asynchronous. */\r
        store_x a1, 0( sp )                                     /* Asynch so save unmodified exception return address. */\r
 \r
@@ -157,25 +157,40 @@ handle_asynchronous:
 \r
                addi t0, x0, 1\r
 \r
+               slli t0, t0, __riscv_xlen - 1   /* LSB is already set, shift into MSB.  Shift 31 on 32-bit or 63 on 64-bit cores. */\r
+               addi t1, t0, 7                                  /* 0x8000[]0007 == machine timer interrupt. */\r
+               bne a0, t1, test_if_external_interrupt\r
+\r
+               load_x t0, pullMachineTimerCompareRegister  /* Load address of compare register into t0. */\r
+               load_x t1, pullNextTime                 /* Load the address of ullNextTime into t1. */\r
+\r
                #if( __riscv_xlen == 32 )\r
-                       slli t0, t0, 31                         /* LSB is already set, shift into MSB. */\r
-                       addi t1, t0, 7                          /* 0x80000007 == machine timer interrupt. */\r
-                       bne a0, t1, test_if_external_interrupt\r
 \r
-                       lw t0, pullMachineTimerCompareRegister  /* Load address of compare register into t0. */\r
-                       lw t1, pullNextTime                     /* Load the address of ullNextTime into t1. */\r
+                       /* Update the 64-bit mtimer compare match value in two 32-bit writes. */\r
                        lw t2, 0(t1)                            /* Load the low word of ullNextTime into t2. */\r
                        lw t3, 4(t1)                            /* Load the high word of ullNextTime into t3. */\r
                        sw t2, 0(t0)                            /* Store low word of ullNextTime into compare register. */\r
                        sw t3, 4(t0)                            /* Store high word of ullNextTime into compare register. */\r
-                       lw t0, ulTimerIncrementsForOneTick      /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */\r
-                       add t4, t0, t2                          /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits. */\r
+                       lw t0, uxTimerIncrementsForOneTick      /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */\r
+                       add t4, t0, t2                          /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */\r
                        sltu t5, t4, t2                         /* See if the sum of low words overflowed (what about the zero case?). */\r
                        add t6, t3, t5                          /* Add overflow to high word of ullNextTime. */\r
                        sw t4, 0(t1)                            /* Store new low word of ullNextTime. */\r
                        sw t6, 4(t1)                            /* Store new high word of ullNextTime. */\r
+\r
                #endif /* __riscv_xlen == 32 */\r
 \r
+               #if( __riscv_xlen == 64 )\r
+\r
+                       /* Update the 64-bit mtimer compare match value. */\r
+                       ld t2, 0(t1)                            /* Load ullNextTime into t2. */\r
+                       sd t2, 0(t0)                            /* Store ullNextTime into compare register. */\r
+                       ld t0, uxTimerIncrementsForOneTick  /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */\r
+                       add t4, t0, t2                          /* Add ullNextTime to the timer increments for one tick. */\r
+                       sd t4, 0(t1)                            /* Store ullNextTime. */\r
+\r
+               #endif /* __riscv_xlen == 64 */\r
+\r
                load_x sp, xISRStackTop                 /* Switch to ISR stack before function call. */\r
                jal xTaskIncrementTick\r
                beqz a0, processed_source               /* Don't switch context if incrementing tick didn't unblock a task. */\r
@@ -212,8 +227,8 @@ as_yet_unhandled:
        j as_yet_unhandled\r
 \r
 processed_source:\r
-       load_x  sp, pxCurrentTCB                        /* Load pxCurrentTCB. */\r
-       load_x  sp, 0( sp )                                     /* Read sp from first TCB member. */\r
+       load_x  t1, pxCurrentTCB                        /* Load pxCurrentTCB. */\r
+       load_x  sp, 0( t1 )                                     /* Read sp from first TCB member. */\r
 \r
        /* Load mret with the address of the next instruction in the task to run next. */\r
        load_x t0, 0( sp )\r